JP2006156768A - Method of manufacturing semiconductor device, and the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily form a minute opening hole, to hardly cause disconnection, and to prevent the occurrence of reattaching phenomenon of an electrode due to over-etching. <P>SOLUTION: An organic system second insulating layer 22 is interposed between silicon system first insulating layer 21 and third insulating layer 23 so that an insulating film 20 can be formed, and anisotropic etching and etching whose anisotropy is strong are alternately repeated to the insulating film so that a stepped part 29 can be formed in the second insulating layer 22, and that a projecting hole 30 can be formed toward a substrate side. Then, a conductive material to be evaporated as a wiring connecting an electrode 1a of the circuit element 1 and the surface of the insulating film is integrated through a conductive material deposited on the stepped part 29. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  In the present invention, the surface of a substrate on which a circuit element including a semiconductor is formed is covered with an insulating material and planarized, and etching is performed on the insulating film to form a hole exposing a part of the circuit element. In a manufacturing method of a semiconductor device in which a conductive material is deposited so as to fill a gap and a conductive portion is formed to be electrically connected to a part of a circuit element, it is easy to form a hole with a small opening and does not cause poor contact of the wiring portion. In addition, the present invention relates to a technique for preventing the reattachment phenomenon of electrodes and the like from occurring.

  Among circuit elements formed on a substrate (wafer) of a semiconductor device, for example, a heterojunction bipolar transistor (hereinafter referred to as HBT) includes emitter, base, and collector layers, and electrodes formed on the surfaces of these layers. It has a mesa structure consisting of

  Each electrode of such a mesa-structured HBT has a relatively large step, and if an attempt is made to directly wire between the HBT and another circuit element formed on the same substrate, the wiring of the wiring is caused by the step. It causes disconnection.

  In order to solve this problem, conventionally, an uneven surface of a substrate on which a circuit element such as HBT is formed is covered with an insulating film made of an organic material having a low dielectric constant such as benzocyclobutene (BCB) or polyimide. The entire surface of the insulating film is flattened, a hole is formed in the insulating film by etching to expose the electrode portion of the circuit element, etc., and a metal or other conductive material is deposited inside the hole and the surface of the insulating film to insulate it. A wiring portion is formed which is electrically connected to the electrode portion of each circuit element from the surface side of the film.

  This hole can be obtained by performing anisotropic etching with, for example, a fluorine-based gas on an organic insulating film. However, when the hole is deep (when the insulating film is thick), a conductive material is deposited inside the hole. And a conductive material deposited around the hole on the surface of the insulating film, a gap is likely to occur, and disconnection occurs.

  As a method for solving this, a technique is known in which the hole is etched so that the opening on the electrode side is narrow and the opening on the surface side of the insulating film is tapered.

  FIG. 10 shows a manufacturing example. First, as shown in FIG. 10A, the electrode 1a of the circuit element 1 is covered with an organic insulating film 3 such as BCB and the entire surface thereof is flattened. Thereafter, a region of the surface excluding the hole formation scheduled portion (resist hole 4 a) is covered with the resist 4.

Next, as shown in FIGS. 10B and 10C, isotropic etching using a mixed gas of trifluoromethane (CHF ₃ ) and oxygen (O ₂ ) is performed, and the insulating film 3 is tapered. After the hole 3a is formed, the resist 4 is removed, and a conductive material is vapor deposited as shown in FIG.

  By forming the tapered hole 3a in this way, the conductive material is deposited not only on the surface of the electrode 1a of the circuit element 1 but also on the inclined surface of the hole 3a, and the surface of the insulating film 3 around the hole 3a is surrounded. A gap between the conductive materials is less likely to occur, and disconnection can be prevented.

  A technique for forming the wiring portion 5 after forming the tapered hole 3a in the organic insulating film 3 as described above is disclosed in, for example, the following Patent Document 1.

JP-A-6-291097

  However, in the method of forming the tapered hole 3a in the organic insulating film 3 by isotropic etching as described above, the resist 4 whose etching rate is the same as that of the insulating film 3 is also greatly retreated, and the target hole is more Since it becomes a large opening, there exists a problem that the hole of a minute opening cannot be provided close.

  In addition, when there is a step between the electrodes of the circuit element 1, the thickness of the insulating film 3 interposed between the electrodes from the surface of the insulating film 3 is different, but the etching time is set according to the portion where the film thickness is large Then, there is a problem that overetching occurs in the portion where the film thickness is small, and the electrode of the circuit element 1 is reattached to the side wall of the hole 3a or the resist 4 by resputtering or the like.

  The present invention solves these problems, and provides a method for manufacturing a semiconductor device and a semiconductor device that are easy to form a hole with a minute opening, are less likely to cause disconnection, and do not cause re-adhesion of electrodes and the like due to overetching. The purpose is to do.

In order to achieve the above object, a method of manufacturing a semiconductor device according to claim 1 of the present invention includes:
An insulating film forming step (S2) in which the surface of the substrate (10) on which the circuit element (1) including the semiconductor element is formed is covered with an insulating film and planarized, and the hole (30) is formed by etching the insulating film. Forming and exposing a part (1a) of the circuit element (S3), and depositing a conductive material (31) so as to fill the hole from the surface side of the insulating film; In a method for manufacturing a semiconductor device including a wiring part forming step (S4) for forming a wiring part (32) that is partially conductive,
The insulating film forming step includes
Covering the surface of the substrate with a silicon-based first insulating layer (S2a);
Covering the surface of the first insulating layer with an organic second insulating layer and planarizing the entire surface (S2b);
Covering the surface of the second insulating layer with a silicon-based third insulating layer (S2c),
The hole forming step includes
A step (S3a) of forming a resist (24) on a portion of the surface of the third insulating layer except a portion where the hole is to be formed;
A first etching step of performing an anisotropic etching process from the surface side of the resist to remove a portion of the third insulating layer not covered with the resist to expose the second insulating layer (S3b); When,
A second etching step of performing a highly anisotropic etching process from the resist surface side, removing the exposed second insulating layer to expose the first insulating layer, and receding the resist; S3c)
An anisotropic etching process is performed from the surface side of the resist, the exposed first insulating layer is removed to expose a part of the circuit element, and the recess of the third insulating layer is retreated. A third etching step (S3d) of removing a portion exposed from the resist, further forming a step (29) in the second insulating layer, and forming a convex hole toward the substrate; It is characterized by containing.

A method for manufacturing a semiconductor device according to claim 2 of the present invention is the method for manufacturing a semiconductor device according to claim 1,
The hole forming step includes
A fourth etching step (S3e) of performing a highly anisotropic etching process after the third etching step to move the position of the step portion of the second insulating layer to the first insulating layer side; It is characterized by being.

A method for manufacturing a semiconductor device according to claim 3 of the present invention is the method for manufacturing a semiconductor device according to claim 1 or 2,
The circuit element includes a heterojunction bipolar transistor, and an electrode of the transistor is a conduction target of the wiring portion.

Moreover, the manufacturing method of the semiconductor device of Claim 4 of this invention is the manufacturing method of the semiconductor device in any one of Claims 1-3,
The second insulating layer is formed of benzocyclobutene.

Moreover, the manufacturing method of the semiconductor device of Claim 5 of this invention is the manufacturing method of the semiconductor device in any one of Claims 1-4,
The first insulating layer and the third insulating layer are formed of any one of silicon oxide, silicon nitride, and silicon oxynitride.

Moreover, the manufacturing method of the semiconductor device of Claim 6 of this invention is the manufacturing method of the semiconductor device in any one of Claims 1-5,
The anisotropic etching in the first etching stage and the third etching stage is etching using a fluorine-based gas.

Moreover, the manufacturing method of the semiconductor device of Claim 7 of this invention is the manufacturing method of the semiconductor device in any one of Claims 1-6,
The highly anisotropic etching in the second etching stage and the fourth etching stage is etching using oxygen gas.

A semiconductor device according to claim 8 of the present invention is
It is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 7.

A semiconductor device according to claim 9 of the present invention is
A substrate (10) having a circuit element (1) formed on its surface;
An insulating film (20) covering the surface of the substrate;
A hole (30) formed by etching the insulating film and exposing a part of the circuit element;
In a semiconductor device having a wiring portion (32) formed by vapor deposition of a conductive material on the inside of the hole and the surface of the insulating film and conducting between the surface side of the insulating film and a part of the circuit element,
The insulating film is
A silicon-based first insulating layer (21) covering the surface of the substrate;
An organic second insulating layer (22) covering the first insulating layer and having a planarized surface;
A silicon-based third insulating layer (23) covering the second insulating layer,
The hole penetrating the insulating film is convex toward the substrate side, and the convex step (29) is formed in an intermediate portion of the second insulating layer. .

  As described above, in the method for manufacturing a semiconductor device according to the present invention, the insulating film is anisotropic with respect to the insulating film formed by sandwiching the organic second insulating layer between the silicon-based first and third insulating layers. Etching and etching with strong anisotropy are alternately performed, a stepped portion is formed in the middle portion of the second insulating layer, a convex hole is formed toward the substrate side, and a conductive material is deposited on the hole. The wiring part is formed.

  For this reason, the conductive material deposited on the bottom of the hole and the conductive material deposited on the surface of the insulating film are integrated via the conductive material deposited on the step portion, and reliable conduction can be obtained with a narrow opening. .

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a flowchart showing a method of manufacturing a semiconductor device to which the present invention is applied, and FIGS. 2 to 5 are local cross-sectional views of the semiconductor device during the manufacturing process. Hereinafter, an embodiment of the present invention will be described based on the flowchart of FIG. 1 and FIGS.

  First, as shown in FIG. 2, a circuit element 1 including HBT or the like is formed on a base substrate 10 (for example, a GaAs substrate) including its electrode 1a (S1).

Next, the process proceeds to the insulating film forming step S2. In this insulating film forming step, as shown in FIG. 3A, the surface of the circuit element 1 is covered with a silicon-based first insulating layer 21 having a predetermined thickness (for example, 150 nm) (S2a). As the silicon-based first insulating layer 21, any one of silicon oxide (SiO ₂ ), silicon nitride (SiN), and silicon oxynitride (SiNxOy) can be used. This process is performed by, for example, a well-known CVD method.

  Subsequently, as shown in FIG. 3B, an organic material such as BCB or polyimide described above is applied to the surface of the first insulating layer 21, and the surface is flattened by a centrifugal treatment to obtain an organic second material. The insulating layer 22 is formed (S2b). Here, the thickness of the second insulating layer 22 is set to, for example, 500 nm on the basis of the surface of the electrode 1a.

  Finally, as shown in FIG. 3C, the surface of the second insulating layer 22 is treated by the same process as the first insulating layer 21 to form a silicon-based third insulating layer having a predetermined thickness (for example, 275 nm). 23 (S2c). Thereby, the insulating film 20 having a three-layer structure is formed. The first insulating layer 21 and the third insulating layer 23 may have a multilayer structure as long as they are silicon-based.

  Next, the process proceeds to the hole forming step S3. In this hole formation step, first, as shown in FIG. 4A, a hole formation planned portion (portion exposed from the resist hole 24a) in the surface of the third insulating layer 23 is formed. A resist 24 is formed in the removed region (S3a).

Subsequently, anisotropic etching using a fluorine-based gas (SF ₆ ) is performed in the thickness direction, and a portion exposed from the resist hole 24a in the third insulating layer 23 is removed as shown in FIG. 4B. Then, a layer hole 23a continuous with the resist hole 24a is formed, and the second insulating layer 22 is exposed (S3b).

  Further, a reactive ion etching process (that is, an oxygen plasma etching process) with strong anisotropy using oxygen gas is performed, and the second insulating layer 22 is exposed from the layer hole 23a as shown in FIG. The part which has been removed is removed to form a layer hole 22a continuous with the layer hole 23a, and the first insulating layer 21 is exposed (S3c). Note that the highly anisotropic etching is an intermediate etching between isotropic etching and anisotropic etching, and the etching strength in the thickness direction is larger than the etching strength in the direction perpendicular thereto. is there.

  Therefore, the resist 24 is etched back by the ion component in the oblique direction as well as in the thickness direction by the oxygen gas.

  Further, since the silicon-based insulating layers 21 and 23 are not etched by oxygen plasma, the third insulating layer 23 serves as an etching mask when the second insulating layer 22 is etched. Further, since the ion component in the oblique direction does not easily reach the lower part of the layer hole, the insulating film 22 does not recede.

  Therefore, the size of the layer hole 22a of the second insulating layer 22 is equal to the size of the layer hole 23a of the third insulating layer 23 and extends from the resist hole 24a of the resist 24 in the state of FIG. There is no.

  Furthermore, even if the second insulating layer 22 is etched out, the first insulating layer 21 functions as an etching stopper layer, so that reattachment of the electrode 1a due to overetching can be prevented.

  Subsequently, an anisotropic etching process corresponding to a silicon-based film thickness of 400 nm is performed with a fluorine-based gas, and the first insulating layer 21 is removed and one electrode 1a of the circuit element 1 is removed as shown in FIG. The part is exposed (S3d).

  Since this etching process is anisotropic, the size of the layer hole 21a of the first insulating layer 21 is equal to the size of the lower part of the layer hole 22a of the second insulating layer 22, and the state shown in FIG. The size of the resist hole 24a is maintained.

  However, since the surface of the third insulating layer 23 is exposed as much as the resist 24 has retreated in the pretreatment, the layer hole 23a of the third insulating layer 23 extends to a position that coincides with the resist hole 24a.

  Then, as the layer hole 23a is enlarged, the second insulating layer 22 is also etched, the upper side of the layer hole 22a is enlarged, and a step portion 29 is formed at a position of 100 nm from the top.

  Subsequently, anisotropic etching using an oxygen gas equivalent to an organic film thickness of 100 nm is performed, and the step 29 of the second insulating layer 22 is lowered from the top to a depth of 200 nm as shown in FIG. (S3e).

  At this time, the resist 24 recedes, but the silicon-based third insulating layer 23 is not etched. Therefore, the etching of the second insulating layer 22 proceeds only in the depth direction, and this etching time is selected. Thus, the depth of the stepped portion 29 can be arbitrarily set. Note that when the second insulating layer 22 is thin, the fourth etching process can be omitted.

  Thus, after the convex hole 30 is formed toward the substrate side exposing a part of the electrode 1a, the resist 24 is removed (S3f), and the process proceeds to the wiring part forming step S4.

  In this wiring portion forming step S4, as shown in FIG. 5A, a conductive material 31 is deposited in and around the hole 30 from the surface side of the third insulating layer 23 (the deposition mask process is performed). Omitted).

  Here, the conductive material 31a deposited on the bottom of the hole 30 (that is, the surface of the electrode 1a), the conductive material 31b deposited on the step 29, and the conductive material 31c deposited on the surface of the third insulating layer 23 are: As shown in FIG. 5 (b), it accumulates upward with time and increases its thickness.

  When a predetermined time elapses, the conductive material 31a deposited on the bottom of the hole 30 and the conductive material 31b deposited on the stepped portion 29 overlap each other at the lateral positions to be surely integrated. In addition, the conductive material 31b deposited on the step portion 29 and the conductive material 31c deposited on the surface of the third insulating layer 23 also overlap each other at the lateral positions and are reliably integrated, as shown in FIG. As shown in c), the electrode 1a of the circuit element 1 and the surface of the third insulating layer 23 are connected by a conductive material that continues in a stepped manner along the inner periphery of the hole 30, and the electrode 1a is connected to the electrode 1a. Thus, the wiring part 32 that is electrically and reliably connected is formed.

  Thus, in the method of manufacturing a semiconductor device of the present invention, the insulating film 20 is formed by sandwiching the organic second insulating layer 22 between the silicon-based first insulating layer 21 and the third insulating layer 23, By alternately repeating anisotropic etching and strong anisotropic etching for the insulating film, the second insulating layer 22 has a stepped portion 29 and a convex hole 30 toward the substrate side. Is forming.

  For this reason, the conductive material vapor-deposited as the wiring part connecting the electrode 1a of the circuit element 1 and the surface of the insulating film is integrated through the conductive material deposited on the stepped part 29 to form a conductive path without disconnection. can do.

  Further, the size of the opening on the lower side of the convex hole 30 formed by etching is substantially equal to the initial resist hole, and the size of the opening on the upper side is small in the receding amount of the resist 24 and the first opening. 3 is not widened by the masking action of the insulating layer 23, so that a large number of wiring portions without disconnection can be provided in a narrow region with a minute opening, and can be applied to a highly integrated semiconductor device.

  Although the above example is an operation for one electrode 1a of the circuit element 1, the above processing steps can be used as they are even when wiring is performed on a plurality of electrodes having steps.

  As an example, a case where an emitter-up type HBT is formed as a circuit element 1 on a substrate 10 such as GaAs as shown in FIG. 6 and wiring to the base electrode 1a, the emitter electrode 1b and the collector electrode 1c is performed will be described. .

  In the insulating film forming step S2, as shown in FIGS. 7A to 7C, the surface of the circuit element 1 is covered with the first insulating layer 21 having a predetermined thickness of silicon (for example, 150 nm) as described above. Then, the surface of the first insulating layer 21 is covered with the organic second insulating layer 22 such as BCB, and the entire surface is flattened. Finally, the surface of the second insulating layer 22 is silicon-based. Is covered with a third insulating layer 23 having a predetermined thickness (for example, 275 nm).

  At this time, the thickness of the second insulating layer 22 varies depending on the height of each electrode. Here, the thickness of the portion overlapping the collector electrode 1c at the lowest position is set to 500 nm.

  In the hole forming step S3, first, as shown in FIG. 8A, a resist is formed on a portion of the surface of the third insulating layer 23 except for a hole formation scheduled portion (resist holes 24a to 24c). 24 is formed (S3a).

Subsequently, anisotropic etching with a fluorine-based gas (SF ₆ ) is performed, and portions exposed from the resist holes 24a to 24c in the third insulating layer 23 are removed as shown in FIG. 8B. Then, layer holes 23a to 23c continuous with the resist holes 24a to 24c are formed to expose the second insulating layer 22 (S3b).

  Further, a highly anisotropic etching process using oxygen gas is performed, and portions exposed from the layer holes 23a to 23c are removed from the second insulating layer 22 as shown in FIG. Layer holes 22a to 22c that are continuous with the holes 23a to 23c, respectively, are formed, and the first insulating layer 21 is exposed (S3c).

  At this time, the resist 24 recedes from the third insulating layer 23 in the same manner as described above, and the layer holes 23a to 23c widen. However, since the silicon-based insulating layers 21 and 23 are not etched by oxygen plasma, the second insulating layer 23 is formed. The layer 22 is etched using the third insulating layer 23 as an etching mask. Therefore, the size of each layer hole 22a-22c does not expand from the hole diameter of the resist holes 24a-24c in the state of FIG.

  Further, in the etching for the second insulating layer 22, the upper part of the emitter electrode 1b is completed first, then the upper part of the base electrode 1a is completed, and finally the upper part of the collector electrode 1c is completed. By the time the etching of the upper part of 1c is completed, the upper side of the emitter electrode 1b and the collect electrode 1a is over-etched, but the first insulating layer 21 covering the electrode surface serves as an etching stopper layer. Reattachment of the electrodes 1a and 1b due to etching can be prevented. Similarly, reattachment of the collector electrode 1c can be prevented.

  Subsequently, an anisotropic etching process corresponding to a silicon-based film thickness of 400 nm is performed with a fluorine-based gas, and exposed from the layer holes 22a to 22c in the first insulating layer 21, as shown in FIG. The layer portions 21a to 21c that are continuous with the layer holes 22a to 22c are formed, and a part of each of the electrodes 1a to 1c of the circuit element 1 is exposed (S3d).

  Since this etching process is anisotropic, the holes of the first insulating layer 21 do not expand beyond the holes of the second insulating layer 22, and the diameters of the holes of the resist 24 in the state of FIG. Maintained.

  On the other hand, since the surface of the third insulating layer 23 is exposed as much as the resist holes 24a to 24c are expanded by the pretreatment, the layer holes 23a to 23c of the third insulating layer 23 are respectively exposed to the resist holes 24a to 24a. It spreads to a position that matches 24c. Then, as the layer holes 23a to 23c are enlarged, the second insulating layer 22 is also etched, the upper side of the layer holes 22a to 22c is enlarged, and step portions 29a to 29c are formed at positions of 100 nm from the top, respectively. It will be.

  Subsequently, etching with strong anisotropy by oxygen gas corresponding to a thickness of 100 nm of the second insulating layer (organic film) is performed, and a step 29a of the second insulating layer 22 is performed as shown in FIG. ˜29c is lowered from the top to a depth of 200 nm (S3e).

  At this time, the resist holes 24a to 24c are widened, but the silicon-based third insulating layer 23 is not etched, so that the etching for the second insulating layer 22 proceeds only in the depth direction. Therefore, the depth of the step portions 29a to 29c can be arbitrarily set by selecting this etching time. Similarly to the above, when the second insulating layer 22 is entirely thin (that is, when the step between the electrodes is small), the fourth etching process can be omitted.

  In this process, the second insulating layer 22 on the upper side of the emitter electrode 1b at the highest position is thin, so that the etching proceeds to the lower end and the stepped portion 29b is eliminated, but the first insulating layer 21 remains without being etched. The first insulating layer 21 forms a step portion.

  In this way, a part of each of the electrodes 1a to 1c is exposed to form holes 30a to 30c having stepped portions therein, and then the resist 24 is removed as shown in FIG. 8 (f) (S3f ), The process proceeds to the wiring part forming step S4.

  In this wiring portion formation step S4, a conductive material is deposited in and around each of the holes 30a to 30c from the surface side of the third insulating layer 23 in a state shown in FIG. Is omitted).

  As described above, the conductive material deposited on the bottoms of the holes 30a and 30c (that is, the surfaces of the electrodes 1a and 1c) and the conductive material deposited on the stepped portions 29a and 29c by the vapor deposition process are lateral to each other. In the same manner, the conductive material deposited on the step portions 29a and 29c and the conductive material deposited around the holes 30a and 30c on the surface of the third insulating layer 23 are also integrated. Overlapping each other's side positions ensures integration.

  Therefore, the base electrode 1a and the collector electrode 1c of the circuit element 1 and the conductive material around the holes 30a and 30c are connected by a conductive material that continues in a stepped manner along the inner periphery of the holes 30a and 30c. As shown in FIG. 9, stepped wiring portions 32a and 32c that are electrically connected reliably are formed.

  In addition, in the hole 30b, the conductive material deposited on the surface of the emitter electrode 1b of the circuit element 1 and the conductive material deposited on the first insulating layer 21 overlap each other in a lateral position to ensure that The conductive material that is integrated and deposited on the first insulating layer 21 and the conductive material that is deposited around the hole 30b on the surface of the third insulating layer 23 also overlap each other at the lateral positions. Integrate securely.

  Therefore, the emitter electrode 1b of the circuit element 1 and the conductive material around the hole 30b are connected by a conductive material that continues in a stepped manner along the inner periphery of the hole 30b, as shown in FIG. Thus, the staircase-shaped wiring portion 32b that is electrically connected reliably is formed.

  In this way, the wiring portions 32a to 32c that are surely conductive can be formed even with respect to the plurality of electrodes 1a to 1c having steps, and since the opening does not widen, the wiring portions 32a to 32c are brought close to each other. Can be provided.

  The semiconductor device configured by the above method is highly reliable because the wiring portion is securely connected to the circuit element, and can be configured with a high degree of integration since the opening of the hole is small.

  In addition, each wiring part 32a-32c of the semiconductor device formed like FIG. 9 is wired, for example to the terminal for external connection (not shown), is resin-molded, and becomes an HBT element. In addition to the HBT, a semiconductor element in which circuit elements such as a diode, a resistor, and a capacitor are formed can also be formed with a wiring portion that is surely connected to each circuit element by the same process as described above.

The flowchart which shows the process sequence of embodiment of this invention. Sectional drawing for demonstrating the process of embodiment of this invention. Sectional drawing for demonstrating the process of embodiment of this invention. Sectional drawing for demonstrating the process of embodiment of this invention. Sectional drawing for demonstrating the process of embodiment of this invention. Sectional drawing for demonstrating the process of embodiment of this invention. Sectional drawing for demonstrating the process of embodiment of this invention. Sectional drawing for demonstrating the process of embodiment of this invention. Sectional drawing for demonstrating the process of embodiment of this invention. Sectional drawing for demonstrating the process of the conventional method

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Circuit element, 1a-1c ... Electrode, 10 ... Board | substrate, 20 ... Insulating film, 21 ... 1st insulating layer, 21a-21c ... Layer hole, 22 ... 2nd insulating layer, 22a-22c: Layer hole, 23: Third insulating layer, 23a-23c: Layer hole, 24: Resist, 24a-24c: Resist hole, 29, 29a-29c: Step, 30, 30a-30c ........ hole, 31, 31a-31c..conductive material, 32, 32a-32c..wiring part

Claims (9)

An insulating film forming step (S2) in which the surface of the substrate (10) on which the circuit element (1) including the semiconductor element is formed is covered with an insulating film and planarized, and the hole (30) is formed by etching the insulating film. Forming and exposing a part (1a) of the circuit element (S3), and depositing a conductive material (31) so as to fill the hole from the surface side of the insulating film; In a method for manufacturing a semiconductor device including a wiring part forming step (S4) for forming a wiring part (32) that is partially conductive,
The insulating film forming step includes
Covering the surface of the substrate with a silicon-based first insulating layer (S2a);
Covering the surface of the first insulating layer with an organic second insulating layer and planarizing the entire surface (S2b);
Covering the surface of the second insulating layer with a silicon-based third insulating layer (S2c),
The hole forming step includes
A step (S3a) of forming a resist (24) on a portion of the surface of the third insulating layer except a portion where the hole is to be formed;
A first etching step of performing an anisotropic etching process from the surface side of the resist to remove a portion of the third insulating layer not covered with the resist to expose the second insulating layer (S3b); When,
A second etching step of performing a highly anisotropic etching process from the resist surface side, removing the exposed second insulating layer to expose the first insulating layer, and receding the resist; S3c)
An anisotropic etching process is performed from the surface side of the resist, the exposed first insulating layer is removed to expose a part of the circuit element, and the recess of the third insulating layer is retreated. A third etching step (S3d) of removing a portion exposed from the resist, further forming a step (29) in the second insulating layer, and forming a convex hole toward the substrate; A method for manufacturing a semiconductor device, comprising: The hole forming step includes
A fourth etching step (S3e) of performing a highly anisotropic etching process after the third etching step to move the position of the step portion of the second insulating layer to the first insulating layer side; 2. The method of manufacturing a semiconductor device according to claim 1, wherein:   3. The method of manufacturing a semiconductor device according to claim 1, wherein the circuit element includes a heterojunction bipolar transistor, and an electrode of the transistor is a conduction target of the wiring portion.   The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating layer is formed of benzocyclobutene.   5. The semiconductor device according to claim 1, wherein the first insulating layer and the third insulating layer are formed of any one of silicon oxide, silicon nitride, and silicon oxynitride. Production method.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the anisotropic etching in the first etching stage and the third etching stage is etching using a fluorine-based gas.   The method for manufacturing a semiconductor device according to claim 1, wherein the highly anisotropic etching in the second etching stage and the fourth etching stage is etching using oxygen gas.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1. A substrate (10) having a circuit element (1) formed on its surface;
An insulating film (20) covering the surface of the substrate;
A hole (30) formed by etching the insulating film and exposing a part of the circuit element;
In a semiconductor device having a wiring portion (32) formed by vapor deposition of a conductive material on the inside of the hole and the surface of the insulating film and conducting between the surface side of the insulating film and a part of the circuit element,
The insulating film is
A silicon-based first insulating layer (21) covering the surface of the substrate;
An organic second insulating layer (22) covering the first insulating layer and having a planarized surface;
A silicon-based third insulating layer (23) covering the second insulating layer,
The hole penetrating the insulating film is convex toward the substrate side, and the convex step (29) is formed in an intermediate portion of the second insulating layer. Semiconductor device.

Images