JPH1012868A - Semiconductor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor in which no shortcircuit is generated in a bit line and a gate electrode even when the bit line contact is not alinged with the gate electrode significantly. SOLUTION: A gate electrode 3 is formed on a silicon substrate 1 with a gate oxide film in between. In addition, an overlaying oxide film 4 is formed on the gate electrode 3 and an overlaying nitride film 5 is formed thereon. Further, a side wall nitride film 7 is formed on the side surface of the gate electrode 3, overlaying oxide film 4 and overlaying nitride film 5 with a buffer oxide film 6 in between. Then, a part of the film 7 is formed into a step part 11 (a part deeper than the side surface of the film 5 on the side surface of the film 4). Thus, even when a part of a contact hole 8a of the bit line is formed on the gate electrode 3, no short circuit between the bit line 10 and gate electrode 3 is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a technique for opening a self-aligned contact.

[0002]

2. Description of the Related Art In recent years, with miniaturization of semiconductor elements, an interlayer insulating layer provided for electrical connection between a source / drain region of a MOS transistor formed on one main surface of a semiconductor substrate and a wiring has been developed. In the formed contact holes, it is becoming difficult to secure a sufficient alignment margin. Therefore, it has been studied to secure the margin by using a self-aligned contact technique using a sidewall made of a nitride film.

A method for manufacturing a semiconductor device using a self-aligned contact technique using a nitride film sidewall will be described below with reference to FIG.

FIG. 22 is a sectional view of a main part showing one step of a method of manufacturing a semiconductor device using the above method. In FIG. 22, reference numeral 51 denotes a silicon substrate, and 52 denotes a silicon substrate 5.
The gate oxide film 53 formed on the gate oxide film 1
The gate electrode 54 formed on the silicon substrate 51 through the gate electrode 2 is formed on the gate electrode 53 through the gate electrode 5.
An overlying oxide film 55 having substantially the same width as 3 is formed on the overlying oxide film 54 and is an overlying nitride film having substantially the same width as the gate electrode 53 similarly to the overlying oxide film 54.

Reference numeral 56 denotes a nitride film sidewall formed on the side surfaces of the gate electrode 53 and the overlying oxide film 54 and the overlying nitride film 55 via a buffer oxide film 57 made of a silicon oxide film. The formed TEOS (Tetra-Ethyl-Ortho S)
(Ilicate) An interlayer oxide film made of an oxide film, and 58 a is a bit line contact hole formed in the interlayer oxide film 58. Since the diameter of bit line contact hole 58a is reduced by nitride film sidewall 56, the alignment margin of bit line contact hole 58a is sufficiently maintained.

[0006]

However, in such a semiconductor device, the alignment error of the bit line contact hole 58a with respect to the gate electrode 53 becomes large, and as shown in FIG. 53, the interlayer oxide film 5 for forming the bit line contact hole 58a is formed.
As a result, the buffer oxide film 56 was also etched at the same time as the etching of FIG. 8, so that the gate electrode 53 and the bit line were frequently short-circuited.

The present invention has been made in view of the above points, and a semiconductor device in which a bit line and a gate electrode are not short-circuited even when an alignment error between a bit line contact hole and a gate electrode is large, and a manufacturing method thereof. The purpose is to obtain a method.

Further, the damage of the semiconductor substrate is reduced,
It is an object of the present invention to obtain a method for manufacturing a semiconductor device capable of forming a high-quality junction.

[0009]

A semiconductor device according to the present invention comprises: a gate electrode formed on a semiconductor substrate via a gate oxide film; a first insulating film formed on the gate electrode; A second insulating film formed on the first insulating film, and a gate insulating film and a side surface of the first and second insulating films on the semiconductor substrate with a third insulating film interposed therebetween. In addition, one part includes a sidewall formed above or below the second insulating film, and the sidewall has higher etching resistance than the third insulating film. .

Further, a part of the sidewall is formed on the gate electrode.

A gate electrode formed on the semiconductor substrate via a gate oxide film; a first insulating film formed on the gate electrode; and a second insulating film formed on the first insulating film. And a sidewall formed on a side surface of the gate electrode and the first and second insulating films via a third insulating film on the semiconductor substrate. A part of the fourth insulating film forming the side wall is formed above or below the second insulating film, and the fourth insulating film is formed of the third insulating film. It is characterized by having higher etching resistance than an insulating film.

Further, a part of the fourth insulating film constituting the sidewall is formed on the gate electrode.

A method for manufacturing a semiconductor device according to the present invention
A semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate oxide film; a first insulating film formed on the gate electrode; and a gate electrode formed on the first insulating film. A step of forming a third insulating film around the second insulating film, a step of forming an insulating film serving as a sidewall around the third insulating film, and forming the insulating film serving as the sidewall anisotropically. The step of forming the side wall by etching and exposing the third insulating film is provided.

Further, a gate electrode formed on the semiconductor substrate and on the semiconductor substrate via a gate oxide film, a first insulating film formed on the gate electrode, and the first insulating film Forming a third insulating film around the second insulating film formed on the film, forming a fourth insulating film serving as a sidewall around the third insulating film, Fifth, which becomes the sidewall around the insulating film of No. 4
Forming the insulating film, exposing the fifth insulating film by anisotropic etching to expose the fourth insulating film, and removing the fourth insulating film to form a sidewall. In addition, a step of exposing the third insulating film is provided.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view of a main part showing Embodiment 1 of the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor substrate. For example, in this embodiment, a silicon substrate is used. Reference numeral 2 denotes a gate oxide film formed on the silicon substrate 1 and reference numeral 3 denotes a gate electrode formed on the silicon substrate 1 via the gate oxide film 2, and has a width of, for example, about 0.30 μm.

Reference numeral 4 denotes a first insulating film formed on the gate electrode 3, which is an overlying oxide film made of a silicon oxide film in the present embodiment.
0.25 μm, and the film thickness is 500 to 1000 °. Reference numeral 5 denotes a second insulating film which is formed on the overlying oxide film 4 and which is wider than the overlying oxide film 4. In the present embodiment, an overlying nitride film made of a silicon nitride film is used. For example, its width is about 0.30 μm.

Reference numeral 6 denotes a third insulating film formed on the side surfaces of the gate electrode 3, the overlying oxide film 4, and the overlying nitride film 5. In the present embodiment, for example, a silicon oxide film having a width of 50 to 300 ° is used. Is a buffer oxide film composed of Reference numeral 7 denotes a side wall formed on the side surfaces of the gate electrode 3, the overlying oxide film 4 and the overlying nitride film 5 with the buffer oxide film 6 interposed therebetween.
A sidewall nitride film made of a silicon nitride film having a width of 800 °, one part of which is deeper than the side surface of the overlying nitride film 5 on the side surface of the overlying oxide film 4 (hereinafter referred to as a step portion 11). )).

Here, the buffer oxide film 6 may be in direct contact with the gate electrode 3 because the hot carrier resistance of the transistor is reduced when the sidewall nitride film 7 contacts the gate electrode 3. Plays a role in preventing.

Reference numeral 8 denotes an interlayer insulating film. In this embodiment, for example, TEOS (Tetra-Ethyl)
-Ortho Silicate) is an interlayer oxide film composed of an oxide film, 8a is a bit line contact hole which is a contact hole formed in the interlayer oxide film 8, and formed inside the bit line 10 and the silicon substrate 1 therein. A connection portion 9 for electrically connecting the source / drain region of the transistor to be formed is formed.

Next, a method of manufacturing the semiconductor device thus configured will be described with reference to FIGS.
2 to 9 show the semiconductor device according to the first embodiment in the order of steps.

First, as shown in FIG. 2, an insulating film 2a made of, for example, a silicon oxide film serving as a gate oxide film 2 is formed on a silicon substrate 1, and a conductive film serving as a gate electrode 3 is formed on the insulating film 2a. 3a, and an insulating film 4a made of, for example, a silicon oxide film which becomes the overlying oxide film 4 on the conductive film 3a, and an insulating film made of, for example, a silicon nitride film which becomes the overlying nitride film 5 on the insulating film 4a. The films 5a are stacked, and a resist 12 patterned in a shape corresponding to the gate electrode 3 is formed on the insulating film 5a.

Next, as shown in FIG. 3, the insulating film 4a and the insulating film 5a are patterned by using the resist 12 as a mask to form the overlying nitride film 5 and the overlying oxide film 4 having substantially the same width as the overlying nitride film. Is formed.
Next, as shown in FIG. 4, an insulating film 4b serving as an overlying oxide film is formed.
Is etched using an etchant such as HF to form a step portion 11 and an overlying oxide film 4. Next, as shown in FIG. 5, the gate electrode 3 is formed by anisotropically etching the conductive film 3a using the overlying nitride film 5 as a mask.

Next, as shown in FIG. 6, an insulating film 6a made of, for example, a silicon oxide film serving as the buffer oxide film 6 is formed on the insulating film 2a and the gate electrode 3 and the overlying oxide film 4 by the CVD method. An insulating film 7a made of, for example, a silicon nitride film to be a sidewall nitride film 7 is formed around the insulating nitride film 5 and around the insulating film 6a. Here, the insulating film 6a is formed to be thinner than the step with respect to the side surface of the overlying nitride film 5 on the side surface of the overlying oxide film 4, that is, the depth of the step portion 11 relative to the side surface of the overlying nitride film 5.

Here, the thicknesses of the insulating film 6a and the insulating film 7a are factors that determine the width of the sidewall nitride film 7, and the thicknesses of the insulating film 6a and the insulating film 7a are limited due to restrictions on the semiconductor device. It is determined. For example, assuming that the width of the gate electrode is about 0.30 μm, the thickness of the insulating film 6a is 50 to 30 μm.
0 °, the thickness of the insulating film 7a is 300 to 800 °, the step with respect to the side surface of the overlying nitride film 5 on the side surface of the overlying oxide film 4, that is, the etching amount of the overlying oxide film 4 is 100 to 500 °, and the film thickness of the overlying nitride film. Is preferably set to 500 to 1000 °.

Next, as shown in FIG. 7, the insulating film 7a is
The sidewall nitride film 7 is formed by etching back with a gas such as F4. At this time, the insulating film 2a
Is removed at the same time as the insulating film 6a formed on the surface of the silicon substrate 1 and the insulating film 2a in contact with the insulating film 6a. Next, an interlayer oxide film 8 is deposited on the silicon substrate 1 as shown in FIG. Next, as shown in FIG. 9, using the resist 13 as a mask,
By performing anisotropic etching with a gas such as C4F8,
A bit line contact hole 8a is opened in interlayer oxide film 8.

After the resist 13 is removed, a conductive film to be the bit line 10 and the connecting portion 9 is formed, and processed into a desired wiring shape to form a bit line, thereby obtaining the semiconductor device shown in FIG.

In the semiconductor device manufactured as described above, the bit line contact hole 8a and the gate electrode 3
Even if a portion of the bit line contact hole 8a is formed on the gate electrode 3, a portion of the bit line contact hole 8a on the gate electrode 3 is formed by the overlying nitride film 5 to form the gate electrode. 3 and the bit line contact hole 8 formed in the portion where the buffer oxide film 6 was formed.
In part a, the upper portion of the buffer oxide film 6 is etched at the time of its formation, but the progress of the etching toward the substrate is stopped by the sidewall nitride film 7 formed in the step portion 11, so that the gate oxide is removed. It does not reach the electrode 3.

Therefore, in the semiconductor device manufactured as described above, there is obtained an effect that the bit line 10 and the gate electrode 3 are not short-circuited.

In the above description, a part of the sidewall nitride film 7 is formed in the step portion 11. However, a part of the sidewall nitride film 7 may be formed on the overlying nitride film 5. Also in this case, the bit line 1
0 and the gate electrode 3 are not short-circuited.

Embodiment 2 FIG. FIG. 10 is a cross-sectional view of a main part showing one step in Embodiment 2 of the present invention, and is a cross-sectional view of a main part showing each step of Embodiment 1 and is shown in FIG. 7 in FIGS. The second embodiment is different from the first embodiment in that an insulating film 6a serving as a buffer oxide film is exposed instead of exposing the silicon substrate 1, corresponding to an etch back process of the sidewall nitride film 7. The only difference is that the other points are the same as in the first embodiment. Here, a part of each of the insulating film 6a and the insulating film 2a to be a gate oxide film is removed in the etching step for forming the bit line contact hole 8a shown in FIG.

More specifically, it is necessary to accurately control the time for anisotropic etching of the insulating film 7a to be a sidewall nitride film and to monitor a gas generated by etching the insulating film 7a. Then, the insulating film 6a serving as a buffer oxide film is exposed.

Also in the above case, the alignment error between the bit line contact hole 8a and the gate electrode 3 increases, and even when a part of the bit line contact hole 8a is formed on the gate electrode 3, this gate electrode 3 A portion of the upper bit line contact hole 8a does not reach the gate electrode 3 due to the overlying nitride film 5, and a portion of the bit line contact hole 8a formed in the portion where the buffer oxide film 6 was formed. During the formation, the upper portion of the buffer oxide film 6 is etched, but the progress of the etching toward the substrate is stopped by the sidewall nitride film 7 formed on the step portion 11, so that the gate electrode 3 Do not reach.

Therefore, in the semiconductor device manufactured as described above, the effect that the bit line 10 and the gate electrode 3 are not short-circuited is obtained.

In the above description, a part of the side wall nitride film 7 is formed in the step portion 11. However, a part of the side wall nitride film 7 may be formed on the overlying nitride film 5. In this case, the bit line 10 and the gate electrode 3 are not short-circuited as described above.

Further, in the step of etching back the sidewall nitride film 7, the silicon substrate 1 is not exposed, and a part of each of the insulating film 6a and the insulating film 2a is removed by etching when forming the bit line contact hole 8a. So that damage to the silicon substrate 1 can be reduced,
Therefore, high-quality bonding can be formed.

Embodiment 3 Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. FIG. 11 is a cross-sectional view of a main part of a third embodiment of the present invention. In FIG. 11, reference numeral 1 denotes a semiconductor substrate. For example, in this embodiment, a silicon substrate is used.
Reference numeral 2 denotes a gate oxide film formed on the silicon substrate 1 and reference numeral 3 denotes a gate electrode formed on the silicon substrate 1 via the gate oxide film 2, and has a width of, for example, about 0.30 μm.

Reference numeral 4 denotes a first insulating film formed on the gate electrode 3, which is an overlying oxide film made of a silicon oxide film in the present embodiment.
0.25 μm, and the film thickness is 500 to 1000 °. Reference numeral 5 denotes a second insulating film which is formed on the overlying oxide film 4 and which is wider than the overlying oxide film 4. In the present embodiment, an overlying nitride film made of a silicon nitride film is used. For example, its width is about 0.30 μm.

Reference numeral 6 denotes a third insulating film formed on the side surfaces of the gate electrode 3, the overlying oxide film 4, and the overlying nitride film 5. In the present embodiment, for example, a silicon oxide film having a width of 50 to 300 ° is used. Is a buffer oxide film composed of

Reference numeral 7 denotes a side wall formed on the side surfaces of the gate electrode 3, the overlying oxide film 4 and the overlying nitride film 5 with the buffer oxide film 6 interposed therebetween, for example, 150 to 500.degree.
Insulating film 14 which is a side wall nitride film made of a silicon nitride film having a width of 50 nm, and a fifth insulating film 14 which is a side wall oxide film made of a silicon oxide film having a width of, for example, 100 to 300 ° formed on the side surface thereof. And the insulating film 15. Here, the sidewall nitride film 1
Part 4 is formed in a portion (hereinafter, referred to as a step portion 11) which is deeper than the side surface of the overlying nitride film 5 on the side surface of the overlying oxide film 4.

In this case, the buffer oxide film 6 directly contacts the gate electrode 3 because the hot carrier resistance of the transistor is reduced when the sidewall nitride film 14 contacts the gate electrode 3. It plays a role in preventing you from doing so.

Reference numeral 8 denotes an interlayer insulating film. In this embodiment, for example, TEOS (Tetra-Ethyl)
-Ortho Silicate) is an interlayer oxide film composed of an oxide film, 8a is a bit line contact hole which is a contact hole formed in the interlayer oxide film 8, and formed inside the bit line 10 and the silicon substrate 1 therein. A connection portion 9 for electrically connecting the source / drain region of the transistor to be formed is formed.

Next, a method of manufacturing the semiconductor device thus configured will be described with reference to FIGS. 12 to 19 show the semiconductor device according to the third embodiment in the order of steps.

First, as shown in FIG. 12, an insulating film 2a made of, for example, a silicon oxide film serving as a gate oxide film 2 is formed on a silicon substrate 1, and a conductive film serving as a gate electrode 3 is formed on the insulating film 2a. 3a, and an insulating film 4a made of, for example, a silicon oxide film which becomes the overlying oxide film 4 on the conductive film 3a, and an insulating film made of, for example, a silicon nitride film which becomes the overlying nitride film 5 on the insulating film 4a. The films 5a are stacked, and a resist 12 patterned in a shape corresponding to the gate electrode 3 is formed on the insulating film 5a.

Next, as shown in FIG. 13, the insulating film 4a and the insulating film 5a are patterned by using the resist 12 as a mask to form the overlying nitride film 5 and the overlying oxide film 4 having substantially the same width as the overlying nitride film. Is formed. Next, as shown in FIG. 14, the insulating film 4b to be the overlying oxide film is isotropically etched using an etchant such as HF to form the step portion 11 and the overlying oxide film 4 is formed. Next, as shown in FIG. 15, the gate electrode 3 is formed by anisotropically etching the conductive film 3a using the overlying nitride film 5 as a mask.

Next, as shown in FIG. 16, an insulating film 6a made of, for example, a silicon oxide film serving as the buffer oxide film 6 is formed on the insulating film 2a and the gate electrode 3 and the overlying oxide film 4 by the CVD method. An insulating film 14a which is formed around the overlying nitride film 5 and which forms the sidewall 7 in the subsequent process, for example, a silicon nitride film is formed around the insulating film 6a. Then, an insulating film 15a serving as a sidewall oxide film made of, for example, a silicon oxide film is formed around the insulating film 15a. Here, the insulating film 6a is formed of the overlying nitride film 5 on the side surface of the overlying oxide film 4.
, That is, a depth smaller than the depth of the overlying nitride film 5 on the side surface of the step portion 11.

Here, the thickness of the insulating film 6a, the insulating film 14a and the insulating film 15a is a factor that determines the width of the side wall 7, and due to restrictions on the semiconductor device, the insulating film 6a, the insulating film 14a and The thickness of the insulating film 15a is determined. For example, if the width of the gate electrode is about 0.30 μm,
The thickness of the insulating film 6a is 50 to 300 °, the thickness of the insulating film 14a is 150 to 500 °, and the thickness of the insulating film 15a is 100 to
300 °, the step with respect to the side surface of the overlying nitride film 5 on the side surface of the overlying oxide film 4, that is, the etching amount of the overlying oxide film 4 is 1
00 to 500 °, and the thickness of the overlying nitride film is set to 500 to 500 °.
Preferably it is 1000 °.

Next, as shown in FIG. 17, the insulating film 14a
The sidewall 7 is formed by etching back the insulating film 15a with a gas such as CF4. At this time, the insulating film 6a formed on the surface of the insulating film 2a and the insulating film 2a in contact with the insulating film 6a are also removed at the same time, so that a part of the surface of the silicon substrate 1 is exposed. Next, an interlayer oxide film 8 is deposited on the silicon substrate 1 as shown in FIG. Next, as shown in FIG. 19, a bit line contact hole 8a is opened in the interlayer oxide film 8 by performing anisotropic etching with a gas such as C4F8 using the resist 13 as a mask.

After the resist 13 is removed, a conductive film to be the bit line 10 and the connecting portion 9 is formed, and processed into a desired wiring shape to form a bit line, thereby obtaining the semiconductor device shown in FIG.

In the semiconductor device manufactured as described above, the bit line contact hole 8a and the gate electrode 3
Even if a portion of the bit line contact hole 8a is formed on the gate electrode 3, a portion of the bit line contact hole 8a on the gate electrode 3 is formed by the overlying nitride film 5 to form the gate electrode. 3 and the bit line contact hole 8 formed in the portion where the buffer oxide film 6 was formed.
In part a, the upper portion of the buffer oxide film 6 is etched at the time of its formation, but the progress of the etching toward the substrate is stopped by the sidewall nitride film 14 formed in the stepped portion 11, so that the gate oxide is removed. It does not reach the electrode 3.

Therefore, in the semiconductor device manufactured as described above, there is obtained an effect that the bit line 10 and the gate electrode 3 are not short-circuited.

In the above description, a part of the sidewall nitride film 14 is formed in the stepped portion 11, but a part of the sidewall nitride film 14 may be formed on the overlying nitride film 5, Also in this case, the bit line 10 and the gate electrode 3 are not short-circuited, as described above.

Embodiment 4 FIG. 20 and 21 are main-portion cross-sectional views showing one process in Embodiment 4 of the present invention, and are main-portion cross-sectional views showing each process in Embodiment 3, and FIGS. 17 corresponds to the etch back process of the sidewall 7 shown in FIG. The fourth embodiment differs from the third embodiment in that, instead of exposing the silicon substrate 1, first, as shown in FIG. 20, an insulating film 15a serving as a side wall oxide film is etched back to form a side wall nitride film. 21 except that the insulating film 14a serving as a buffer oxide film is exposed by removing the insulating film 14a serving as a sidewall nitride film as shown in FIG. The other points are the same as in the third embodiment. Here, a part of each of the insulating film 6a and the insulating film 2a to be a gate oxide film is removed in the etching step for forming the bit line contact hole 8a shown in FIG.

More specifically, the insulating film 15a to be a side wall oxide film and the insulating film 1 to be a side wall nitride film
4a to accurately control the time of anisotropic etching,
By monitoring the gas generated by etching these insulating films 15a and 14a, the insulating film 6a serving as a buffer oxide film is exposed.

Also in the above case, the alignment error between the bit line contact hole 8a and the gate electrode 3 increases, and even when a part of the bit line contact hole 8a is formed on the gate electrode 3, this gate electrode 3 A portion of the upper bit line contact hole 8a does not reach the gate electrode 3 due to the overlying nitride film 5, and a portion of the bit line contact hole 8a formed in the portion where the buffer oxide film 6 was formed. Is formed, the upper portion of the buffer oxide film 6 is etched, but the progress of the etching toward the substrate is stopped by the sidewall nitride film 14 formed in the step portion 11, so that the gate electrode 3 Do not reach.

Therefore, in the semiconductor device manufactured as described above, there is obtained an effect that the bit line 10 and the gate electrode 3 are not short-circuited.

Further, in the step of etching back the sidewall 7, the silicon substrate 1 is not exposed, and the insulating film 6a and the insulating film 2a to be the gate oxide film are removed by etching when the bit line contact hole 8a is formed. Therefore, damage to the silicon substrate 1 can be reduced, and therefore, high-quality bonding can be formed.

[0057]

According to the present invention, there is provided a semiconductor device comprising: a gate electrode formed on a semiconductor substrate via a gate oxide film;
A first insulating film formed on the gate electrode, a second insulating film formed on the first insulating film, and the gate electrode and the first and second insulating films on the semiconductor substrate; A portion formed on the side surface of the insulating film with the third insulating film interposed therebetween, and a portion provided with a sidewall formed above or below the second insulating film, wherein the side wall is formed of the third insulating film; Since the etching resistance is higher than that of the insulating film, the bit line and the gate electrode are not short-circuited even when the alignment error between the bit line contact hole and the gate electrode is large.

Further, a gate electrode formed on a semiconductor substrate via a gate oxide film, a first insulating film formed on the gate electrode, and a second insulating film formed on the first insulating film. And a sidewall formed on a side surface of the gate electrode and the first and second insulating films via a third insulating film on the semiconductor substrate. A part of the fourth insulating film forming the side wall is formed above or below the second insulating film, and the fourth insulating film is formed of the third insulating film. Since the etching resistance is higher than that of the insulating film, the bit line and the gate electrode are not short-circuited even when the alignment error between the bit line contact hole and the gate electrode is large.

A method of manufacturing a semiconductor device according to the present invention
A semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate oxide film; a first insulating film formed on the gate electrode; and a gate electrode formed on the first insulating film. A step of forming a third insulating film around the second insulating film, a step of forming an insulating film serving as a sidewall around the third insulating film, and forming the insulating film serving as the sidewall anisotropically. Since the sidewall is formed by etching and the step of exposing the third insulating film is provided, there is an effect that damage to the semiconductor substrate can be suppressed and a high-quality junction can be formed.

Further, a gate electrode formed on the semiconductor substrate and the semiconductor substrate via a gate oxide film, a first insulating film formed on the gate electrode, and the first insulating film Forming a third insulating film around the second insulating film formed on the film, forming a fourth insulating film serving as a sidewall around the third insulating film, Fifth, which becomes the sidewall around the insulating film of No. 4
Forming the insulating film, exposing the fifth insulating film by anisotropic etching to expose the fourth insulating film, and removing the fourth insulating film to form a sidewall. In addition, since the step of exposing the third insulating film is provided, there is an effect that damage to the semiconductor substrate can be suppressed and a high-quality junction can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part showing a first embodiment of the present invention.

FIG. 2 is an essential part cross sectional view showing the first embodiment of the present invention in the order of steps;

FIG. 3 is an essential part cross sectional view showing the first embodiment of the present invention in the order of steps;

FIG. 4 is an essential part cross sectional view showing the first embodiment of the present invention in the order of steps;

FIG. 5 is an essential part cross sectional view showing the first embodiment of the present invention in the order of steps;

FIG. 6 is an essential part cross sectional view showing the first embodiment of the present invention in the order of steps;

FIG. 7 is an essential part cross sectional view showing the first embodiment of the present invention in the order of steps;

FIG. 8 is an essential part cross sectional view showing the first embodiment of the present invention in the order of steps;

FIG. 9 is an essential part cross sectional view showing Embodiment 1 of the present invention in the order of steps;

FIG. 10 is an essential part cross sectional view showing one step in Embodiment 2 of the present invention;

FIG. 11 is an essential part cross sectional view showing Embodiment 3 of the present invention in the order of steps;

FIG. 12 is an essential part cross sectional view showing a third embodiment of the present invention in the order of steps;

FIG. 13 is an essential part cross sectional view showing a third embodiment of the present invention in the order of steps;

FIG. 14 is an essential part cross sectional view showing Embodiment 3 of the present invention in the order of steps;

FIG. 15 is an essential part cross sectional view showing Embodiment 3 of the present invention in the order of steps;

FIG. 16 is an essential part cross sectional view showing Embodiment 3 of the present invention in the order of steps;

FIG. 17 is an essential part cross sectional view showing Embodiment 3 of the present invention in the order of steps;

FIG. 18 is an essential part cross sectional view showing Embodiment 3 of the present invention in the order of steps;

FIG. 18 is an essential part cross sectional view showing Embodiment 3 of the present invention in the order of steps;

FIG. 20 is an essential part cross sectional view showing one step in Embodiment 4 of the present invention;

FIG. 21 is an essential part cross sectional view showing one step in Embodiment 4 of the present invention;

FIG. 22 is an essential part cross sectional view showing one step of a conventional semiconductor device manufacturing method;

FIG. 23 is an essential part cross sectional view showing a case where a bit line contact hole runs over a gate electrode in one step of a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 2 gate insulating film, 3 gate electrode, 4 first insulating film, 5 second insulating film, 6,
6a Third insulating film, 7 side wall, 7a insulating film to be a side wall, 14, 14a fourth insulating film, 15, 15a fifth insulating film.

Claims (6)

[Claims] A gate electrode formed on the semiconductor substrate via a gate oxide film; a first insulating film formed on the gate electrode; and a second electrode formed on the first insulating film. An insulating film formed on the side surface of the gate electrode and the first and second insulating films via the third insulating film on the semiconductor substrate; And a sidewall formed above or below, wherein the sidewall has higher etching resistance than the third insulating film. 2. The semiconductor device according to claim 1, wherein a part of the sidewall is formed on the gate electrode. 3. A gate electrode formed on a semiconductor substrate via a gate oxide film, a first insulating film formed on the gate electrode, and a second insulating film formed on the first insulating film. And a sidewall formed on a side surface of the gate electrode and the first and second insulating films via a third insulating film on the semiconductor substrate. And a fifth insulating film, a part of the fourth insulating film constituting the sidewall is formed above or below the second insulating film, and the fourth insulating film is formed of a third insulating film. A semiconductor device having higher etching resistance than a film. 4. The semiconductor device according to claim 3, wherein a part of the fourth insulating film forming the sidewall is formed on the gate electrode. 5. A semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, a first insulating film formed on the gate electrode, and the first insulating film Forming a third insulating film around the second insulating film formed thereon, forming an insulating film serving as a sidewall around the third insulating film, insulating the sidewall; A method for manufacturing a semiconductor device, comprising a step of forming a sidewall by anisotropically etching a film and exposing the third insulating film. 6. A semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate oxide film, a first insulating film formed on the gate electrode, and the first insulating film. A third insulating film is formed around the second insulating film formed on the film.
Forming a fourth insulating film serving as a sidewall around the third insulating film; forming a fifth insulating film serving as the sidewall around the fourth insulating film By anisotropically etching the fifth insulating film,
A method of manufacturing a semiconductor device, comprising: exposing the fourth insulating film; forming a sidewall by removing the fourth insulating film; and exposing the third insulating film.