JPH0823034A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To sufficiently flatten the surface of a semiconductor substrate or of an interlayer insulating film after embedding a conductive layer in a trench or a contact hole. CONSTITUTION:A silicon nitride film 22 is formed on the surface of a silicon substrate 21, a TEOS film is formed on this silicon nitride film 22 followed by providing the silicon nitride film 22, the TEOS film and the silicon substrate 21 with the first and second opening hole parts and a trench 21a. Next, a second polysilicon film 27 is accumulated in the first and second opening hole parts and in the trench 21a and the TEOS film followed by etching the second polysilicon film 27 so as to position the surface of the polysilicon film 27 on the first opening hole part in order to remove the TEOS film. Next, a thickness for etching of the polysilicon film 27 is set up to the film thickness of the silicon nitride film 22 so as to subject the polysilicon film 27 to isotropic etching. Next, the silicon nitride film 22 is removed. Accordingly, the surface of the semiconductor substrate is sufficiently flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device capable of flattening the surface of a semiconductor substrate or an interlayer insulating film after a conductive layer is buried in a trench or a contact hole.

[0002]

20 to 27 are sectional views showing a conventional method of manufacturing a trench capacitor. First, the interlayer insulating film 2 made of a silicon oxide film, a silicon nitride film, or a laminated film thereof is provided on the surface of the silicon substrate 1. After this, as shown in FIG. 21, a resist film 3 is formed on this interlayer insulating film 2. Next, as shown in FIG. 22, the interlayer insulating film 2 is etched using the resist film 3 as a mask. After that, as shown in FIG. 23, the resist film 3 is removed. Next, by etching using the interlayer insulating film 2 as a mask, a trench 1a is formed in the silicon substrate 1.

Thereafter, as shown in FIG. 24, an insulating film 4 is provided on the inner surface of the trench 1a. Next, a polysilicon film (not shown) is formed in the trench 1a by the CVD method, and the polysilicon film is brought into contact with the silicon substrate 1. After that, an NO film (not shown) is formed as a capacitor insulating film on the polysilicon film.

Next, as shown in FIG. 25, the NO film,
A conductive layer 5 made of polysilicon is deposited on the insulating film 4 and the interlayer insulating film 2. Thereafter, as shown in FIG. 26, this conductive layer 5 is isotropically etched so as to have the same height as the surface of silicon substrate 1. Next, as shown in FIG. 27, the interlayer insulating film 2 is removed.

By the way, in the above-mentioned conventional method for manufacturing a trench capacitor, an interlayer insulating film is formed by etching when forming the trench 1a in the silicon substrate 1 and pretreatment for depositing the conductive layer 5, for example, cleaning treatment in the trench 1a. 2 is etched. This causes variations in the thickness of the interlayer insulating film 2. Therefore, the deposited conductive layer 5
26 and the height of the conductive layer 5 after the conductive layer 5 is etched so as to have the same height as the surface of the silicon substrate 1 also varies as shown in FIG. As a result, as shown in FIG. 27, there is a problem in the flatness of the surface of the silicon substrate 1.

Further, when the conductive layer 5 is etched to have the same height as the surface of the silicon substrate 1, the interlayer insulating film 2 is formed.
In order to prevent the etching residue of the conductive layer 5 from occurring above, it is necessary to set the etching amount larger than the amount corresponding to the surface of the silicon substrate 1. That is, the conductive layer 5 is overlaid.
Needs to be etched. As a result, as shown in FIG. 27, a step is generated between the surface of the silicon substrate 1 and the conductive layer 5 in the trench 1a, which causes a problem in the flatness of the surface of the silicon substrate 1. Along with this, there is the step,
It is necessary to reduce the lateral dimension due to miniaturization,
Also, it is necessary to secure a certain thickness or more of the interlayer insulating film in order to reduce the wiring capacitance.
There is a problem that the aspect ratio of the module becomes large. Specifically, when a sputtered conductive film is formed on the step, the coverage of the sputtered conductive film is poor, so that there is a problem that a step break occurs at the stepped portion. Further, when an interlayer insulating film is provided on the step and a contact hole located on the step is formed in the interlayer insulating film, a necessary amount of etching the interlayer insulating film varies depending on the depth of the step. This causes generation of etching residue or ground removal in the step portion. Further, when a word line, a contact, or the like is processed in the upper layer of the step portion, the conductive film remains in the step, which causes a short. Therefore, such poor flatness becomes a factor that severes the processing in the post process.

28 to 32 are sectional views showing a conventional method of manufacturing a semiconductor device, showing a method of burying a conductive layer in a contact hole. First, the metal wiring 11
An interlayer insulating film 12 is deposited on the above. Next, as shown in FIG. 29, a resist film 1 is formed on the interlayer insulating film 12.
3 is provided. Then, as shown in FIG. 30, contact hole 12a is formed in interlayer insulating film 12 by etching using resist film 13 as a mask.

Next, as shown in FIG. 31, the resist film 13 is removed, and a conductive layer 14 made of polysilicon is deposited in the contact hole 12a and on the interlayer insulating film 12. Thereafter, as shown in FIG. 32, conductive layer 14 is etched to have the same height as interlayer insulating film 12.

In the conventional method of manufacturing a semiconductor device, when the conductive layer 14 is etched to have the same height as the surface of the interlayer insulating film 12, an etching residue of the conductive layer 14 is left on the interlayer insulating film 12. To avoid
It is necessary to set the etching amount larger than the amount corresponding to the surface of the interlayer insulating film 12. That is, the conductive layer 14 must be over-etched. As a result, as shown in FIG. 32, a step is generated between the surface of the interlayer insulating film 12 and the conductive layer 14 in the contact hole 12a, and the surface of the interlayer insulating film 12 cannot be sufficiently flattened. The problem due to the inability to be planarized is the same as that of the conventional method of manufacturing a trench capacitor. Therefore, such poor flatness becomes a factor that severes the processing in the post process.

[0010]

In the conventional method of manufacturing a trench capacitor and the method of manufacturing a semiconductor device described above, a conductive layer is buried in a trench formed in a silicon substrate and in a contact hole formed in an interlayer insulating film. At this time, the height of the embedded conductive layer varies. As a result, there arises a problem that the surfaces of the silicon substrate and the interlayer insulating film cannot be sufficiently flattened and made uniform.

The present invention has been made in consideration of the above circumstances, and an object thereof is to sufficiently form a surface of a semiconductor substrate or an interlayer insulating film after a conductive layer is buried in a trench or a contact hole. An object of the present invention is to provide a method for manufacturing a semiconductor device that can be planarized.

[0012]

In order to solve the above problems, the present invention provides a step of forming a first interlayer film on the surface of a semiconductor substrate, and a second interlayer film on the first interlayer film. Forming a film; forming a groove in the first and second interlayer films and the semiconductor substrate; depositing a conductive layer in the groove and on the second interlayer film; So that the surface of the conductive layer is located between the second interlayer films,
Etching the conductive layer, removing at least the second interlayer film in the vicinity of the groove, and setting a thickness at which the conductive layer is etched to a film thickness of the first interlayer film, And a step of isotropically etching the conductive layer.

Further, the method is characterized by further including a step of removing the first interlayer film after the step of isotropically etching the conductive layer. Further, a step of forming a first interlayer film on the wiring, a step of forming a second interlayer film on the first interlayer film, and a step of forming a third interlayer film on the second interlayer film.
Forming an interlayer film, forming a contact hole in the first to third interlayer films, and depositing a conductive layer in the contact hole and on the third interlayer film,
Etching the conductive layer so that the surface of the conductive layer is located between the third interlayer films in the contact holes, and removing the third interlayer film at least near the contact holes. Setting the thickness of the conductive layer to be etched to the thickness of the second interlayer film and isotropically etching the conductive layer. Further, the method is characterized by further including a step of removing the first interlayer film after the step of isotropically etching the conductive layer.

[0014]

According to the present invention, the conductive layer is deposited in the groove of the semiconductor substrate and on the second interlayer film, and the surface of the conductive layer is located between the second interlayer film in the groove. Then, the second interlayer film is removed. At this time, the conductive layer projects from the surface of the first interlayer film. In this state, the conductive layer is isotropically etched to the surface of the semiconductor substrate. At this time, conditions are set such that the conductive layer is isotropically etched by the same thickness as the first interlayer film,
Etch the conductive layer. This allows the surface of the conductive layer and the surface of the semiconductor substrate to be at the same height.

A conductive layer is deposited in the contact hole and on the third interlayer film, and the conductive layer is etched so that the surface of the conductive layer is located between the third interlayer film in the contact hole. After that, the third interlayer film is removed. At this time, the conductive layer projects from the surface of the second interlayer film. In this state, the conductive layer is isotropically etched to the surface of the first interlayer film. At this time, conditions are set so that the conductive layer is isotropically etched by the same thickness as the second interlayer film, and the conductive layer is etched. This allows the surface of the conductive layer and the surface of the first interlayer film to have the same height.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. 1 to 10 are cross-sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
This is a case where it is applied to a memory capacitor of RAM. First, on the surface of the silicon substrate 21, a CVD (Chemi
A silicon nitride film 22 as a first interlayer insulating film is deposited by the cal vapor deposition method. Next, a TEOS (tetraethyl orthosilicate) film 23 as a second interlayer insulating film is formed on the silicon nitride film 22 by a CVD method.
Are deposited.

After this, as shown in FIG.
A resist film 24 is provided on the film 23. Next, as shown in FIG. 3, using the resist film 24 as a mask,
The TEOS film 23 and the silicon nitride film 22 are sequentially anisotropically etched. As a result, the TEOS film 23 is provided with the first opening 23a, and the silicon nitride film 22 is provided with the second opening 22a. After that, the resist film 24 is removed. Next, the TEOS film 23 is used as a mask for anisotropic etching to form a trench 21a in the silicon substrate 21.

Next, as shown in FIG. 4, the trench 2 is formed.
An oxide film 25 is formed on the inner surface of 1a by thermal oxidation. After this, the oxide film 25 on the bottom of the trench 21a is formed.
Are removed by anisotropic etching. Next, as shown in FIG. 5, a first polysilicon film 26 is formed on the bottom of the trench 21a and inside the oxide film 25 by the CVD method, and the first polysilicon film 26 is formed on the silicon substrate 2.
1 is contacted. After that, an NO film (not shown) is formed as a capacitor insulating film on the first polysilicon film 26.

Thereafter, as shown in FIG. 6, a second polysilicon film 27 is deposited on the NO film and the TEOS film 23. Next, as shown in FIG. 7, the second polysilicon film 27 is isotropically etched,
The second polysilicon film 27 is removed up to the middle of the first opening 23a of the TEOS film 23.

Next, as shown in FIG. 8, the TEOS film 23 is removed. In the removal step at this time, since the selection ratio is large due to the etching of TEOS and polysilicon,
It has no effect on the polysilicon film 27. Thereafter, as shown in FIG. 9, the second polysilicon film 27 is
Isotropic etching is performed by the same thickness as the silicon nitride film 22. As a result, the second polysilicon film 27 has the same height as the silicon substrate 21.

That is, even if the second polysilicon film 27 before the isotropic etching is projected from the surface of the silicon nitride film 22 as shown in FIG. 8, the second polysilicon film 27 is isotropic. The second polysilicon film 27 can be made to have the same height as the silicon substrate 21 by setting the thickness of the silicon nitride film 22 to be subjected to the characteristic etching. That is, when the second polysilicon film 27 is isotropically etched by the film thickness c, not only the etching progresses in the direction of the arrow b shown in FIG.
Point a at which the upper surface of No. 2 contacts the second polysilicon film 27
Etching proceeds concentrically around ₁ and a ₂ . Therefore, the polysilicon film 27 has the points a ₁ and a ₂
The height of the polysilicon film 27 on the side wall of the trench 21a is determined by the depth etched from.
Further, by combining the etching from the points a ₁ and a ₂ and the etching from the direction of the arrow b, the upper surface of the polysilicon film 27 is almost flat even in the central portion of the trench 21a as shown in FIG. Becomes

After this, as shown in FIG. 10, the silicon nitride film 22 is removed. According to the first embodiment, the TEOS film 2 and the trench 21a of the silicon substrate 21 are formed.
A second polysilicon film 27 is deposited on top of the TEOS film 23 and the second polysilicon film 27 is deposited on the TEOS film 23.
After the removal up to the middle, the TEOS film 23 is peeled off. At this time, the second polysilicon film 27 is replaced by the silicon nitride film 22.
Protruding from the surface of. In this state, the second polysilicon film 27 is isotropically etched to the surface of the silicon substrate 21. At this time, conditions are set so that the second polysilicon film 27 is isotropically etched by the same thickness as the silicon nitride film 22, and the polysilicon film 27 is isotropically etched. As a result, the surface of the second polysilicon film 27 and the surface of the silicon substrate 21 can have the same height. Therefore, the surface of the silicon substrate 21 can be made sufficiently flat and uniform.

That is, a silicon nitride film 22 is provided on the surface of the silicon substrate 21, and TEO is formed on the nitride film 22.
An S film 23 is provided. Therefore, the silicon nitride film 22 is not etched by the etching when forming the trench 21a in the silicon substrate 21. At the same time, the film thickness of the silicon nitride film 22 is not thinned by the pretreatment before the conductive layer 27 is embedded in the trench 21a. Therefore, the thickness of the silicon nitride film 22 does not vary. As a result, the silicon nitride film 22
If the conditions are set so that the second polysilicon film 27 is isotropically etched by the same thickness as that of the second polysilicon film 27, the thickness of the silicon nitride film 22 does not vary. And the surface of the silicon substrate 21 can have the same height. That is, the polysilicon film 27
Assuming that the thickness of the isotropic etching is the thickness of the silicon nitride film 22, even if the polysilicon film 27 is projected from the surface of the nitride film 22 as shown in FIG. The surface of the film 27 and the surface of the substrate 21 can have the same height.

11 to 20 are sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.
This is when applied to embedding a contact hole.
First, BPSG (Boron-doped Phospho-Silicat) as a first interlayer insulating film is formed on the metal wiring 31 by the CVD method.
An e Glass) film 32 is deposited. Next, this BPSG film 3
A silicon nitride film 33 as a second interlayer insulating film is deposited on the second layer 2 by the CVD method. Next, on this silicon nitride film 33, a TEOS film 34 as a third interlayer insulating film is deposited by the CVD method.

After this, as shown in FIG.
A resist film 35 is provided on the S film 34. next,
As shown in FIG. 13, using this resist film 35 as a mask, the TEOS film 34, the silicon nitride film 33, and the BPSG are formed.
The film 32 is sequentially anisotropically etched. This allows
TEOS film 34, silicon nitride film 33 and BPSG film 3
2 is provided with a contact hole 36. After this, FIG.
The resist film 35 is removed as shown in FIG.

Next, as shown in FIG. 15, a conductive layer 37 made of polysilicon is deposited in the contact hole 36 and on the TEOS film 34. After that, as shown in FIG. 16, the conductive layer 37 is isotropically etched, so that the conductive layer 37 becomes TE in the contact hole 36.
The OS film 34 is removed to the middle. Next, as shown in FIG. 17, at least the TEOS film 34 near the contact hole 36 is peeled off.

Thereafter, as shown in FIG. 18, the conductive layer 37 is formed.
Is isotropically etched by the same thickness as the silicon nitride film 33. As a result, the conductive layer 37 has the same height as the BPSG film 32. That is, although the conductive layer 37 before the isotropic etching was projected from the surface of the silicon nitride film 33 as shown in FIG.
If the same thickness as that of No. 3 is used for the isotropic etching, the conductive layer 37 can have the same height as the BPSG film 32. The mechanism by which the conductive layer 37 is isotropically etched is the same as in the first embodiment.

Next, as shown in FIG. 19, the silicon nitride film 33 is removed. As a result, the conductive layer 37 is embedded in the contact hole 36 formed in the BPSG film 32, and the BPSG film 32 after the filling has a flat surface.

According to the second embodiment, a conductive layer 37 is deposited in the contact hole 36 and on the TEOS film 34, and the conductive layer 37 is used as the TEOS film 3 of the contact hole 36.
After removing up to the middle of 4, the TEOS film 34 is peeled off.
At this time, the conductive layer 37 projects from the surface of the silicon nitride film 33. In this state, the conductive layer 37 is formed on the BPSG film 32.
Isotropic etching is performed up to the surface of. At this time, conditions are set so that the conductive layer 37 is isotropically etched by the same thickness as the silicon nitride film 33, and the conductive layer 37 is isotropically etched. As a result, the surface of the conductive layer 37 and B
The surface of the PSG film 32 can have the same height, and B
The surface of the PSG film 32 can be sufficiently flattened.

That is, a silicon nitride film 33 is provided on the surface of the BPSG film 32, and TEOS is formed on the nitride film 33.
A membrane 34 is provided. Therefore, the contact holes 36 are formed in the TEOS film 34, the silicon nitride film 33, and the BPSG film 32.
The silicon nitride film 33 is formed by etching when forming
Surface is not etched. Therefore, the thickness of the silicon nitride film 33 does not vary. As a result, if the conditions are set so that the conductive layer 37 is isotropically etched by the same thickness as the silicon nitride film 33, the thickness of the silicon nitride film 33 will not vary.
The surface of the conductive layer 37 and the surface of the BPSG film 32 can have the same height. That is, since there is no variation in the thickness of the silicon nitride film 33, if the thickness for the isotropic etching of the conductive layer 37 is set to the thickness of the silicon nitride film 33,
The surface of the conductive layer 37 and the surface of the BPSG film 32 can have the same height. Therefore, it is not necessary to overetch the conductive layer 37 in order to prevent the etching residue of the conductive layer 37 unlike the prior art.

[0031]

As described above, according to the present invention,
The thickness at which the conductive layer is etched is set to the thickness of the first interlayer film, and the conductive layer is isotropically etched. Therefore, the surface of the semiconductor substrate or the interlayer insulating film after the conductive layer is filled in the trench or the contact hole can be sufficiently flattened.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the invention, showing the next step of FIG. 1;

FIG. 3 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 2;

FIG. 4 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 3;

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 4;

FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 5;

FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 6;

FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 7;

FIG. 9 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 8;

FIG. 10 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention, showing the next step of FIG. 9;

FIG. 11 is a sectional view showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention, showing the next step of FIG. 11;

FIG. 13 is a sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention, showing the next step of FIG. 12;

FIG. 14 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention, showing the next step of FIG. 13;

FIG. 15 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention, showing the next step of FIG. 14;

FIG. 16 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention, showing the next step of FIG. 15;

FIG. 17 is a sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention, showing the step subsequent to that of FIG. 16;

FIG. 18 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention, showing the next step of FIG. 17;

FIG. 19 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention, showing the next step of FIG. 18;

FIG. 20 is a cross-sectional view showing the first conventional semiconductor device manufacturing method.

FIG. 21 is a cross-sectional view showing the first conventional semiconductor device manufacturing method, and showing the next step of FIG. 20;

FIG. 22 is a cross-sectional view showing the first conventional semiconductor device manufacturing method, and showing the next step of FIG. 21;

FIG. 23 is a cross-sectional view showing the first conventional semiconductor device manufacturing method, and showing the next step of FIG. 22;

FIG. 24 is a cross-sectional view showing the first conventional semiconductor device manufacturing method, and showing the next step of FIG. 23;

FIG. 25 is a cross-sectional view showing the first conventional semiconductor device manufacturing method, and showing the next step of FIG. 24;

FIG. 26 is a cross-sectional view showing the first conventional semiconductor device manufacturing method, and showing the next step of FIG. 25;

FIG. 27 is a cross-sectional view showing the first conventional semiconductor device manufacturing method, and showing the next step of FIG. 26;

FIG. 28 is a cross-sectional view showing the second conventional method for manufacturing a semiconductor device.

FIG. 29 is a cross-sectional view showing the second conventional method for manufacturing a semiconductor device, showing the next step of FIG. 28;

FIG. 30 is a cross-sectional view showing the second conventional method for manufacturing a semiconductor device, showing the next step of FIG. 29;

FIG. 31 is a cross-sectional view showing the second conventional method for manufacturing a semiconductor device, showing the next step of FIG. 30;

32 is a cross-sectional view showing the second conventional method for manufacturing a semiconductor device, showing the next step of FIG. 31; FIG.

[Explanation of symbols]

21 ... Silicon substrate, 21a ... Trench (groove), 22 ... Silicon nitride film, 22a ... Second opening, 23 ... TEOS film, 23a
... first opening portion, 24 ... resist film, 25 ... oxide film, 26 ... first polysilicon film, 27 ... second polysilicon film, 31 ...
Metal wiring, 32 ... BPSG film, 33 ... Silicon nitride film, 34 ...
TEOS film, 35 ... Resist film, 36 ... Contact hole (groove), 37 ... Conductive layer.

Claims (5)

[Claims] 1. A step of forming a first interlayer film on a surface of a semiconductor substrate, a step of forming a second interlayer film on the first interlayer film, and the first and second interlayer films. A step of forming a groove in the semiconductor substrate; a step of depositing a conductive layer in the groove and on the second interlayer film; and a surface of the conductive layer located between the second interlayer films in the groove. As such, the step of etching the conductive layer, the step of removing at least the second interlayer film in the vicinity of the groove, and the thickness of the conductive layer etched to the film thickness of the first interlayer film. And a step of isotropically etching the conductive layer, the manufacturing method of the semiconductor device comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the groove is a trench. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of removing the first interlayer film after the step of isotropically etching the conductive layer. 4. A step of forming a first interlayer film on the wiring, a step of forming a second interlayer film on the first interlayer film, and a step of forming a second interlayer film on the second interlayer film. A step of forming a third interlayer film, a step of providing a contact hole in the first to third interlayer films, a step of depositing a conductive layer in the contact hole and on the third interlayer film, Etching the conductive layer so that the surface of the conductive layer is located between the third interlayer films in the contact holes; and removing the third interlayer film at least near the contact holes. And a step of setting the thickness of the conductive layer to be etched to the thickness of the second interlayer film and isotropically etching the conductive layer, the method for manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of removing the first interlayer film after the step of isotropically etching the conductive layer.