JPH10163322A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which can reduce the junction capacitance and a leakage current and can prevent degradation in punch-through resistance by reducing the contacting area between a silicon film and a silicon substrate. SOLUTION: This semiconductor device comprises, an interlayer TEOS (tetraethyl orthosilicate) oxide film 3 having a contact hole 4 formed on a silicon substrate 1, a film 6a made of silicon carbide formed in a part of the opening of the contact hole 4 on the surface of the silicon substrate 1; and a phosphorus-doped polysilicon film 8 which is formed in the contact hole 4 and has a contact surface 1a with the silicon substrate 1. On the surface of the silicon substrate 1, the contact surface 1a is surrounded by a film 6a made of silicon carbide. Consequently, the area of a junction surface 9a between an N<+> diffusion region 9 formed by diffusion of phosphorus from the phosphorus- doped polysilicon film 8 to the silicon substrate 1 and a P-type well 12 formed in the silicon substrate 1 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a bonding surface between a silicon substrate and an electric element such as a wiring.

[0002]

2. Description of the Related Art The structure of a conventional semiconductor device is shown in FIG.
5 will be described. Here, FIG. 15 is a cross-sectional view of a main part showing a structure of a conventional semiconductor device. In FIG.
Reference numeral 1 denotes a silicon substrate having a concave portion 1c in a part of the surface, 2 denotes a gate electrode of an N-channel field effect MOS transistor formed on the silicon substrate 1, and 3 denotes an interlayer TEOS ( Tetra-Eth
yl-Ortho Silicate) oxide film, 4 is a contact hole formed in the interlayer TEOS oxide film 3 which opens on the surface including the concave portion 1c of the silicon substrate 1, and 5 is the N-type source / drain of the field effect MOS transistor. Area.

Further, 7a is formed in the inside of the contact hole 4, and a cylindrical TEOS oxide film is formed along the side surface of the contact hole 4, and 8 is formed in the inside of the contact hole 4 to make contact with the silicon substrate 1. A phosphorus-doped polycrystalline silicon film contacting at 1a, 9 is an N ⁺ diffusion region formed by diffusion of phosphorus from the phosphorus-doped polycrystalline silicon film 8 to the silicon substrate 1, and 9a is formed in the N ⁺ diffusion region 9 and the silicon substrate 1. The junction surface 13 with the P-type well 12 is used to insulate the phosphorus-doped polycrystalline silicon film 8 from an electrical element formed on the phosphorus-doped polycrystalline silicon film 8 and formed in an upper layer such as a wiring. of,
An upper TEOS interlayer film made of a TEOS oxide film.

[0004] In addition, x is the width of the silicon substrate concave portion 1c in this cross section, and y is the side wall T on the surface of the silicon substrate 1.
This is the interval in the main cross section of the inner surface of the EOS oxide film 7a. Conventionally, the interval y shows a value that is about 20 to 30% larger than the value of the width x. About 0.1
In the case of 6 μm, the interval y showed a value of about 0.2 μm.

Here, a method of manufacturing a conventional semiconductor device having the above-described structure will be described below with reference to FIGS.
It will be described based on. Here, FIGS. 16 to 21 are cross-sectional views of essential parts showing a conventional method of manufacturing a semiconductor device in the order of steps.

First, as shown in FIG. 16, a P-type well 12 is formed by ion implantation of, for example, boron or the like, and an N-type well is formed on the P-type well 12 through a gate oxide film.
Gate electrode 2 of channel field effect MOS transistor
Is further formed by ion implantation of, for example, phosphorus on the silicon substrate 1 in which the N-type source / drain regions 5 of the MOS transistor are formed so as to be surrounded by the P-type well 12. Form 3

Next, as shown in FIG. 17, an electron cyclotron resonance type is applied to a desired position of the interlayer TEOS oxide film 3 using a photolithography technique, for example, using a CF ₄ -based or CHF ₃ -based gas system. Reactive ion etching (ECR-RI
E: Electron Cyclotron Reso
nonce-Reactive Ion Etchin
A contact hole 4 opening in the surface of the silicon substrate 1 is formed by the method g).

Next, as shown in FIG. 18, the silicon substrate 1 including the inside of the contact hole 4 is formed by using the CVD method.
A TEOS oxide film 7 is deposited thereon.

Next, as shown in FIG. 19, the TEOS oxide film 7 is anisotropically etched to expose the surface of the silicon substrate 1 and to form the sidewall TEOS oxide film 7a.
Is formed on the side surface of the contact hole 4.

Here, a concave portion 1c is formed on the exposed surface of the silicon substrate 1 by overetching. At this time, the width x in the main section of the silicon substrate concave portion 1c is:
The interval in the cross section of the inner surface of the side wall TEOS oxide film 7a on the surface of the silicon substrate 1 coincides with the interval in the present section.

Here, the sidewall TEOS oxide film 7a
Is formed in order to prevent a short circuit between the gate electrode 2 and the phosphorus-doped polycrystalline silicon film 8 formed in a later step.

At this time, a natural oxide film 11 is formed on the exposed surface of the silicon substrate 1, and since the natural oxide film 11 is an insulator, a phosphorus-doped polycrystalline silicon film formed in a later step is formed. In order to make electrical connection between the silicon substrate 1 and the silicon substrate 8, it is necessary to remove them.

Therefore, as shown in FIG. 20, immediately before forming the phosphorus-doped polycrystalline silicon film 8, the natural oxide film 11 is removed by wet etching using hydrofluoric acid. Since the wet etching using hydrofluoric acid is an isotropic etching, the side wall TEOS oxide film 7a is also etched at the same time, and this cross section of the inner surface of the side wall TEOS oxide film 7a on the surface of the silicon substrate 1 is obtained. Interval y
Is larger than the width x in the main cross section of the silicon substrate concave portion 1c.

Next, as shown in FIG.
Immediately after the removal of 1, a phosphorus-doped polycrystalline silicon film 8 is deposited on the silicon substrate 1 including the inside of the contact hole 4 so as to be in contact with the exposed surface 1 a of the silicon substrate 1 from which the native oxide film 11 has been removed.

Thereafter, the phosphorus-doped polycrystalline silicon film 8 is processed into a desired shape by using a photolithography technique, and the silicon substrate 1 including the processed phosphorus-doped polycrystalline silicon film 8 is formed on the silicon substrate 1 by CVD. An upper TEOS interlayer film 13 made of a TEOS oxide film is deposited.

Then, by performing a heat treatment, the surface of the upper TEOS interlayer film 13 is made smooth to reduce a step between the peripheral circuit and the memory cell portion, and a metal wiring such as an aluminum wiring formed in the upper layer is formed. The semiconductor device shown in FIG. 15 is obtained by improving the resistance to wet etching performed before the etching. Here, phosphorus diffuses from the phosphorus-doped polycrystalline silicon film 8 to the silicon substrate 1 by the heat treatment, and an N ⁺ diffusion layer 9 is formed on the silicon substrate 1.

[0017]

In the conventional semiconductor device as described above, the heat treatment applied to the upper TEOS interlayer film 13 and the formation of a dielectric film (ON film) when forming a capacitor of a memory cell are performed. By the heat treatment after the step of forming the phosphorus-doped polycrystalline silicon film 8 such as the heat treatment in the above, phosphorus diffuses from the phosphorus-doped polycrystalline silicon film 8 to the silicon substrate 1 to form the N ⁺ diffusion layer 9.
In the step of etching the natural oxide film 11 using hydrofluoric acid shown in FIG. 1, the contact surface 1a where the phosphorus-doped polycrystalline silicon film 8 and the silicon substrate 1 come into contact later is enlarged, so that the N ⁺ diffusion Layer 9 also enlarges.

Therefore, the N ⁺ diffusion layer 9 and the P-type well 12
The area of the N ⁺ / P junction interface, which is the bonding surface 9a with the N ⁺ / P junction, also increases, and the phosphorus-doped polysilicon film 8
And the leakage current at the junction between the phosphorus-doped polycrystalline silicon film 8 and the silicon substrate 1 also increases.

The diffusion of phosphorus in a direction parallel to the main surface of the silicon substrate 1 serves as a part of the N-type source / drain region 5 of the field-effect transistor. There is also a problem that the resistance is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has a small contact area between a silicon film and a silicon substrate, and a diffusion region formed by diffusion of impurities from the silicon film to the silicon substrate. And the junction (PN junction) area with the impurity region of the different conductivity type formed on the main surface of the silicon substrate can be reduced, whereby the junction capacitance between the silicon film and the silicon substrate can be reduced. It is another object of the present invention to provide a semiconductor device capable of reducing a leak current at a junction between a silicon film and a silicon substrate.

Further, diffusion of impurities from the silicon film in a direction parallel to the main surface of the silicon substrate is suppressed, and therefore, a diffusion region formed by diffusion of impurities from the silicon film to the silicon substrate is formed by a field effect type. It is an object of the present invention to provide a semiconductor device which can prevent deterioration of punch-through resistance of the transistor when used as part of a source / drain region of the transistor.

Another object of the present invention is to provide a semiconductor device which does not require an increase in the number of steps when manufacturing the semiconductor device.

[0023]

A semiconductor device according to the present invention comprises: an interlayer insulating film formed on a silicon substrate and having a contact hole opened on the surface of the silicon substrate;
An impurity diffusion preventing film having etching resistance to hydrofluoric acid formed on a part of a portion of the silicon substrate surface where the contact hole is opened; and an impurity diffusion preventing film formed inside the contact hole and being formed on the silicon substrate surface. An impurity-containing silicon film having a contact surface with the silicon substrate in a portion where the film is not formed, and a contact surface between the silicon film and the silicon substrate on the silicon substrate surface, wherein the impurity diffusion It is characterized by being surrounded by a prevention film.

Further, the impurity diffusion preventing film is made of silicon carbide.

An interlayer insulating film formed on the silicon substrate and having a contact hole opening on the surface of the silicon substrate, and an interlayer insulating film formed inside the contact hole and opening the contact hole on the silicon substrate surface A portion having a contact surface with the silicon substrate, an impurity diffusion preventing film having etching resistance to hydrofluoric acid, and a portion of the portion of the silicon substrate surface where the contact hole is opened, formed inside the contact hole. A silicon film containing an impurity having a contact surface with the silicon substrate, and a contact surface between the silicon film and the silicon substrate on the surface of the silicon substrate; It is characterized by being surrounded by a contact surface.

Further, the impurity diffusion preventing film is a silicon nitride film.

Further, a cylindrical silicon oxide film is provided along the contact hole on the impurity diffusion preventing film inside the contact hole, and a silicon film is formed in contact with the inner wall of the cylindrical silicon oxide film. It is characterized by having.

The method of manufacturing a semiconductor device according to the present invention comprises:
A step of forming an interlayer insulating film on a silicon substrate, and forming a contact hole opening in the surface of the silicon substrate in the interlayer insulating film by anisotropic dry etching using a gas system having a high carbon ratio; Forming an impurity diffusion preventing film having etching resistance to hydrofluoric acid on the surface of the silicon substrate where the contact hole is opened; and depositing a silicon oxide film on the silicon substrate including the inside of the contact hole; Removing the silicon oxide film and the impurity diffusion preventing film by dry etching to expose a portion of the silicon substrate where the impurity diffusion preventing film is not formed; and cleaning the exposed silicon substrate surface with hydrofluoric acid. Using a step of etching, and inside the contact hole,
Forming a silicon film containing impurities in contact with the exposed silicon substrate.

Further, the impurity diffusion preventing film is made of silicon carbide.

A step of forming an interlayer insulating film on the silicon substrate; a step of forming a contact hole in the surface of the silicon substrate in the interlayer insulating film; and a step of forming a contact hole on the silicon substrate including the inside of the contact hole. Depositing an impurity diffusion preventing film having etching resistance to hydrofluoric acid, and depositing a silicon oxide film on the impurity diffusion preventing film including the inside of the contact hole;
Removing the silicon oxide film and the impurity diffusion preventing film by anisotropic dry etching to expose the silicon substrate surface; etching the exposed silicon substrate surface using hydrofluoric acid; Forming a silicon film containing impurities inside the hole so as to be in contact with the exposed silicon substrate.

Further, the impurity diffusion preventing film is a silicon nitride film.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. First, the structure of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIG. Here, FIG. 1 is a fragmentary cross-sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a recess 1c in a part of the surface.
, A gate electrode of an N-channel field-effect MOS transistor formed on the silicon substrate 1, and an interlayer T formed on the silicon substrate 1.
EOS (Tetra-Ethyl-Ortho Si)
oxide), 4 is a concave portion 1c of the silicon substrate 1.
The contact holes 5 formed in the interlayer TEOS oxide film 3 which are opened on the surface including the N-type source / drain regions of the field-effect MOS transistor.

Reference numeral 6a denotes a phosphorus diffusion preventing film which is formed in a portion of the surface of the silicon substrate 1 where the contact hole 4 is opened except the substrate concave portion 1c and has etching resistance to hydrofluoric acid. In the form 1,
Specifically, a film made of silicon carbide having a thickness of about 50 to 100 ° is used.

A reference numeral 7a is formed inside the contact hole 4, and a cylindrical TEOS oxide film is formed along the side surface of the contact hole 4; a reference numeral 8 is formed inside the contact hole 4; A contact surface 1a surrounded by the film 6a made of silicon carbide described above, a phosphorus-doped polycrystalline silicon film contacting the silicon substrate 1,
Reference numeral 9 denotes an N ⁺ diffusion region formed by diffusion of phosphorus from the phosphorus-doped polycrystalline silicon film 8 to the silicon substrate 1, 9a
Denotes a junction surface between the N ⁺ diffusion region 9 and a P-type well 12 formed in the silicon substrate 1, and 13 denotes an electric element formed on the phosphorus-doped polycrystalline silicon film 8 and formed on an upper layer such as a wiring. Upper layer TEO made of a TEOS oxide film for insulating the silicon oxide film from phosphorus-doped polycrystalline silicon film 8.
This is an S interlayer film.

Next, a method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
Here, FIGS. 2 to 7 are main-portion cross-sectional views illustrating a method of manufacturing the semiconductor device in the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 2, a P-type well 12 is formed by ion implantation of, for example, boron.
A gate electrode 2 of an N-channel field-effect MOS transistor is formed on the P-type well 12 with a gate oxide film interposed therebetween. Further, the N-type source / drain of the MOS transistor is formed by ion implantation of, for example, phosphorus. An interlayer TEOS oxide film is formed on a silicon substrate in which a region is surrounded by a P-type well.

Next, as shown in FIG. 3, using a photoengraving technique, a gas system having a high carbon ratio, specifically, for example, a C ₄ F ₈ system is placed at a desired position of the interlayer TEOS oxide film 3. Cyclotron resonance type reactive ion etching (ECR-RIE: Electron Cyclotrr)
on Resonance-Reactive Ion
A contact hole 4 opening in the surface of the silicon substrate 1 is formed by an (Etching) method.

At this time, conventionally, CF ₄ or CHF ₃
In the first embodiment, a C ₄ F ₈ system having a high carbon ratio is used, whereas a system gas system is used.
On the surface of the silicon substrate 1 where the contact hole 4 is opened, a film 6 made of silicon carbide having a thickness of about 50 to 100 ° is formed. The silicon carbide film 6 has etching resistance to hydrofluoric acid and a phosphorus-doped polycrystalline silicon film 8 formed in a later step.
This is a film having a feature that diffusion of phosphorus from the silicon substrate 1 can be prevented.

Next, as shown in FIG. 4, a TEOS oxide film 7 is deposited on the silicon substrate 1 including the inside of the contact hole 4 by using the CVD method.

Next, as shown in FIG. 5, the TEOS oxide film 7 and the film 6 made of silicon carbide are anisotropically dry-etched, so that the film 6 made of silicon carbide on the silicon substrate 1 is not formed. And exposing the side wall TEOS oxide film 7 a to the contact hole 4.
Formed on the side surface.

Here, on the exposed surface of the silicon substrate 1, a concave portion 1c is formed by overetching, and a film 6a made of etched silicon carbide and surrounding the concave portion 1c is formed. The width x ₁ in the cross section of the silicon substrate recess 1c is in the silicon substrate 1 coincides with the spacing in the cross-section of the inner surface of the side wall TEOS oxide film 7a.

Here, the sidewall TEOS oxide film 7a
Is formed in order to prevent a short circuit between the gate electrode 2 and the phosphorus-doped polycrystalline silicon film 8 formed in a later step.

At this time, a natural oxide film 11 is formed on the exposed surface of the silicon substrate 1, and since this natural oxide film 11 is an insulator, a phosphorus-doped polycrystalline silicon film formed in a later step is formed. In order to make electrical connection between the silicon substrate 1 and the silicon substrate 8, it is necessary to remove them.

Next, as shown in FIG. 6, immediately before forming the phosphorus-doped polycrystalline silicon film 8, the natural oxide film 11 is removed by wet etching using hydrofluoric acid. Since the wet etching using hydrofluoric acid is an isotropic etching, the side wall TEOS oxide film 7a is also etched at the same time. On the other hand, the film 6a made of silicon carbide remains without being etched because it has etching resistance to hydrofluoric acid. Therefore, the distance y ₁ in the main cross section of the inner surface of the sidewall TEOS oxide film 7a on the surface of the silicon substrate ₁ is larger than the width x ₁ in the main cross section of the silicon substrate concave portion 1c.

Next, as shown in FIG.
Immediately after the removal, a phosphorus-doped polycrystalline silicon film 8 is deposited on the silicon substrate 1 including the inside of the contact hole 4 so as to be in contact with the exposed surface 1a of the silicon substrate 1 from which the native oxide film 11 has been removed.

Thereafter, the phosphorus-doped polycrystalline silicon film 8 is processed into a desired shape by using a photolithography technique, and the silicon substrate 1 including the processed phosphorus-doped polycrystalline silicon film 8 is formed on the silicon substrate 1 by CVD. An upper TEOS interlayer film 13 made of a TEOS oxide film is deposited.

Then, a heat treatment is performed to smooth the surface of the upper TEOS interlayer film 13 to reduce the step between the peripheral circuit and the memory cell portion, and to form a metal wiring such as an aluminum wiring formed in the upper layer. The semiconductor device shown in FIG. 1 is obtained by improving the resistance to wet etching performed before the etching. Here, phosphorus diffuses from the phosphorus-doped polycrystalline silicon film 8 to the silicon substrate 1 by the heat treatment, and an N ⁺ diffusion layer 9 is formed on the silicon substrate 1.

In the first embodiment, in the wet etching process using hydrofluoric acid shown in FIG. 6, the film 6a made of silicon carbide remains without being etched because it has etching resistance to hydrofluoric acid. Therefore, the phosphorus-doped polycrystalline silicon film 8 contributes to the diffusion of phosphorus from the phosphorus-doped polycrystalline silicon film 8 to the silicon substrate 1.
The area of the contact surface 1a between the semiconductor substrate 1 and the silicon substrate 1 is reduced as compared with the conventional case, and an N ⁺ diffusion
Can be prevented, and the area of the N ⁺ / P junction interface at the junction surface 9a between the N ⁺ diffusion region 9 and the P-type well 12 formed in the silicon substrate 1 can be reduced.

Therefore, the junction area between phosphorus-doped polycrystalline silicon film 8 and silicon substrate 1 can be reduced by reducing the area of junction surface 9a, and the junction between phosphorus-doped polycrystalline silicon film 8 and silicon substrate 1 can be reduced. Can also reduce the leakage current.

Since the diffusion of impurities from the phosphorus-doped polycrystalline silicon film 8 in a direction horizontal to the silicon substrate 1 can be suppressed, the phosphorus-doped polycrystalline silicon film 8 can be suppressed.
N ⁺ diffusion region 9 formed by diffusion of impurities from silicon into silicon substrate 1, even when used as a part of N-type source / drain region 5 of a field-effect transistor, has a punch-through resistance of the transistor. Deterioration can be prevented.

Further, the method of manufacturing a semiconductor device according to the first embodiment has an advantage that the number of steps does not need to be increased as compared with the conventional method.

In the first embodiment of the present invention,
Although the phosphorus-doped polycrystalline silicon film 8 is used, a phosphorus-doped amorphous silicon film may be used instead. In this case, the same effect as described above is obtained.

Embodiment 2 Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. First,
Second Embodiment A structure of a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. Here, FIG. 8 is a cross-sectional view of a principal part showing the structure of the semiconductor device according to the second embodiment of the present invention.

In FIG. 8, reference numeral 1 denotes a recess 1c on a part of the surface.
, A gate electrode of an N-channel field-effect MOS transistor formed on the silicon substrate 1, and an interlayer T formed on the silicon substrate 1.
EOS (Tetra-Ethyl-Ortho Si)
oxide), 4 is a concave portion 1c of the silicon substrate 1.
The contact holes 5 formed in the interlayer TEOS oxide film 3 which are opened on the surface including the N-type source / drain regions of the field-effect MOS transistor.

Reference numeral 7a is formed inside the contact hole 4 and a cylindrical side wall TEOS oxide film is formed along the side surface of the contact hole 4, and reference numeral 8 is formed inside the contact hole 4 to make contact with the silicon substrate 1. A phosphorus-doped polycrystalline silicon film contacting at 1a, 9 is an N ⁺ diffusion region formed by diffusion of phosphorus from the phosphorus-doped polycrystalline silicon film 8 to the silicon substrate 1, and 9a is formed in the N ⁺ diffusion region 9 and the silicon substrate 1. This is a bonding surface with the P-type well 12.

Reference numeral 10a is formed inside the contact hole 4, and the side surface and the side wall TE of the contact hole 4 are formed.
This is a phosphorus diffusion prevention film having a cylindrical portion interposed between OS oxide films 7a and a portion in contact with silicon substrate 1 at contact surface 1b and having etching resistance to hydrofluoric acid. Specifically, a silicon nitride film having a thickness of about 100 ° is used.
Here, on the surface of the silicon substrate 1, the contact surface 1a between the phosphorus-doped polycrystalline silicon film 8 and the silicon substrate 1 is:
Contact surface 1b between silicon nitride film 10a and silicon substrate 1
Surrounded by

Reference numeral 13 denotes a TEOS oxide film formed on the phosphorus-doped polycrystalline silicon film 8 to insulate an electric element formed in an upper layer such as a wiring from the phosphorus-doped polycrystalline silicon film 8. This is an upper TEOS interlayer film.

Next, a method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 9 to 14 are main-portion cross-sectional views illustrating a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention in the order of steps.

First, as shown in FIG. 9, a P-type well 12 is formed by ion implantation of, for example, boron.
A gate electrode 2 of an N-channel field-effect MOS transistor is formed on the P-type well 12 with a gate oxide film interposed therebetween. Further, the N-type source / drain of the MOS transistor is formed by ion implantation of, for example, phosphorus. An interlayer TEOS oxide film is formed on a silicon substrate in which a region is surrounded by a P-type well.

Next, as shown in FIG. 10, an electron cyclotron resonance type is formed at a desired position of the interlayer TEOS oxide film 3 by using a photolithography technique, for example, by using a CF ₄ -based or CHF ₃ -based gas system. Reactive ion etching (ECR-RI
E: Electron Cyclotron Reso
nonce-Reactive Ion Etchin
A contact hole 4 opening in the surface of the silicon substrate 1 is formed by the method g).

Next, as shown in FIG. 11, the silicon substrate 1 including the inside of the contact hole 4 is formed by the CVD method.
A silicon nitride film 10 having a thickness of about 100 ° is deposited thereon.
Thereafter, a TEOS oxide film 7 is deposited on the silicon nitride film 10 including the inside of the contact hole 4 by using the CVD method.

Next, as shown in FIG. 12, the TEOS oxide film 7 and the silicon nitride film 10 are anisotropically dry-etched, thereby exposing the surface of the silicon substrate 1 and forming the sidewall TEOS oxide film 7a into the contact holes 4a. Is formed on the side surface of the substrate through a silicon nitride film 10a. Here, the silicon nitride film 10a is formed by removing a part of the silicon nitride film 10 deposited in the previous step, which is in contact with the silicon substrate 1, by etching in this step.

Here, a concave portion 1c is formed on the exposed surface of the silicon substrate 1 by overetching. At this time, the width x in the main section of the silicon substrate concave portion 1c
₂ is a side wall TEOS oxide film 7 on the surface of the silicon substrate 1
a coincides with the interval in the section of the inner surface of FIG.

Here, the side wall TEOS oxide film 7a
Is formed in order to prevent a short circuit between the gate electrode 2 and the phosphorus-doped polycrystalline silicon film 8 formed in a later step.

At this time, a natural oxide film 11 is formed on the exposed surface of the silicon substrate 1, and since the natural oxide film 11 is an insulator, a phosphorus-doped polycrystalline silicon film formed in a later step is formed. In order to make electrical connection between the silicon substrate 1 and the silicon substrate 8, it is necessary to remove them.

Next, as shown in FIG. 13, immediately before forming the phosphorus-doped polycrystalline silicon film 8, the natural oxide film 11 is removed by wet etching using hydrofluoric acid. Since the wet etching using hydrofluoric acid is an isotropic etching, the side wall TEOS oxide film 7a is also etched at the same time. On the other hand, the silicon nitride film 10
a remains without being etched because it has etching resistance to hydrofluoric acid. Therefore, at the bottom of contact hole 4, the distance y ₂ in the main cross section of the inner surface of sidewall TEOS oxide film 7 a is larger than the width x ₂ in the main cross section of silicon substrate recess 1 c.

Next, as shown in FIG.
Immediately after the removal of 1, a phosphorus-doped polycrystalline silicon film 8 is deposited on the silicon substrate 1 including the inside of the contact hole 4 so as to be in contact with the exposed surface 1 a of the silicon substrate 1 from which the native oxide film 11 has been removed.

Thereafter, the phosphorus-doped polycrystalline silicon film 8 is processed into a desired shape by using a photomechanical technique, and the silicon substrate 1 including the processed phosphorus-doped polycrystalline silicon film 8 is formed on the silicon substrate 1 by CVD. An upper TEOS interlayer film 13 made of a TEOS oxide film is deposited.

Then, a heat treatment is performed to smooth the surface of the upper TEOS interlayer film 13 to reduce the steps in the peripheral circuit and the memory cell portion, and to form a metal wiring such as an aluminum wiring formed in the upper layer. The semiconductor device shown in FIG. 8 is obtained by improving the resistance to wet etching performed before the etching. Here, phosphorus diffuses from the phosphorus-doped polycrystalline silicon film 8 to the silicon substrate 1 by the heat treatment, and an N ⁺ diffusion layer 9 is formed on the silicon substrate 1.

In the second embodiment, in the wet etching process using hydrofluoric acid shown in FIG. 13, the silicon nitride film 10a remains without being etched because it has etching resistance to hydrofluoric acid. Therefore, the area of the contact surface 1a between the phosphorus-doped polycrystalline silicon film 8 and the silicon substrate 1 which contributes to the diffusion of phosphorus from the phosphorus-doped polycrystalline silicon film 8 to the silicon substrate 1 is suppressed as compared with the conventional case, and the phosphorus-doped polycrystalline silicon film 8 can prevent the spread of the N ⁺ diffusion regions 9 formed by the diffusion of phosphorus into the silicon substrate 1 from, N at the joint surfaces 9a of the N ⁺ diffusion region 9 and the P-type well 12 formed on the silicon substrate 1 ⁺
/ P junction interface area can be reduced.

Therefore, the junction area between phosphorus-doped polycrystalline silicon film 8 and silicon substrate 1 can be reduced by reducing the area of bonding surface 9a, and the junction between phosphorus-doped polycrystalline silicon film 8 and silicon substrate 1 can be reduced. Can also reduce the leakage current.

Since the diffusion of impurities from the phosphorus-doped polycrystalline silicon film 8 in the direction parallel to the silicon substrate 1 can be suppressed, the phosphorus-doped polycrystalline silicon film 8
N ⁺ diffusion region 9 formed by diffusion of impurities from silicon into silicon substrate 1, even when used as a part of N-type source / drain region 5 of a field-effect transistor, has a punch-through resistance of the transistor. Deterioration can be prevented.

In Embodiment 2 of the present invention,
Although the phosphorus-doped polycrystalline silicon film 8 is used, a phosphorus-doped amorphous silicon film may be used instead. In this case, the same effect as described above is obtained.

[0075]

According to the present invention, there is provided a semiconductor device formed on a silicon substrate, the interlayer insulating film having a contact hole opened on the surface of the silicon substrate, and a part of the silicon substrate surface where the contact hole is opened. An impurity diffusion preventing film having etching resistance to hydrofluoric acid formed in a portion, and a contact with the silicon substrate in a portion of the silicon substrate surface where the impurity diffusion preventing film is not formed, formed in the contact hole. A silicon film containing an impurity, the surface of the silicon substrate, the contact surface between the silicon film and the silicon substrate, characterized by being surrounded by the impurity diffusion prevention film, The contact area between the silicon film and the silicon substrate can be suppressed to be small. The junction (PN junction) area between the diffusion region formed by diffusion of impurities from the silicon film to the silicon substrate and the impurity region of the different conductivity type formed on the main surface of the silicon substrate can be reduced. In addition, the junction capacitance between the silicon film and the silicon substrate can be reduced, and the leakage current at the junction between the silicon film and the silicon substrate can be reduced. In addition, diffusion of impurities from the silicon film in a direction parallel to the main surface of the silicon substrate can be suppressed, so that a diffusion region formed by diffusion of impurities from the silicon film to the silicon substrate has an electric field effect. When used as a part of the source / drain region of a type transistor, it is possible to prevent the punch-through resistance of the transistor from deteriorating. Furthermore, in the manufacture of the semiconductor device, there is an advantage that it is not necessary to increase the number of steps as compared with the related art.

An interlayer insulating film formed on the silicon substrate and having a contact hole opening on the surface of the silicon substrate, and an interlayer insulating film formed inside the contact hole and opening the contact hole on the surface of the silicon substrate. A portion having a contact surface with the silicon substrate, an impurity diffusion preventing film having etching resistance to hydrofluoric acid, and a portion of the portion of the silicon substrate surface where the contact hole is opened, formed inside the contact hole. A silicon film containing an impurity having a contact surface with the silicon substrate, and a contact surface between the silicon film and the silicon substrate on the surface of the silicon substrate; Since it is characterized by being surrounded by the contact surface, the silicon film and the The contact area with the silicon substrate can be suppressed to be small. Therefore, a diffusion region formed by diffusion of the impurity from the silicon film to the silicon substrate and an impurity of a different conductivity type formed on the main surface of the silicon substrate. The junction (PN junction) area with the region can be reduced, so that the junction capacitance between the silicon film and the silicon substrate can be reduced, and the leakage current at the junction between the silicon film and the silicon substrate can be reduced. Can also be reduced. In addition, since diffusion of impurities from the silicon film in a direction parallel to the main surface of the silicon substrate can be suppressed, a diffusion region formed by diffusion of impurities from the silicon film to the silicon substrate has a field effect effect. When used as a part of the source / drain region of a type transistor, it is possible to prevent the punch-through resistance of the transistor from deteriorating.

A method of manufacturing a semiconductor device according to the present invention
A step of forming an interlayer insulating film on a silicon substrate, and forming a contact hole opening in the surface of the silicon substrate in the interlayer insulating film by anisotropic dry etching using a gas system having a high carbon ratio; Forming an impurity diffusion preventing film having etching resistance to hydrofluoric acid on the surface of the silicon substrate where the contact hole is opened; and depositing a silicon oxide film on the silicon substrate including the inside of the contact hole; Removing the silicon oxide film and the impurity diffusion preventing film by dry etching to expose a portion of the silicon substrate where the impurity diffusion preventing film is not formed; and cleaning the exposed silicon substrate surface with hydrofluoric acid. Using a step of etching, and inside the contact hole,
Forming a silicon film containing impurities so as to be in contact with the exposed silicon substrate.In a semiconductor device manufactured using the manufacturing method, the contact area between the silicon film and the silicon substrate is reduced. Therefore, a junction (PN junction) between a diffusion region formed by diffusion of impurities from the silicon film to the silicon substrate and an impurity region of a different conductivity type formed on the main surface of the silicon substrate can be suppressed. 2) The area can be reduced, so that the junction capacitance between the silicon film and the silicon substrate can be reduced, and also the leak current at the junction between the silicon film and the silicon substrate can be reduced. In addition, diffusion of impurities from the silicon film in a direction parallel to the main surface of the silicon substrate can be suppressed, so that a diffusion region formed by diffusion of impurities from the silicon film to the silicon substrate has an electric field effect. When used as a part of the source / drain region of a type transistor, it is possible to prevent the punch-through resistance of the transistor from deteriorating. Furthermore, in the manufacture of the semiconductor device, there is an advantage that it is not necessary to increase the number of steps as compared with the related art.

A step of forming an interlayer insulating film on the silicon substrate; a step of forming a contact hole opening in the surface of the silicon substrate in the interlayer insulating film; and a step of forming a contact hole on the silicon substrate including the inside of the contact hole. Depositing an impurity diffusion preventing film having etching resistance to hydrofluoric acid, and depositing a silicon oxide film on the impurity diffusion preventing film including the inside of the contact hole;
Removing the silicon oxide film and the impurity diffusion preventing film by anisotropic dry etching to expose the silicon substrate surface; etching the exposed silicon substrate surface using hydrofluoric acid; Forming a silicon film containing impurities inside the hole so as to be in contact with the exposed silicon substrate. Therefore, in a semiconductor device manufactured using the manufacturing method, the silicon film and the silicon substrate The contact area between the diffusion region and the diffusion region formed by diffusion of the impurity from the silicon film to the silicon substrate and the impurity region of the different conductivity type formed on the main surface of the silicon substrate can be reduced. Can reduce the junction area (PN junction) of the silicon film and the silicon substrate It is possible to reduce the junction capacitance of,
The leak current at the junction between the silicon film and the silicon substrate can also be reduced. In addition, diffusion of impurities from the silicon film in a direction parallel to the main surface of the silicon substrate can be suppressed, so that a diffusion region formed by diffusion of impurities from the silicon film to the silicon substrate has an electric field effect. When used as a part of the source / drain region of a type transistor, it is possible to prevent the punch-through resistance of the transistor from deteriorating.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view showing a method of manufacturing the semiconductor device in the first embodiment of the present invention in the order of steps;

FIG. 3 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor device in the first embodiment of the present invention in the order of steps.

FIG. 4 is an essential part cross sectional view showing the manufacturing method of the semiconductor device in the first embodiment of the present invention in the order of steps;

FIG. 5 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor device in the first embodiment of the present invention in the order of steps.

FIG. 6 is an essential part cross sectional view showing the manufacturing method of the semiconductor device in the first embodiment of the present invention in the order of steps;

FIG. 7 is an essential part cross sectional view showing the manufacturing method of the semiconductor device in the first embodiment of the present invention in the order of steps;

FIG. 8 is a fragmentary cross-sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor device in the second embodiment of the present invention in the order of steps;

FIG. 10 is a fragmentary cross-sectional view showing a method of manufacturing the semiconductor device in the second embodiment of the present invention in the order of steps;

FIG. 11 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor device in the second embodiment of the present invention in the order of steps;

FIG. 12 is a fragmentary cross-sectional view showing a method of manufacturing the semiconductor device in the second embodiment of the present invention in the order of steps;

FIG. 13 is a fragmentary cross-sectional view showing the method of manufacturing the semiconductor device in the second embodiment of the present invention in the order of steps;

FIG. 14 is an essential part cross sectional view showing the manufacturing method of the semiconductor device in the second embodiment of the present invention in the order of steps;

FIG. 15 is a cross-sectional view of a main part showing a structure of a conventional semiconductor device.

FIG. 16 is a fragmentary cross-sectional view showing a conventional method of manufacturing a semiconductor device in the order of steps;

FIG. 17 is a fragmentary cross-sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps;

FIG. 18 is a fragmentary cross-sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps;

FIG. 19 is a fragmentary cross-sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps;

20 is a fragmentary cross-sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps; FIG.

FIG. 21 is an essential part cross sectional view showing the conventional method of manufacturing the semiconductor device in the order of steps;

[Explanation of symbols]

1 silicon substrate, 1a contact surface between silicon film and silicon substrate, 1b contact surface between impurity diffusion prevention film and silicon substrate, 3 interlayer insulating film, 4 contact holes,
6, 6a impurity diffusion preventing film, 7 silicon oxide film,
8 Silicon film, 10, 10a Impurity diffusion preventing film.

Claims (8)

[Claims] 1. An interlayer insulating film formed on a silicon substrate and having a contact hole opening on the surface of the silicon substrate, and hydrofluoric acid formed on a part of the opening of the contact hole on the surface of the silicon substrate. An impurity diffusion preventing film having etching resistance to the silicon substrate; and an impurity formed inside the contact hole and having a contact surface with the silicon substrate in a portion of the silicon substrate surface where the impurity diffusion preventing film is not formed. A semiconductor device, comprising: a silicon film; and a contact surface between the silicon film and the silicon substrate on the surface of the silicon substrate, surrounded by the impurity diffusion preventing film. 2. The semiconductor device according to claim 1, wherein the impurity diffusion preventing film is made of silicon carbide. 3. An interlayer insulating film formed on a silicon substrate and having a contact hole opening on the surface of the silicon substrate; and an interlayer insulating film formed inside the contact hole and opening the contact hole on the surface of the silicon substrate. A portion having a contact surface with the silicon substrate, an impurity diffusion preventing film having etching resistance to hydrofluoric acid, and a part of a portion of the silicon substrate surface where the contact hole is opened, formed inside the contact hole. A silicon film containing impurities having a contact surface with the silicon substrate; and a contact surface between the silicon film and the silicon substrate on the surface of the silicon substrate. A semiconductor device, which is surrounded by a contact surface. 4. The semiconductor device according to claim 3, wherein the impurity diffusion preventing film is a silicon nitride film. 5. A step of forming an interlayer insulating film on a silicon substrate, and a step of forming a contact hole opened on the surface of the silicon substrate in the interlayer insulating film by anisotropic dry etching using a gas system having a high carbon ratio. Forming and forming an impurity diffusion preventing film having etching resistance to hydrofluoric acid on the surface of the silicon substrate where the contact hole is opened; and depositing a silicon oxide film on the silicon substrate including the inside of the contact hole Removing the silicon oxide film and the impurity diffusion preventing film by anisotropic dry etching to expose a portion of the silicon substrate where the impurity diffusion preventing film is not formed; Etching the surface with hydrofluoric acid; Method of manufacturing a semiconductor device and forming a silicon film containing an object in contact with the silicon substrate exposed above. 6. The method according to claim 5, wherein the impurity diffusion preventing film is made of silicon carbide. 7. A step of forming an interlayer insulating film on a silicon substrate, a step of forming a contact hole opened in the surface of the silicon substrate in the interlayer insulating film, and a step of forming a contact hole inside the contact hole on the silicon substrate. Depositing an impurity diffusion preventing film having etching resistance to hydrofluoric acid, depositing a silicon oxide film on the impurity diffusion preventing film including the inside of the contact hole, and forming the silicon oxide film by anisotropic dry etching. Removing the film and the impurity diffusion preventing film to expose the silicon substrate surface; etching the exposed silicon substrate surface using hydrofluoric acid; and silicon containing an impurity inside the contact hole. Forming a film in contact with the exposed silicon substrate. Production method. 8. The method according to claim 7, wherein the impurity diffusion preventing film is a silicon nitride film.