JP2709200B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a miniaturized structure of a semiconductor device.

[0002]

2. Description of the Related Art In recent years, in the field of semiconductor devices, technological development has been promoted for higher integration and higher speed of semiconductor devices with the expansion of higher demand. Both of these have opposite aspects, and there is a case where a high integration of a semiconductor device may hinder a high speed operation. Therefore, a technology that can realize both of these is very important.

[0003] High integration of a semiconductor device necessarily involves miniaturization of the semiconductor device or miniaturization of the structure of individual semiconductor elements constituting the semiconductor device.

FIG . 4 shows a MOS (Metal Oxide Semiconductor) .
FIG. 1 is a cross-sectional view showing a MOSFET (field effect transistor) disclosed in Japanese Patent Application Laid-Open No. 61-16573 as a conventional example intended for miniaturization of an element structure in a tor) type semiconductor device.

In FIG. 1, 1 is a MOSFET, 2 is a silicon substrate, 3 is a thin gate oxide film formed on the silicon substrate 2 and 4 is a polycrystalline silicon formed on the thin gate oxide film 3. Gate electrode.
Reference numerals 5 and 6 denote a source region and a drain region which are formed in the vicinity of the surface of the silicon substrate 2 at an interval from each other and in which impurities are diffused, and a surface region of the silicon substrate 2 between the source region 5 and the drain region 6. Form the channel region of the MOSFET. Reference numerals 7 and 8 are electrode conductive layers formed on the surfaces of the source region 5 and the drain region 6, respectively, and made of polycrystalline silicon. 9 is a field oxide film for element isolation, 10 is an interlayer insulating film, and 11 is an aluminum wiring layer. The electrode conductive layers 7 and 8 are formed in the source region 5.
And is formed to extend from the surface of drain region 6 to the upper surface of field oxide film 9 for element isolation. Furthermore,
Electrode conductive layers 7 and 8 are connected to aluminum wiring layer 11 through contact holes formed in interlayer insulating film 10 above field oxide film 9.

The conventional example has the following features from the viewpoint of miniaturization of the structure. (1) The shape of the gate electrode 4 is formed so as to give different gate electrode widths at the lower part and the upper part. That is, since the lower part of the gate electrode 4 is formed to have a small width, the MOSFE defined by this gate electrode width is formed.
The channel width of T can also be reduced. Further, since the upper portion of the gate electrode 4 is formed to have a large width, a reduction in the area of the cross-sectional area of the gate electrode 4 is suppressed. By suppressing the decrease in the cross-sectional area of the gate electrode 4 as described above, the increase in the wiring resistance of the gate electrode 4 is suppressed. (2) The contact between the source region 5 and the drain region 6 and the aluminum wiring layer 11 is made above the field oxide film 9 via the electrode conductive layers 7 and 8. Therefore, it is not necessary to secure a space for the source region 5 and the drain region 6 to directly contact the aluminum wiring layer 11. Thereby, the diffusion width of the impurities in source region 5 and drain region 6 can be reduced.

[0007]

In the conventional method of manufacturing a semiconductor device, a polycrystalline silicon layer (a part of the conductive layers 7 and 8 for electrodes) on the channel region for forming the channel region is removed. It is necessary to remove by etching. However, since this polycrystalline silicon layer has been formed directly on the silicon substrate 2, when this region is etched away, irregularities of about several hundred square meters of the polycrystalline silicon layer are reflected on the silicon substrate 2. Will be. As described above, if the silicon substrate surface has irregularities, particularly when a gate oxide film is formed by thermal oxidation, the surface irregularities become sharper and the gate breakdown voltage deteriorates.

The present invention has been made to solve such a problem, and has as its object to provide a method for manufacturing a semiconductor device having a flat channel region of a silicon substrate.

[0009]

A method for manufacturing a semiconductor device according to the present invention includes a step of rigidly polishing a conductive layer formed on a silicon substrate.

[0010]

According to the present invention, since the channel region is formed after the conductive layer of polycrystalline silicon is rigidly polished and flattened, irregularities on the silicon substrate are suppressed to several tens of mm or less, and the reliability of the gate insulating layer is reduced. The degree is improved.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings. 1 to 3 are cross-sectional views for explaining one embodiment of the present invention. As shown in FIG. 1A, after forming a groove in the silicon substrate 2, a so-called trench isolation region 2 in which an insulating film such as an oxide film is buried is formed. As shown in FIG. 1B, an electrode conductive layer 7 (or 8) made of polycrystalline silicon is formed on the silicon substrate 2 and the trench isolation region 12 by, for example, CV.
Deposit 5000 ° by Method D. At this time, the irregularities on the surface of the polycrystalline silicon electrode conductive layer 7 are about several hundreds of square meters. The electrode conductive layer 7 is rigidly polished to a thickness of about 2000 °. At this time, the unevenness on the surface of the electrode conductive layer 7 is about several Å. Thereafter, as shown in FIG. 1C, a thickness of 20 μm is formed on the conductive layer 7 for electrodes by a CVD method or the like.
An insulating layer, for example, an oxide film 13 of about 00 ° is formed. Further, as shown in FIG. 2A, after the insulating layer 13 and the electrode conductive layer 7 on the silicon substrate 2 serving as the channel region are etched to remove a part thereof, for example, an oxide film The sidewall 14 is formed. Thereafter, as shown in FIG. 2B, a gate oxide film 3 as a gate insulating film and a gate electrode 4 are sequentially formed. Further, C in FIG.
After the gate electrode 4 and the insulating layer 13 are etched into a desired pattern, as shown in FIG.
In the case of an OS transistor, the source region 5 and the drain region 6 are formed by implanting impurities such as boron and BF ₂ and performing heat treatment. Next, as shown in FIG. 3A, for example, a titanium silicide film 15 is formed on the gate electrode 4 and the electrode conductive layers 7 and 8 on the source 5 and the drain region 6 in a self-aligned manner. And to reduce the resistance of the wiring. Further, as shown in FIG.
An interlayer insulating film 10 made of a G film or the like is formed, contact holes are provided at predetermined locations, and a source region 5 and a drain region 6 are connected to a titanium silicide film 15 and aluminum connected to the electrode conductive layers 7 and 8 respectively. An aluminum wiring layer 11 made of an alloy or the like is formed.

Although the trench isolation is used as the isolation method in the above embodiment, the height from the surface of the silicon substrate is one.
Other methods may be used as long as the separation method is about 000 ° or less.

In the above embodiment, the conductive layers 7, 8 for electrodes are used.
Although an example in which an oxide film is used as the upper insulating layer 13 is shown,
Another insulating film such as a nitride film or a composite film thereof may be used.

Further, in the above embodiment, the example in which the source region 5 and the drain region are formed after the formation of the gate electrode 4 has been described. However, the source region 5 and the drain region may be formed before the formation of the gate electrode. May be.

[0015]

As described above, according to the present invention, a conductive layer of polycrystalline silicon on a silicon substrate to be a channel region is flattened by rigid polishing and then removed by etching to expose the silicon substrate. As a result, the silicon substrate hardly has irregularities as in the prior art, so that the gate insulating layer does not deteriorate,
There is an effect that the reliability of the device can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a part of an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating another part of the embodiment.

FIG. 3 is a cross-sectional view illustrating a remaining part of the embodiment.

FIG. 4 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 2 Silicon substrate 3 Gate insulating layer 4 Gate electrode 7, 8 Conductive layer for polycrystalline silicon electrode

Claims (1)

(57) [Claims] A step of forming a conductive layer on a silicon substrate; a step of rigidly polishing the conductive layer; a step of etching and removing a part of the rigidly polished conductive layer; Forming a gate insulating layer;
Forming a gate electrode on the gate insulating layer.