JPS62224077A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the density of integration by forming polycrystalline Si films or high melting-point metallic silicide films, layers thereof mutually differ, which have an area larger than contact holes and to which an impurity is doped, onto a diffusion layer between the mutually adjacent contact holes. CONSTITUTION:A layer insulating film 13 is shaped to the whole surface, and the predetermined sections of the layer insulating film 13 and a gate insulating film 3 to expose the surface of a source region 7. A polycrystalline Si film 14, to which an impurity such as phosphorus is doped and which is connected to the source region 7 and has a large area, is formed. A layer insulating film 9 is shaped to the whole surface, the prescribed sections of the layer insulating film 9 and the layer insulating film 13 are removed through etching to form contact holes 9a, 9b, and wirings 10, 11 are brought into contact with polycrystalline Si films 12, 14 through the contact holes 9a, 9b. Accordingly, the contact holes 9a, 9b can easily be shaped even when an MOSFET is fined, thus increasing the density of integration of an element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device with high integration density.

[Conventional technology]

4M bit dynamic RAM (Random Access Me), which has been researched and developed in recent years.
MOry) and 1M bit static RAM
In S LSI, the MOS that makes up these
With the miniaturization of FETs, it has become difficult to form contact holes for connecting wiring to the source and drain regions of MOS FETs.

The present inventors have studied - how to make wiring contacts to the source region and drain region of the MOS FET constituting the above-mentioned MOS LSI; The following is not a publicly known technique.

This is a technique studied by the present inventor, and its outline is as follows.

As shown in FIG. 3, in order to manufacture a conventional MOS LSItI, such as a dynamic RAM, first, a semiconductor substrate 1, such as a p-type Si (silicon) substrate, is coated with, for example, 5 iOz[l! Field insulation v2 like I and gate insulation INIA3tI-0 are then formed on top of this gate insulation film 3 with gate salt t44 and insulation! After forming the a film 5, using these as a mask, an n film is formed in the semiconductor substrate 1.
Implant type impurities with relatively low energy. Next, after forming an insulating film such as a SiO2 film on the entire surface, RIE (Reactive Ion Etchi)
By performing anisotropic etching using etching methods such as etching, sidewalls 6 made of an insulator are formed on the side surfaces of the gate salt ti4 and the insulator IIUS. Next, using this sidewall 6 as a mask, n-type impurities are ion-implanted into the semiconductor substrate 1 at a high concentration with relatively high energy, and then annealing is performed to electrically activate the impurities to form the source region 7 and the drain region. form 8. Next, after forming an interlayer insulating film 9 on the entire surface, predetermined portions of the interlayer insulating film 9 and gate insulating film 3 are removed by etching to form contact holes 9a and 9b. Next, deep portions 7a and 8a for preventing alloy spikes are formed in the source region 7 and drain region 8 by ion-implanting n-type impurities into the semiconductor substrate 1 with relatively high energy through these contact holes 9a and 9b. do. Thereafter, the wiring 1 is connected to the source region 7 and the drain region 8 through the contact holes 9a and 9b, respectively.
0,.

Contact 11.

Note that the portion 7 below the side surface of the gate electrode 4 of the source region 7 and drain region 8 formed as described above.
b and 8b are i-type, and the other parts are n'-type.

The source region 7 is formed by these n-type portions 7b and 8b.
And the electric field near the drain region 8 is relaxed. A MOS FET with such a configuration is LDD
(Light, ly Doped Drain
) structure is called MOS FET. MOS F'E having an LDD structure having the insulating film 5 and the side ri 6
T is, for example, IEEE Transactions on Electron Devices.
RANSACTIONS ON ELECTRON
DEVICES) VOL.

ED-29, NO, 4, 1982 ρ, 590-596
is shown.

[Problem that the invention seeks to solve]

In one photolithography step for forming the contact holes 9a and 9b described above, the field M edge film 2 is
Allowance from the end and side l! It is necessary to take into account the margin from 6 and allow for a margin for mask fitting. However, with the miniaturization of 1MO5FETs, the above-mentioned mask alignment margin has become extremely small, making mask alignment difficult and forcing the diameters of contact holes 9a and 9b to be reduced.

An object of the present invention is to provide a technique that can increase mask alignment margin in one photolithography process for forming contact holes.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

An overview of one typical invention disclosed in this application is as follows.

That is, an impurity-doped polycrystalline Si film or a high melting point total silicide film, which has different layers between adjacent contact holes and has a larger area than the contact hole, is provided on the diffusion layer, respectively. ing.

[For production]

According to the above-mentioned means, it is possible to sufficiently increase the margin for mask alignment in one photolithography process for forming a contact hole.

The configuration of the present invention will be explained below along with two embodiments.

In all the figures of the embodiment, parts having the same functions as those in FIG. 3 are denoted by the same reference numerals, and repeated explanation thereof will be omitted.

[Example 1] As shown in FIG. 1A, first, a field insulating film 2 and a gate insulating film 3, such as a SiOg film, are formed on a semiconductor substrate 1, such as a p-type Si substrate. Next, in this state, a polycrystalline Si film and a SiO2Pa film are formed on the entire surface of the semiconductor substrate 1.
Sequential deposition by t-CVD.

Then, by continuous etching using photolithography technology, a gate electrode 4 made of polycrystalline sig and an insulation s5 such as a SiO2 film are formed. By ion implantation using these as masks, phosphorus is introduced into the semiconductor substrate 1 in order to form shallow i-type semiconductor regions Fb, 8b with low impurity concentration. Next, the semiconductor substrate l
After depositing a SiO2 film on the entire upper surface by CvD, RIE
By performing anisotropic etching such as
Then, arsenic is implanted into the semiconductor substrate 1 to form a deep n° type semiconductor region with a high impurity concentration by ion implantation using the insulating films 5 and 6 (and the gate electrode 4) as a mask. A source region 7 and a drain region 8 are respectively formed by performing zero-order annealing to form an LDD structure MOS FET.The gate insulating film 3 on the zero-order drain region 8 is etched and removed. After forming polycrystalline Si [112 (shown in a patterned state in FIG. 1A) on the entire surface of the semiconductor substrate 1 to expose the surface of the drain region 8.

The polycrystal 5iffl12 is doped with an impurity such as phosphorus by ion implantation and diffusion to lower its resistance. Thereafter, by patterning the polycrystalline Si film, the polycrystalline 5i connected to the drain region 8 is
lli12 can be formed in a self-alignment line with respect to the gate electrode 4. This polycrystalline Si crotch 12 overlaps the gate electrode 4 and field insulating film 2, and has a sufficiently larger area than contact holes 9a and 9b to be formed later. Since the gate electrode 4 is covered (buried) with the insulating films 5 and 6, the polycrystalline Si film 12 can be stacked on the gate electrode 4 as described above.

Next, as shown in FIG. 1B, after forming a glabellar insulation film 13 such as a SiO2 film on the entire surface, predetermined portions of the interlayer insulating film 13 and the gate insulating film 3 are removed by etching to remove at least the source region. Expose the surface of 7. Next, a polycrystalline Si film 1 having a large area doped with an impurity such as phosphorus and connected to the source region 7 is formed using the same method as in the case of forming the polycrystalline silicon film 12 described above.
form 4. As is clear from the above, the polycrystalline Si films 12 and 14 have different layers.

Next, as shown in FIG. 1C, after forming an interlayer insulating FIA 9 such as a phosphosilicate glass (PSG) film on the entire surface, the glabellar insulating film 9 and a predetermined portion of the interlayer insulating film 13 are removed by etching. Contact holes 9a, 9
form b. Next, these contact holes 9a, 9
For example, A1 arrangement 1 is applied to the polycrystalline Si film 12.14 through b.
Contact A10.11. In this case, since the area of the polycrystalline Si film 12.degree. 14 is made sufficiently large, the margin for mask alignment in one photolithography step for forming the contact holes 9a, 9b can be made extremely large. Therefore, even if the MOSFET is made into a machine box, the contact holes 9a and 9b can be easily formed, so that the elements can be integrated at a high density. Furthermore, the diameters of these contact holes 9a and 9b can be made sufficiently large. Furthermore, since the polycrystalline Si films 14.12 are provided between the wiring 10.11 and the source region 7 and drain region 8, as described above, it is possible to prevent the occurrence of so-called alloy spikes. Moreover, for this reason, ion implantation for forming a deep diffusion layer for preventing alloy spikes can be omitted.

Further, since it is not necessary to perform ion implantation for forming this deep diffusion layer, there is no adverse effect on the i-type portions 7b and 8b provided in the source region 7 and drain region 8 for electric field relaxation.

[Example 2] In order to manufacture the MOS LSI according to Example 2,
As shown in FIG. 2A, in the same manner as in Example 1, a field insulating film 2 is first formed on a semiconductor substrate 1 such as a p-type Si substrate. Gate insulating film 3. Gate electrode 4. Insulating film 5 such as SiO2 film, for example insulating film 1 such as Si3N4 film
5. Side wall 6. A source region 7 and a drain region 8 are respectively formed.

The insulating film 15 is formed on the entire surface of the semiconductor substrate 1 by CVD or the like prior to patterning the gate electrode 4, and is then etched together with the insulating film 5 in etching for forming the gate electrode 4. Next, the gate insulating film 3 on the source region 7 and drain region 8 is removed by etching to expose the surfaces of the source region 7 and drain region 8.

Next, after forming polycrystalline 5ilIII12 (already patterned in FIG. 2A) on the entire surface, this polycrystalline Si film 12 is doped with an impurity such as phosphorus by ion implantation, diffusion, etc. . Next, on this polycrystalline Si film 12, an insulating film 16 such as an SiO2 film and an insulating film 17 such as an Si3N4 film are sequentially formed.
2 is patterned into the shape shown in FIG. 2A. As a result, a polycrystalline Si film 12 having a large area and connected to the drain region 8 is formed in a self-alignment line with respect to the gate electrode 4.

Next, by performing thermal oxidation in this state, as shown in FIG. 2B, the side surface of the polycrystalline Si film 12 is coated.

A SiO 2 film 18 continuous to the insulating film 16 has a film shape 8 .

Next, the insulating films 15, 17 and the SiO2 film 19 formed on the source region 7 formed during the thermal oxidation are removed by etching, as shown in FIG. 2C.

Polycrystalline Si [14] is formed on the entire surface, and this polycrystalline Si film 1
4 is doped with an impurity such as phosphorus.

Next, this polycrystalline Si film 14 is patterned into a predetermined shape. Thereby, the polycrystalline Si film 14 connected to the source region 7 and having a large area can be formed in a self-alignment line with respect to the gate electrode 4. Polycrystalline Si film 12
is covered (embedded) with an insulating film 16.18
Therefore, the polycrystalline Si film 14 can also be stacked on the polycrystalline Si film 12. In this case, there is no need to form a 1M insulating film.

There is also no need for alignment margin between the polycrystalline Si films 12 and 14.

After this, as shown in FIG. 2D, similarly to Example 1, an interlayer insulation layer [9] is formed on the entire surface, and then contact holes 9a and 9b are formed in this interlayer insulation film 9. , 9b, the wirings 11°lO are brought into contact with the polycrystalline Si films 12, 14, respectively. In this case, the area of the polycrystalline Si films 12.14 is made sufficiently large, and these polycrystalline Si films 12.14
Since the gate electrode 4 is provided in the self-alignment line with respect to the gate electrode 4, the mask alignment margin in one photolithography step for forming the contact holes 9a and 9b can be made extremely large as in the first embodiment. Therefore, even if the MOS FET is miniaturized, the contact hole 9
Since the elements a and 9b can be easily formed, the elements can be highly integrated. Further, the diameters of these contact holes 9a and 9b can be made sufficiently large. moreover.

The polycrystalline Si films 12, 14 described above can prevent alloy spikes from occurring, and therefore ion implantation for forming a deep diffusion layer for preventing alloy spikes can be omitted. Therefore, this ion implantation for forming a deep diffusion layer does not adversely affect the i-type portions 7b and 8b provided in the source region 7 and drain region 8 for electric field relaxation.

The invention made by the present inventor has been specifically explained above based on the above embodiments, but the present invention is as follows.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications may be made without understanding the gist thereof.

For example, in the second embodiment, the insulating film 15 can be omitted. Further, the gate electrode 4 is made of 1Mo.

It may be made of a film of a high melting point metal such as W, Ti, Ta, etc. or a silicide film thereof, or a film in which these films are stacked on a polycrystalline Si film. Moreover, the above-mentioned polycrystalline Si film 12.1
4 (7) generation Warini, MoSi 2 film, Wsiz r! A
A film in which a high melting point metal silicide film is laminated on a high melting point metal silicide film or a polycrystalline Si film may also be used. Furthermore, in the above two embodiments, the present invention is applied to a MOS
Although the present invention has been described in the case where it is applied to an LSI, it is also possible to apply the present invention to various other semiconductor integrated circuit devices.

〔Effect of the invention〕

The effects obtained by one representative invention among the inventions disclosed in this application will be briefly described.

It is as follows.

That is, it is possible to increase the mask alignment margin in one photolithography process for forming contact holes, and it is therefore possible to obtain a semiconductor integrated circuit device with high integration density.

[Brief explanation of drawings]

1A to 1C show a MOS according to Embodiment 1 of the present invention.
Cross-sectional views showing an example of an LSI manufacturing method in the order of steps, FIGS. 2A to 2D are 1 MOS according to Example 2 of the present invention
A cross-sectional view showing an example of an LSI manufacturing method in the order of steps. FIG. 3 is a cross-sectional view of a conventional MO3Lsi studied by the inventor. In the figure, 1... semiconductor substrate, 2... field insulating film, 3... gate insulating film, 4... gate electrode, 5.1
5゜16.17... Insulating film, 7... Source region, 8
Mountain drain region, 9, 13... interlayer insulating film, 1o, 1
1...Figure 1A Figure 18 Figure 1c Figure 2A Cause 2B Figure 2C Comparison

Claims (1)

[Claims] 1. A plurality of diffusion layers provided in a semiconductor substrate, an insulating film provided on the semiconductor substrate, and a plurality of insulating layers provided in order to bring wiring into contact with each of the plurality of diffusion layers. A semiconductor integrated circuit device comprising a plurality of contact holes provided in a film, the contact holes doped with impurities and having different layers between adjacent contact holes and having a larger area than the contact holes. A semiconductor integrated circuit device characterized in that a polycrystalline Si film or a high melting point metal silicide film is provided on each of the diffusion layers. 2. The semiconductor integrated circuit device according to claim 1, wherein the diffusion layer is a source region and a drain region. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the impurity is phosphorus. 4. The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the semiconductor integrated circuit device is a dynamic RAM. 5. The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the semiconductor integrated circuit device is a static RAM.