JPH0481323B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming contact holes for establishing electrical connections.

[Technical background of the invention and its problems]

In recent years, semiconductor devices have become smaller and more highly integrated, and so-called integrated circuits (ICs), large-scale integrated circuits (LSIs), and even ultra-LSIs have been prototyped and developed. In order to improve the integration density of semiconductor devices, especially integrated circuits, it is necessary to further reduce the dimensions of the elements constituting the circuits. For this reason, there has been remarkable progress in microfabrication technology, and the development of step-and-repeat methods, reduction exposure methods, electron beam exposure methods, X-ray exposure methods, etc. is progressing.

However, it is not easy to accurately form fine patterns and replace them with semiconductor element structures, and various problems remain to be solved. For example, reduction of processing dimensions has many problems in terms of accuracy and reliability, and in particular, formation of fine hole patterns (contact holes) is always considered to be the most difficult due to its shape. In other words, 10: which can resolve a groove pattern with a line width of about 1 [μm]:
Even if a 1-reduction projection type exposure device is used, it is practically difficult to resolve an aperture pattern of 1 [μm] x 1 [μm]. ], the resolution at the periphery of the exposed area will drop significantly, and the aperture pattern that can be used in practice will have dimensions of 1.5 [μm]×1.5 [μm] or more. Furthermore, even if a resist pattern with an opening size of about 1 [μm] is formed, it is difficult to check this pattern using normal optical methods.
It is not possible to monitor process variations, etc. This difficulty increases as the minimum resist pattern becomes smaller, and a scanning electron microscope with high resolution and magnification is required for monitoring, which increases the cost and time required for monitoring. .

In addition, the openings made by anisotropic dry etching, which is usually used to form micro-openings, have a steep upper part of the opening, and the smaller the opening size, the more the wiring metal will adhere to the inside of the formed opening. As a result, the film thickness becomes thinner at the bottom and side walls of the aperture, reducing reliability. Furthermore, when anisotropic dry etching is used, traps and pinholes are generated in the insulating film due to ion bombardment received by the object to be etched during dry etching and static electricity generated on the surface of the object to be etched.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that can reliably form fine contact holes for connecting electrode wiring, and that can contribute to miniaturization and higher integration of integrated circuits. It is in.

[Summary of the invention]

The gist of the present invention is to first form a spacer film that is recessed from the insulating film toward the edge of the contact hole on the insulating film in which the contact hole is to be formed, and then to form a stacked film of the spacer film and the insulating film so that the desired contact hole is formed. By forming a large-diameter hole and forming a new insulating film on the sidewall of this hole in a self-aligned manner, it is possible to provide a margin for the pattern dimension when forming the hole, and also to create a large diameter hole at the edge of the contact hole. The purpose is to create a gentle taper on the surface of the insulating film.

That is, in the present invention, when forming a contact hole in a first insulating film, which is an interlayer insulating film provided on a semiconductor substrate, to be connected to a substrate diffusion layer or a base electrode wiring under this insulating film, First, a spacer film is formed on the first insulating film so as to be recessed from the insulating film with respect to the edge of the contact hole, and then an opening with a diameter larger than that of the desired contact hole is formed in the laminated film of this spacer film and the first insulating film. form a pore. Next, the entire surface is covered with a second insulating film, and this is dry-etched so that the second insulating film remains only on the side walls of the opening in a self-aligned manner, thereby obtaining a contact hole of a desired diameter. The surface of the insulating film has a gentle taper at the edge of the contact hole.

Here, in order to improve the processing accuracy of the contact hole, it is important to perform the step of leaving the second insulating film on the side wall of the hole in a self-aligned state without mask alignment. In this case, it is desirable to provide a second insulating film over the entire surface and then etch the entire surface of the insulating film using an anisotropic dry etching method. At this time, the process of forming the second insulating film uses low pressure chemical vapor deposition (LPCVD), which can form fine holes with good coverage.
CVD method is preferred. Furthermore, in order to form minute openings with high precision, it is desirable to use photolithography using a resist, an anisotropic dry etching method, or the like. In addition, since the spacer film is primarily used as a stopper during dry etching of the second insulating film, Al, Cr,
With metals such as Ti, metal silicide films, semiconductors, and insulator films,
A material that serves as a mask for anisotropic dry etching of the second insulating film is preferred, and a polycrystalline silicon film is particularly preferred. When a polycrystalline silicon film is used, it is not only extremely effective because it has a large selectivity in anisotropic dry etching with respect to the silicon oxide film or silicon nitride film used as the first or second insulating film. Helps prevent damaged layers and pinholes during directional dry etching. Furthermore, polycrystalline silicon is more thermally stable than metals such as Al and can be treated at high temperatures, so it is effective as a spacer film. Furthermore, if a low-temperature film formation method such as ion plating or plasma CVD is used to form the second insulating film, it is necessary to avoid high-temperature processes after forming the wiring because it will generate hills or react with Si at high temperatures. It can also be applied to the formation of contact holes on Al wiring, which is required.

〔Effect of the invention〕

According to the present invention, when forming a contact hole,
The size of the opening to be patterned can be made larger than the desired contact hole diameter. In other words,
Since the minimum dimension that must be formed in patterning technology can be increased, it is extremely effective in forming fine contact holes that are at or below the patterning limit. Moreover, since the width of the second insulating film left on the side wall of the opening can be controlled with high precision without a mask alignment process, fine contact holes can be formed with a high yield. Therefore, it is effective for miniaturizing and highly integrating semiconductor devices, especially integrated circuits. Furthermore, monitoring of the resist pattern used to form the openings can be facilitated. for example,
Assuming that the desired contact hole diameter is 1 [μm] x 1 [μm] and a second insulating film with a width of 0.3 [μm] is left on the side wall of the hole, the hole size of the resist pattern is
1.6 [μm] x 1.6 [μm] is sufficient. This is a dimension that can be easily confirmed using an optical microscope or the like.

Furthermore, by forming the spacer film on the first insulating film and using it as a mask for anisotropic dry etching, damage to the first insulating film during dry etching and increase in pinholes are reduced.
Furthermore, by controlling the shape of the spacer film, it is also possible to form a more gradual taper at the top of the opening. In particular, if the spacer film is processed to have apertures that are slightly larger than the apertures provided in the first insulating film, the slope at the top of the apertures will be smoother.

Furthermore, the method of the present invention can reduce the overlap margin provided around the contact hole due to mask misalignment or the like. This is Si
A case in which a contact opening is formed in a diffusion layer wiring provided on a substrate will be specifically explained as an example. 1st
As shown in the figure, in general, in order to form a contact hole 12 of dimension D _C on a diffusion layer 11 (line width D _L ), the width of the diffusion layer is changed at the contact hole 12 .
S _CF must be expanded on both sides. Here S _CF is
It is expressed as S _CF =S _M +S _P. S _M is a margin dimension that takes into account the mask alignment error between the diffusion layer 11 and the contact hole 12 , and S _P is a margin dimension that takes into account variations in the processing dimensions of the diffusion layer 11 and the contact hole 12 . In other words, only the diffusion layer 11 in S _CF
If the edge of the contact hole 12 is not formed outside the contact hole 12, the error caused by S _M and S _P will cause the contact hole 12 to overlap the field insulating film outside the diffusion layer 11, causing the field insulating film to deteriorate. This causes the inconvenience that it is removed by etching when forming the contact hole. In Figure 1, the width of the diffusion layer is
D _L and contact dimension D _C are shown as the same dimensions. On the other hand, when the method of the present invention is used, the diffusion layer 21 spreads at the contact 22 shown in FIG.
S' _CF is expressed as S' _CF =S' _M +S' _P -T. S′ _M is a margin dimension that takes into account the mask alignment error between the diffusion layer 21 and the contact hole 22, S _P is a margin dimension that takes into account the variation in the processing dimensions of the diffusion layer 21 and the contact hole 22, and T is This is the thickness of the second insulating film remaining on the side wall of the opening. Here, S _M and S′ _M , S _P and
Assuming that _S'P are approximately equal, _S'CF may be smaller than _SCF by an amount corresponding to the film thickness T. That is, by using the method of the present invention, it is possible to reduce the dimensional spread of the diffusion layer 21 around the contact hole 22 by T on one side. To simplify the explanation, we have shown the margin dimensions for the combination of the diffusion layer and the contact hole, but of course, the same applies to the case between the gate electrode, the first layer Al wiring, and the contact hole, etc. between the wiring and the contact hole. effect can be obtained.

[Embodiments of the invention]

3A to 3E are cross-sectional views showing a manufacturing process for forming a contact hole for a diffusion layer in a MOS type semiconductor device as a reference example for explaining the present invention in detail.

First, a P-type silicon substrate 31 with a specific resistance of 5 to 50 [Ωcm] is prepared, and a field insulating film 32 is embedded in the element isolation region of this substrate 31.
Form the gate electrode (not shown) of the MOSFET,
Next, diffusion layers 33 such as a source and a drain are formed by ion implantation. After that, the substrate surface is covered with a first insulator, for example, a 1 μm SiO ₂ film 34 by CVD, and then a 1000 Å polycrystalline silicon film 35 is deposited as a spacer film by low pressure CVD.
(a). Thereafter, a desired opening resist pattern 36 is formed, the polycrystalline silicon film 35 is etched away using this resist pattern 36 as a mask, and then the SiO ₂ film 3 is removed by an anisotropic dry etching method.
4 is selectively removed to form a contact hole (b). At this time, as shown in the figure, the field insulating film 32 is
It may be overetched by about 3000 Å. Next, the resist pattern 36 is removed and the substrate surface is
After treatment and cleaning with O ₂ plasma, acid, etc., depressurize
A SiO ₂ film 37 is formed as a second insulating film by CVD method (c). Here, the thickness of the formed film is 3000 Å, but there is no particular restriction on the thickness of the formed film. Next, the entire surface of the substrate is anisotropically dry etched to form a SiO ₂ film 37.
is removed by etching, leaving the SiO ₂ film 37 only on the side wall of the contact hole (d). In this way, the contact hole is tapered such that the opening diameter at the top becomes smaller than that at the bottom. Thereafter, the polycrystalline silicon film 35 is removed, and electrode wiring 38 in contact with the n ⁺ layer 33 is formed by vapor deposition and patterning of Al (e).

Thus, according to this reference example, a fine contact hole with a taper on the side wall can be formed with a high yield. Further, according to this reference example, by providing a spacer film and dry etching the first insulating film, it is possible to reliably prevent unnecessary damage and pinholes from occurring.

In addition, in the above reference example, as the second insulating film
Although the SiO ₂ film produced by the LPCVD method was used, the present invention is not limited to this. For example, by using a plasma CVD method or an optical CVD method in which a film is formed while irradiating light, the second insulating film can be formed at a lower temperature, thereby avoiding the disadvantages caused by high-temperature treatment. These are particularly effective when forming contact holes on Al wiring, etc., which are particularly susceptible to high temperature processing. Furthermore, before forming the second insulating film by LPCVD or the like, it is also possible to oxidize the surface of the diffusion layer to form an oxide film, and then form the second insulating film.

Furthermore, by thermally nitriding the substrate surface before forming the first insulating film and forming a nitrided layer on the surface of the diffusion layer and the element isolation insulating film, drying of the SiO ₂ film in the subsequent process is facilitated. It can also be used as a stopper during etching. Furthermore, although the explanation has been made using a polycrystalline silicon film as a spacer film, the invention is not limited to this.
A similar effect can be obtained by using a metal film such as Cr or Cr which acts as a stopper during etching of the second insulating film. In particular, it is preferable to use a conductive film as the spacer film because it prevents local charge-up during anisotropic dry etching and reduces the occurrence of damage and pinholes in the insulating film.

FIGS. 4a to 4d show, as an embodiment of the present invention, a manufacturing process for forming a contact hole on a diffusion layer wiring in a MOS type semiconductor device, similar to the reference example. Portions corresponding to those in the reference example are given the same reference numerals as in the reference example. First, do the same as the reference example,
After forming a SiO ₂ film 34 as a first insulating film and a polycrystalline silicon film 35 as a spacer film on the substrate and forming a resist pattern 36, the polycrystalline silicon film 35 is selectively removed by an anisotropic dry etching method. . Next, the polycrystalline silicon film 35 is etched using, for example, isotropic dry etching in CF ₄ /O ₂ gas.
Retract by 0.2μm. The retreat dimension can be appropriately set depending on the pattern size. Next, the SiO ₂ film 34 is selectively removed using an anisotropic dry etching method to form an opening larger than the desired opening size (a). After removing the resist pattern 36 and cleaning the substrate surface, a SiO ₂ film 37 is formed as a second insulating film by the LPCVD method (b). At this time, as shown in the figure, the polycrystalline silicon film 35 recedes at the edge of the opening, so that the
The surface of the SiO ₂ film 37 has a gentler taper than that of the reference example. Next, the substrate surface is subjected to anisotropic dry etching to etch the SiO ₂ films 37 and 34, thereby forming contact openings having a gentler taper than in the reference example (c). After this, electrode wiring 38 is formed (d).

Here, as a method for receding the edges of the polycrystalline silicon film, etching the polycrystalline silicon film by anisotropic dry etching and then side etching by isotropic dry etching was used, but the present invention is not necessarily limited to this. do not have. For example, it is also possible to perform side etching by wet etching. It is also possible to include a step of receding the edge of the polycrystalline silicon film 35 after anisotropic dry etching of the SiO ₂ film 34, which is the first insulating film. Furthermore, it is also possible to perform etching of the polycrystalline silicon film 35 only by isotropic etching without anisotropic dry etching.

According to this example, in addition to the effects of the reference example,
The taper at the upper part of the contact hole becomes more gentle, thereby reliably preventing disconnection of the electrode wiring. Another advantage of this embodiment is that by receding the edge of the polycrystalline silicon film below the edge of the resist pattern, it is possible to clearly observe whether a fine resist pattern is reliably formed. is obtained.

[Brief explanation of the drawing]

1 and 2 are diagrams showing contact hole patterns for explaining the effects of the present invention, and FIG.
Figures a to e are cross-sectional views showing the manufacturing process of a reference example for explaining the present invention in detail, and Figures 4 a to d are cross-sectional views showing the manufacturing process of the embodiment of the present invention. 31...Si substrate, 32...field insulating film,
33... Diffusion layer, 34... SiO ₂ film (first insulating film), 35... Polycrystalline silicon film (spacer film),
36...Resist pattern, 37...SiO ₂ film (second insulating film), 38... Electrode wiring.

Claims (1)

[Claims] 1. A step of forming a first insulating film to serve as an interlayer insulating film on a semiconductor substrate, a step of forming a spacer film made of a different material on this first insulating film, and a step of forming a spacer film made of a different material from the first insulating film, a step of forming a contact hole in a laminated film of insulating films, a step of retreating the aperture edge of the spacer film with respect to an aperture edge of the first insulating film, and then forming a second insulating film on the entire surface. etching the second layer by dry etching using the spacer film as a mask.
The insulating film is removed to expose the first insulating film at the edge of the opening, and the exposed first insulating film and second insulating film are etched to form a second insulating film only on the side wall of the contact hole. a step of leaving the film in a self-aligned manner and smoothing the exposed edge of the opening formed by the first insulating film; 1. A method of manufacturing a semiconductor device, comprising the step of forming an electrode wiring that contacts an already formed base electrode wiring.