JPS59181614A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To give the size of a pattern an allowance, and to fine an integrated circuit and increase the degree of integration of the circuit by forming a spacer film on an insulating film, shaping an opening having a diameter larger than a desired contact hole to the laminated films and forming a insulating film on side walls through a self-alignment. CONSTITUTION:The surface of a substrate is coated with an SiO2 film 34 as a first insulating film, and a polycrystalline Si film 35 is deposited as a spacer film. A resist pattern 36 for a desired opening is formed, the polycrystalline Si film 35 is removed through etching while using the pattern 36 as a mask, and the SiO2 film 34 is removed selectively to shape a contact hole. The resist pattern 36 is removed, and an SiO2 film 37 is formed as a second insulating film. The SiO2 film 37 is removed through etching, and the SiO2 film 37 is left only on the side wall section of the contact hole. Consequently, a taper is formed to the contact hole so that the diameter of an upper opening is made smaller than that of a bottom. The polycrystalline Si film 35 is removed, and an electrode wiring 38 being in contact with an n<+> layer 33 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for forming contact holes for establishing electrical connections.

[Technical background of the invention and its problems]

In recent years, semiconductor devices have become smaller and more highly integrated.1.
Scrap integrated circuit (IC), large-scale integrated circuit (LSI),
Furthermore, prototypes of VLSIs have been developed4, and in order to improve the integration density of semiconductor devices, especially integrated circuits, it is necessary to further reduce the dimensions of the elements that make up the circuits.

For this reason, there has been remarkable progress in microfabrication technology, and the development of reduction exposure methods such as step and repeat methods, as well as electron beam exposure methods and xH exposure methods, is progressing.

However, it is not easy to accurately form fine patterns and replace them with semiconductor element structures.
Various problems remain to be resolved. - For example, the reduction of processing dimensions has many problems in terms of accuracy and reliability, and in particular, the formation of fine hole patterns (contact holes) is considered to be the most difficult, considering its shape.

In other words, even if a 10:1 reduction projection type exposure device capable of resolving a groove pattern with a line width of about 1 [μm] is used, it is practically difficult to resolve an aperture pattern with a line width of 1 [μrr+)Xl [μm]. In particular, the Uki product for one exposure is 101 mm.
]X10[:+nm], the resolution at the periphery of the exposure area is significantly reduced, and the aperture pattern that can be used in practice has dimensions of 15[μm]X1.5[:μm] or more. Let's do it. Unfortunately, even if a resist pattern with an opening size of about 1 [μm] is formed, it is difficult to check this pattern using normal optical methods, and it is necessary to monitor process variations. I can't. This difficulty increases as the minimum pattern of the resist becomes smaller, and monitoring requires a scanning electron microscope with high resolution and magnification, and the cost and time required for monitoring are extremely large. Become.

In addition, the hole formed by anisotropic dry etching, which is commonly used to form fine holes, has a steep upper part, and the smaller the hole is, the more the wiring metal is applied inside the formed hole. It becomes difficult to attach the film, and the film thickness becomes thinner on the inner bottom surface and side wall of the hole, reducing reliability. Furthermore, when anisotropic dry etching is used, holes, cracks, and pinholes are generated in the insulating film due to ion bombardment received by the object to be etched, static electricity generated on the surface of the object, etc. during dry etching.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that can reliably form fine contact holes for connecting electrode wiring, and that can contribute to miniaturization and higher integration of integrated circuits. It is in.

[Summary of the invention]

The main points of the present invention are: - First, a spacer film is formed on an insulating film in which a contact hole is to be formed, and an opening having a diameter as large as the desired contact hole is formed in the laminated film of the spacer film and the insulating film.
By forming a new insulating film on the side wall of the opening with self-alignment, the pattern size when forming the opening has a margin.

That is, in the present invention, when forming a contact hole in a first insulating film provided on a semiconductor substrate to be connected to a substrate diffusion layer or a base electrode wiring under this insulating film,
First, a spacer film is formed on the first insulating film, and then an opening having a diameter larger than the desired contact hole is formed in the laminated film of the spacer film and the first insulating film. Next, the entire surface is covered with a second insulating film, and this is dry-etched so that the second insulating film remains only on the side walls of the hole in a self-lined manner, thereby obtaining a contact hole of the desired diameter. be.

Here, in order to improve the processing accuracy of the contact hole, it is important to perform the step of leaving the second insulating film on the side wall of the hole in a self-lined state without mask alignment. It is preferable to provide a second insulating film over the entire surface and then to etch this insulating film over the entire surface using an anisotropic dry etching method. At this time, the second
The insulating film is formed using the low pressure vapor deposition method (LP (:VD) method), which can form fine holes with good coverage.
The CVD method is preferred. Furthermore, in order to form minute openings with high precision, it is desirable to use photolithography using Renos, an anisotropic dry etching method, or the like.

Furthermore, since the spacer film is primarily used as a filler during dry etching of the second insulating film, AI!
r cr l Metals such as T1, metal silicide films, semiconductors,
An insulating film that serves as a mask for anisotropic drying and etching with respect to the second insulating film is preferable, and a polycrystalline silicon film is particularly preferable. When using a polycrystalline silicon film, the first
Also, it is not only extremely effective because it has a large selectivity in anisotropic dry etching with respect to silicon oxide film or silicon nitride film used as the second insulating film, but also removes the damage layer during anisotropic dry etching. and helps prevent pinholes. Furthermore, polycrystalline silicon is more thermally stable than metals such as A1 and can be treated at high temperatures, so it is effective as a spacer film. Furthermore, if a low-temperature film formation method such as ion blating or plasma CVD is used to form the second insulating film, high-temperature processes after wiring formation must be avoided because hillocks may occur or react with Si at high temperatures. The present invention can also be applied to forming contact holes on Al wiring, which is required.

〔Effect of the invention〕

According to the present invention, when forming a contact hole, the size of the opening to be patterned can be made larger than the desired contact hole diameter. In other words, it is possible to increase the minimum size that must be formed in the patterning technique, which is extremely effective in forming fine contact holes that are at or below the patterning limit. Moreover, since the width of the second insulating film left on the side wall of the opening can be controlled with high precision without a mask alignment process, fine contact holes can be formed with a high yield. Therefore, it is effective for miniaturizing and highly integrating semiconductor devices, especially integrated circuits. Furthermore, monitoring of the resist pattern used to form the openings can be facilitated. For example, if the desired contact hole diameter is 1 [μm]
X1 [μm], and a second hole with a width of 03 [μm] is placed on the side wall of the opening.
If an insulating film is left behind, the regimen) /? The dimensions of the damaged openings may be 16 [μm] xi, 6 [μm]. This is a dimension that can be easily confirmed using an optical microscope or the like.

Furthermore, by forming a spacer film on the first insulating film and using it as a mask for anisotropic drying and etching, the first
Damage to the insulating film during drying and etching and increase in pinholes are reduced. Furthermore, by controlling the shape of the spacer film, it is also possible to form the chi-ri at the top of the opening even more smoothly. In particular, if the spacer film is processed to have apertures that are slightly larger than the apertures provided in the first insulating film, the slope at the top of the apertures will be smoother.

Furthermore, the method of the present invention can reduce the overlap margin provided around the contact hole due to mask misalignment or the like. This will be specifically explained by taking as an example the case where a contact opening is formed in a diffusion layer wiring provided on an 81 substrate. As shown in FIG. 1, generally the diffusion layer 11
(Line width DL) Dimensions above. In order to form the contact hole 12, the width of the diffusion layer at the contact hole 12 must be reduced to S. Both sides must be expanded by F. Here, ScF is S. It is designated as F-8M+SP. SM
S is a margin dimension that takes into account the mask alignment error between the diffusion layer 1 and the contact hole 12, and S is a margin dimension that takes into account variations in the processing dimensions of the diffusion layer 11 and the contact hole 12.

That is, unless the edge of the diffusion layer 11 is formed outside the contact hole 12 by ScF, the contact hole 12 will overlap the field insulating film outside the diffusion layer 11 due to errors caused by SM and SP. A problem arises in that the field insulating film is etched away when forming the contact hole. In FIG. 1, for simplicity, the width of the diffusion layer and the contact dimension DC are shown as the same dimension. - When using the method of Rikiki's invention, the spread S5F of the diffusion layer 21 at the contact 22 shown in FIG.
It is represented by S knee T.

S4 C is a margin dimension that takes into consideration the mask alignment error between the diffusion layer 21 and the contact hole 22, St is a margin dimension that takes into consideration the variation in the processing dimensions of the diffusion layer 21 and the contact hole 22, and Ti/i, the opening This is the thickness of the second insulating film remaining on the side wall of the hole.

Here, assuming that SM and 84 and SP and 86 are almost equal, S5I is S. Compared to FK, it can be made smaller by the equivalent of the film thickness T. That is, by using the method of the present invention, it is possible to reduce the dimensional spread of the diffusion layer 21 around the contact hole 22 by T on each side. To simplify the explanation, we have shown the margin dimensions for the combination of the diffusion layer and the contact hole, but of course, in the case of a dart electrode, first cut A/wiring and contact hole, etc. Similar effects can be obtained between them.

[Embodiments of the invention]

FIGS. 3(a) to 3(,) are cross-sectional views showing a manufacturing process for forming a contact hole for a diffusion layer in an MO8 type semiconductor device as an embodiment of the present invention.

First, a P-type silicon substrate 31 with a specific resistance of 5 to 50 [Dctn] is prepared, and after the element isolation region-field insulating film 32'ff of this substrate 31 is buried, an MO8
A FETO electrode (not shown) is formed, and then a diffusion layer 33 such as a source and a drain is formed by ion implantation.
It is covered with a 5iO7 film 34 of 1 .mu.m by D.D., and then a 10007 polycrystalline silicon film 35 is deposited as a suction film by low pressure CVD (a). Thereafter, a desired opening resist pattern 36 is formed, and the polycrystalline silicon film 3 is etched away using the resist 1 and the turf 36 as a mask, and then S is etched by an anisotropic dry etching method.
Contact holes are formed by selectively removing the r02 film 34 (b). At this time, the field insulating film 32 may be over-etched by about 1000 to 3000× as shown in the figure. Next, the Lenost pattern 36 is removed, and the substrate surface is treated and cleaned with 02 plasma, acid, etc., and then a SiO2 film 37 is formed as a second insulating film by a low pressure CVP method (C). Here, the thickness of the formed film is 3000X, but there is no particular restriction on the thickness of the formed film. Next, the entire surface of the substrate is anisotropically dry etched to remove the 5i02 film 37, leaving the S102 film 37 only on the sidewalls of the contact holes (d). In this way, the contact hole is formed with a chi/saw shape such that the opening diameter at the top is smaller than that at the bottom. Thereafter, the polycrystalline silicon film 35 is removed, and electrode wiring 38 in contact with the layer 33 is formed by vapor deposition and patterning of Al (e).

Thus, according to this embodiment, it is possible to form a fine contact hole with a cheese on the 0(1j wall) with a high yield.Furthermore, according to this embodiment, the first By dry etching the insulating film, unnecessary damage and pinholes can be reliably prevented from occurring.

In the above embodiment, the insulating film of the whistle 2 is LP CV.
Although the SiO2 film produced by method D was used, the present invention is not limited thereto. For example, by using a plasma CVD method, a photo-CVD method in which a film is formed while irradiating light, etc., the second insulating film can be formed at a lower temperature, and problems caused by high-temperature processing can be avoided. These are particularly effective when forming contact holes on Al wiring, etc., which are particularly susceptible to high temperature processing. It is also possible to oxidize the surface of the diffusion layer to form an oxide film before forming the second insulating film by LPCVD or the like, and then form the second insulating film.

Furthermore, in the present invention, the surface of the substrate is thermally nitrided before forming the first insulating film, and a nitrided layer is formed on the surface of the diffusion layer and the surface of the insulating film for element isolation. It can also be used as a stopper during dry etching of the Sio2 film. Further, in this embodiment, a polycrystalline silicon film is used as the surface film, but the present invention is not limited to this. A similar effect can be obtained if the material serves as a stopper during film etching. In particular, when a conductor film is used as the waver film,
This is preferable because it prevents local charge-up during anisotropic dry etching and reduces damage and pinholes in the insulating film.

FIGS. 4(a) to 4(d) show a manufacturing process for forming a contact hole on a diffusion layer wiring in an MO8 type semiconductor device as another embodiment of the present invention, similar to the previous embodiment. 1. Parts corresponding to those in the previous embodiment are given the same reference numerals as in the previous embodiment. First, in the same manner as in the previous embodiment, a S]02 film 34 is formed as a first insulating film on a substrate. After forming a polycrystalline silicon film 35 as a spacer film and forming a resistor layer 736, the polycrystalline silicon film 35 is selectively removed by an anisotropic drying and etching method.

Next, the polycrystalline silicon film 35'e is retreated by 0.2 μm using, for example, isotropic dry etching in CF4102 gas. The retreat dimension can be set appropriately depending on the pattern size. Next, the SiO2 film 34 is selectively removed using an anisotropic dry etching method to form an opening larger than the desired opening size (a). After removing the resist pattern 36 and cleaning the substrate surface, a Sio2 film 37 is formed as a second insulating film by LPCVD.
Sur (b).

At this time, as shown in the figure, since the polycrystalline silicon film 35 recedes at the edge of the opening, the surface of the formed SiO2 film 37 has a more gentle taper than in the previous embodiment. Next, the surface of the substrate is anisotropically dry etched to etch the S r 02 film 37.34f, thereby forming a contact hole having a gentler tenorization than in the previous example (c). After this, electrode wiring 38 is formed (d).

Here, as a method for receding the edges of the polycrystalline silicon film, etching the polycrystalline silicon film by anisotropic dry etching and then side etching by isotropic dry etching was used, but the present invention is not necessarily limited to this. It's not a thing. For example, it is also possible to perform side etching by wet etching. In addition, the first insulating film S
It is also possible to include a step of recessing the edges of the polycrystalline silicon film 35 after anisotropic dry etching the iO2 film 34. Furthermore, it is also possible to perform etching of the polycrystalline silicon film 35 only by isotropic etching without anisotropic dry etching.

According to this embodiment, in addition to the effects of the previous embodiment, the tenor e above the contact hole becomes more gentle, thereby reliably preventing disconnection of the electrode wiring.

This embodiment has the advantage that by receding the edge of the resist pattern and the edge of the polycrystalline silicon film below it, it is possible to clearly observe whether a fine resist pattern has been reliably formed. can get.

[Brief explanation of drawings]

FIGS. 1 and 2 are diagrams showing patterns of contact holes for detailed explanation of the present invention, and FIGS. 3(a) to (,
) is a sectional view showing the manufacturing process of one embodiment of the present invention, and FIGS. 4(a) to 4(d) are sectional views showing the manufacturing process of another embodiment. 3 No. St substrate, 32 Field insulating film, 3
3... Diffusion layer, 34... S IO2 film (first insulating film), 35... Polycrystalline silicon film (suspension film),
36...Renostonoya turn, 37...S 102
film (second insulating film), 38...electrode wiring. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 35 Figure 3 R Figure 4

Claims (2)

[Claims] (1) forming a first insulating film on the semiconductor substrate;
A step of forming a spacer film made of a different material on the first insulating film, a step of forming a contact hole in the laminated film of these spacer films and the first insulating film, and then a step of forming a second insulating film on the entire surface. a step of forming an insulating film, a step of etching the second insulating film using a dry etching method to leave the second insulating film only on the side wall of the contact hole in a self-lined manner, and then etching the second insulating film through the contact hole. 1. A method for manufacturing a semiconductor device, comprising: forming an electrode wiring that contacts a base electrode wiring already formed under a substrate diffusion layer or a first insulating film. (2) The opening edge of the spacer film is set back with respect to the opening edge of the first insulating film.
A method for manufacturing a semiconductor device according to section 1.