JP2003007819A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method that can prevent a silicon nitride as an etching stopper from being etched off in the self-aligning contact process. SOLUTION: A gate electrode is formed by using a resist film for the region where a contact hole is formed on the gate electrode and a mask for a gate electrode formation made of a first silicon nitride for the region where a contact hole is not formed on the gate electrode.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a semiconductor device including a step of forming a contact hole without causing damage to a semiconductor substrate and a large amount of etching loss when forming a contact hole on a gate electrode covered with a silicon nitride film. And a method for producing the same. 2. Description of the Related Art As the integration and performance of semiconductor devices have advanced, the design rules for gate electrodes have been reduced to quarter micron or less, and semiconductor devices have been developed. It has become difficult to form contact holes due to the narrower source / drain regions of transistors constituting the device. Therefore, in such a highly integrated semiconductor device, in particular, an SRAM (Sta)
tic Random Access Memory)
In such cases, a self-aligned contact hole is often formed in a narrow source / drain region between gate electrodes. This contact hole is formed in the SAC (Se
(If Aligned Contact). In the etching for forming the SAC, the gate electrode must be surrounded by an insulator film serving as a stopper, for example, a silicon nitride film. However, when a borderless contact hole is formed in the source / drain region and the device isolation region, the gate electrode and the device isolation region serving as a borderless portion need to be covered with a silicon nitride film functioning as an etching stopper. On the other hand, a shared contact hole (in which one contact hole for a gate electrode and a source / drain region is shared) and a region where a contact hole is formed on a gate electrode are subjected to etching for forming a SAC. It is necessary to remove the silicon nitride film on the gate electrode. As a method for removing the silicon nitride film on the gate electrode, there is a method in which a resist film is formed on the silicon nitride film by photolithography, and dry etching is performed using the resist film as a mask. This method can be implemented relatively easily when the width of the gate electrode is wide and the margin for mask alignment is sufficient. However, if the width of the gate electrode becomes narrower in order to cope with high integration, it becomes difficult to align the mask by photolithography, and the opening of the mask will be in the source / drain region or the element isolation region. . If dry etching is performed in this state, in the source / drain regions, etching damage to the semiconductor substrate occurs in addition to the etch-off of the silicon nitride film provided for forming the SAC. In addition, even in the element isolation region, SAC
Etching off of the silicon nitride film provided for the formation occurs, and as a result, a large amount of etching loss occurs in the element isolation region at the time of forming the SAC. FIGS. 2A to 2J show a method of manufacturing a conventional semiconductor device having a structure in which an SAC, a contact on a gate electrode, and a shared contact coexist in a gate electrode covered with a silicon nitride film. An element isolation region 12 is formed on a semiconductor substrate (silicon substrate) 1, and after a gate insulating film (gate oxide film) 2 is formed, a conductive film (polycrystalline silicon film) 3 and a first silicon nitride film 4 are formed. Then, a resist film 5 for forming a gate electrode is formed on the silicon nitride film 4 (see FIG. 2A). Using the resist film 5 as a mask,
The first silicon nitride film 4 is etched by a dry etching technique (see FIG. 2B), and after removing the resist film 5 (see FIG. 2C), the etched first silicon nitride film 4 is removed. The gate electrode 3a is formed by etching the conductive film 3 by a dry etching technique as a mask (see FIG. 2D). Thereafter, a second silicon nitride film 6 is grown on the entire surface (see FIG. 2E), and is etched back, so that a side wall spacer made of the second silicon nitride film is formed on the side surface of the gate electrode 3a. 6a is formed (see FIG. 2F). Further, a third silicon nitride film 7 serving as an etch stopper at the time of forming the SAC is formed on the entire surface (see FIG. 2G). In FIG. 2G, since the side wall spacer is made of a silicon nitride film, a boundary with the third silicon nitride film is not shown. After the gate electrode 3a is covered with the silicon nitride film in this manner, a resist film 8 for opening a contact hole on the gate electrode is formed by photolithography. In this case, when the gate electrode width becomes narrow, it becomes difficult to align the mask by photolithography technology,
Part of the contact hole pattern of the resist film 8 is in a state (part A) over the source / drain region or the element isolation region 12 (see FIG. 2H). When dry etching is performed in this state, etching damage occurs on the semiconductor substrate 1 in the source / drain region, in addition to etching off the silicon nitride film 7 provided for SAC processing. Further, the silicon nitride film 7 provided for the SAC processing is also etched off in the element isolation region (see FIG. 2I). Further, a resist film 9 for forming the SAC, the contact hole on the gate electrode and the shared contact hole is formed by photolithography. Next, each contact hole is formed by dry etching using the resist film 9. In this case, a large amount of etch loss occurs in the element isolation region in the region (part A) where the silicon nitride film 7 is etched off (see FIG. 2 (j)). As described above, when a mask shift occurs in photolithography when a contact hole is formed on a gate electrode covered with a silicon nitride film, a part of the contact hole pattern in the resist film becomes a source / drain. In such a case, the silicon nitride film may be damaged by etching in the source / drain regions, and may be etched off in the source / drain regions, and may be etched off in the borderless device isolation regions. A large amount of loss of the silicon oxide film occurs during processing, and problems such as junction leak have occurred. SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention provides a method of forming a nitride film to serve as an etch stopper during SAC processing in a device isolation region that is damaged in a source / drain region or borderless. In order not to cause silicon etch-off, it is necessary to make a contact during the processing of the gate electrode so that the silicon nitride film is not formed on the gate electrode. The present inventors have found that the step of removing the silicon nitride film on the electrode can be eliminated, and reached the present invention. Thus, according to the present invention, on a conductive layer formed on a semiconductor substrate via a gate insulating film, a region for forming a gate electrode other than a region for forming a contact hole on the gate electrode in a later step is formed. A step of forming one silicon nitride film; a step of forming a resist film in a region where a contact hole is to be formed on the gate electrode; and a step of using the first silicon nitride film and the resist film as a first mask. Forming a gate electrode by etching the conductive layer, and removing the resist film, then forming a sidewall spacer made of a second silicon nitride film on the side surface of the gate electrode and the first silicon nitride film thereon. Forming a third silicon nitride film and an interlayer insulating film on the entire surface in this order; and forming a third nitride film using a second mask. Forming a contact hole by simultaneously performing a self-aligned contact etching using the recon film as a stopper and an etching for forming a contact hole on the gate electrode from which the resist film has been removed, with respect to the interlayer insulating film. A method for manufacturing a semiconductor device is provided. DETAILED DESCRIPTION OF THE INVENTION In the present invention, a region where a gate electrode and a source / drain region of a semiconductor device such as a transistor are connected by one contact hole or a region where a contact hole is formed on the gate electrode are formed. In order to omit the step of removing the silicon nitride film by etching, one of the features is that the silicon nitride film on the gate electrode which needs to be contacted when forming the gate electrode is removed in advance. Specifically, a gate insulating film, a conductive layer for forming a gate electrode, and a silicon nitride film are stacked on a semiconductor substrate, and a pattern for forming a gate electrode which does not need to be contacted is formed thereon with a resist film. . Using this resist film as a mask, only the silicon nitride film is dry-etched using the conductive layer as a stopper. Thereafter, the resist film is removed by O ₂ plasma ashing or the like. After that, a silicon nitride film is grown on the entire surface and etched back to form a side wall of the silicon nitride film on the side surface of the gate electrode.
A silicon nitride film serving as an etch stopper during C processing is formed on the entire surface. Conventionally, here, a step of removing the silicon nitride film on the gate electrode is required, and in addition to etching off the silicon nitride film, etching damage may occur on the semiconductor substrate. However, in the present invention, since this step is not necessary, there is little possibility that etching damage occurs. Further, an interlayer insulating film is formed on the entire surface, and an oxide film etching (SAC) using a silicon nitride film as an etch stopper by using a resist film for forming a contact which is borderless with respect to the narrow source / drain region and the element isolation region as a mask. )
Even if the etching is performed, since there is no etch-off in the previous step of the silicon nitride film serving as an etch stopper for the SAC etching, a large amount of loss in the element isolation region can be prevented. Hereinafter, the present invention will be described more specifically with reference to FIGS. 1 (a) to 1 (i). 1A to 1I are schematic cross-sectional process diagrams of a method for manufacturing a semiconductor device according to the present invention. In the figure, reference numeral 1 denotes a semiconductor substrate, 2 denotes a gate insulating film, 3 denotes a conductive layer, 4 denotes a first silicon nitride film, 5 denotes a resist film,
Reference numeral 6 denotes a second silicon nitride film, 7 denotes a third silicon nitride film, 8 denotes a resist film, 9 denotes a resist film, 10 denotes an interlayer insulating film, 11 denotes a resist film, and 12 denotes an element isolation region. First, as shown in FIG. 1A, a gate insulating film 2, a conductive layer 3, and a first silicon nitride film 4 are formed on a semiconductor substrate 1 having element isolation regions 12 formed at desired positions. The resist film 5 is formed on the first silicon nitride film 4 in a region where a gate electrode is desired to be formed. However, the resist film 5 is not formed in a region where a contact hole is desired to be formed on the gate electrode. The semiconductor substrate is not particularly limited, and an element substrate such as a silicon substrate,
A compound substrate such as a silicon germanium substrate may be used. In addition, as the element isolation region, a silicon oxide film formed by a LOCOS method, an impurity layer into which impurities are implanted at a high concentration, and the like can be given. Among these, it is preferable that the element isolation region is made of a silicon oxide film. As the gate insulating film, a silicon oxide film,
A silicon nitride film, and a laminate of these films.
Further, the thickness of the gate insulating film varies depending on the type, but can be, for example, 0.002 to 0.005 μm. The method of forming the gate insulating film depends on the type of the semiconductor substrate and the gate insulating film.
Method, sputtering method and the like. The conductive layer is not particularly limited as long as it is a material suitable for the gate electrode. For example, aluminum, metal layers such as copper, polycrystalline silicon,
Examples include a silicon-based layer such as a silicide of a high melting point metal (for example, titanium, tungsten, or the like), and a laminate of these layers. The thickness of the conductive layer varies depending on the type, but can be, for example, 0.1 to 0.3 μm. As a method for forming the conductive layer, a CVD method, a sputtering method, an epitaxial method, an evaporation method, or the like can be appropriately selected depending on the type. The thickness of the first silicon nitride film can be, for example, 0.1 to 0.3 μm. As a method for forming the first silicon nitride film, a CVD method, a sputtering method, or the like can be given. The method for forming the resist film is not particularly limited, and a known photolithography technique can be used. Next, as shown in FIG. 1B, the first silicon nitride film 4 is etched using the resist film 5 as a mask and the conductive layer 3 as an etch stopper. Here, dry etching is usually employed.
For example, using an RIE apparatus and a pressure of 50 to 100 mTorr
r, RF power 400 to 800 W, CHF ₃ : CF ₄ : A
r: O ₂ = 5 to 50 sccm: 5 to 50 sccm: 50
２００200 sccm: a mixed gas plasma condition of 5 to 15 sccm. By this etching, the first silicon nitride film 4 in a region where a contact hole is desired to be formed is removed. Next, as shown in FIG. 1C, the resist film 5 is removed by a known method such as O ₂ plasma ashing. Next, as shown in FIG. 1D, a resist film 11 is formed on the conductive layer 3 in a region where a contact hole is desired to be formed. The method for forming the resist film is not particularly limited, and a known photolithography technique can be used. Next, as shown in FIG. 1E, the conductive layer 3 is etched using the first silicon nitride film 4 and the resist film 11 as a first mask and the gate insulating film 2 as an etch stopper. Here, dry etching is usually employed. For example, using an RIE device, pressure 3 to 1
0 mTorr, RF power 300 to 600 W, Cl ₂ :
HBr: He: O ₂ = 30-60 sccm: 100-1
50 sccm: 10 to 30 sccm: 5 to 15 sccm
Of mixed gas plasma conditions. This etching forms the gate electrode 3a. After forming the gate electrode, a source / drain region (not shown) can be formed by injecting impurities into the semiconductor substrate 1 using the gate electrode 3a as a mask. Next, as shown in FIG. 1F, after removing the resist film 11 by a known method such as O ₂ plasma ashing, a second silicon nitride film 6 is formed on the entire surface. The thickness of the second silicon nitride film is, for example, 0.05
０．１0.15 μm. As a method for forming the second silicon nitride film, a CVD method, a sputtering method, or the like can be given. Next, as shown in FIG. 1G, a sidewall spacer 6a made of silicon nitride is formed on the side surface of the gate electrode 3a by etching back the second silicon nitride film 6. Next, as shown in FIG. 1H, a third silicon nitride film 7 is formed on the entire surface. This silicon nitride film 7 serves as an etch stopper during SAC processing. The thickness of the third silicon nitride film is, for example, 0.02 to 0.05.
μm. As a method for forming the third silicon nitride film, a CVD method, a sputtering method, or the like can be given.
Note that, in FIG. 1H, since the side wall spacer is made of a silicon nitride film, a boundary with the third silicon nitride film is not shown. Next, as shown in FIG. 1I, after an interlayer insulating film 10 is formed on the entire surface, for example, a contact hole for forming a borderless contact hole with respect to a narrow source / drain region and an element isolation region is formed. A resist film (second mask) 9 having a pattern is formed, and the interlayer insulating film 10 is etched (for example, dry-etched) using the resist film 9 as a mask and the third silicon nitride film 7 as an etch stopper. This etching can include etching for forming a SAC, etching for forming a contact hole in a gate electrode, and etching for forming a shared contact hole. In this step, the third silicon nitride film 7 serving as an etch stopper is
Are not etched off, so that a large amount of loss in the element isolation region does not occur. Thereafter, the third silicon nitride film 7 existing at the bottom of the contact hole is also etched away to form each contact hole. The interlayer insulating film is not particularly limited as long as it is a material having a higher etching rate than the silicon nitride film, and any film made of a known material can be used. For example, an insulating film such as a silicon oxide film can be given. The thickness of the interlayer insulating film can be, for example, 0.7 to 1.5 μm. Examples of the method for forming the interlayer insulating film include a CVD method and a baking method.
The surface may be flattened by the MP technique. Thereafter, the resist film 9 is removed by a known method such as O ₂ plasma ashing. According to the method of the present invention, the number of steps of forming a resist film directly on a gate electrode for which a contact hole is desired to be formed (corresponding to FIG. 1D) is increased.
Since the steps of FIGS. 2H and 2I can be omitted from the conventional manufacturing method, one etching step can be omitted as a whole. According to the method of manufacturing a semiconductor device of the present invention, a silicon nitride film is not formed in a region on a gate electrode where a contact hole is formed in a gate electrode forming step. In order to form the contact hole only on the shared contact hole or the gate electrode, the step of removing the silicon nitride film can be omitted. Omission of this step can prevent damage to the semiconductor substrate. Also, contact holes (S) which are borderless with the element isolation region are formed in the narrow source / drain region.
Since etch-off of the silicon nitride film serving as an etching stopper when forming (AC) can be eliminated, a large amount of loss in the element isolation region during SAC processing can be prevented. As described above, a method for manufacturing a semiconductor device with improved yield and reliability can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic process sectional view of a method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a schematic cross-sectional process view of a conventional method for manufacturing a semiconductor device. DESCRIPTION OF REFERENCE NUMERALS 1 semiconductor substrate 2 gate insulating film 3 conductive layer 3 a gate electrode 4 first silicon nitride films 5, 8, 9, 11 resist film 6 second silicon nitride film 6 a sidewall spacer 7 third nitride Silicon film 10 Interlayer insulating film 12 Element isolation region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/11 H01L 27/08 102D F-term (Reference) 4M104 AA01 AA02 BB01 BB02 BB04 BB24 DD02 DD04 DD07 DD16 DD17 EE05 EE09 EE17 FF30 GG09 GG10 GG14 5F033 HH04 HH08 HH11 HH26 KK01 KK04 KK08 KK11 KK26 NN12 NN40 QQ09 QQ25 QQ31 QQ37 QQ48 RR04 RR06 SS08 SS11 SS22 TT08 5F048 AA09 BB01 DA01 BA01 BA01 BA01 BA01 BA01 DA01 BA01 JA36 JA37 JA39 MA03 MA15 PR03 PR06 PR07 PR09 PR29 PR40

Claims (1)

Claims: 1. A gate electrode is formed on a conductive layer formed on a semiconductor substrate via a gate insulating film, except for a region where a contact hole is formed on the gate electrode in a later step. Forming a first silicon nitride film in a region; forming a resist film in a region where a contact hole is formed on a gate electrode; forming a first silicon nitride film and a resist film in a first region; A step of forming a gate electrode by etching the conductive layer as a mask; and, after removing the resist film, a sidewall spacer made of a second silicon nitride film on the side surface of the gate electrode and the first silicon nitride film thereon. Forming a third silicon nitride film and an interlayer insulating film on the entire surface in this order; and using a second mask to strike the third silicon nitride film. Forming a contact hole by simultaneously performing a self-aligned contact etching as a stopper and an etching for forming a contact hole on the gate electrode from which the resist film has been removed, with respect to the interlayer insulating film. A method for manufacturing a semiconductor device.