JPH11135628A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To work a wiring film pattern into an exact desired shape and to prevent a wiring film from being etched at opening a contact hole. SOLUTION: This manufacture is provided with a process for forming a CVD oxidized film 108 on a semiconductor substrate 1, the process for forming a thermally oxidized film 109 on the CVD oxidized film 108, the process for forming a conductive film composed of a polycrystalline silicon film 110/tungsten silicide film 111, the process for forming a silicon nitride film 112 on the conductive film, the process for forming the CVD oxidized film 112 on the silicon nitride film 112, the process for patterning a CVD oxidized film 113 and the silicon nitride film 112 into a prescribed shape, the process for patterning the conductive film into the prescribed shape with the CVD oxidized film 113 and the silicon nitride film 112 as a mask, the process for removing the CVD oxidized film 113, the process for forming a nitride film sidewall and the process for forming the contact hole which reaches the semiconductor substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to patterning a wiring film formed on an interlayer insulating film and etching the interlayer insulating film to reach a semiconductor substrate between the wiring films. The present invention relates to a method for manufacturing a semiconductor device including a step of forming a contact hole.

[0002]

2. Description of the Related Art In semiconductor devices represented by dynamic random access memory (DRAM) and static random access memory (SRAM), high integration,
The device dimensions are being miniaturized for the purpose of higher performance and more functions.

By the way, KrF excimer laser beam lithography technology is used for forming a fine pattern having a size of 0.3 μm or less, and a chemically amplified resist having higher transparency is used as a resist. There is a problem that the wiring pattern is liable to be thinned or chipped due to halation or the like.

For this reason, an antireflection film is usually applied on a wiring layer to be patterned, and a chemically amplified resist is applied thereon, followed by exposure and development. Normally, the antireflection film is not developed, but is etched by dry etching using a chemically amplified resist as a mask. The selectivity to the chemically amplified resist at the time of the dry etching is as very small as about 1 to 1.5. For this reason, the chemically amplified resist is also etched to reduce the film thickness. When dry etching the wiring material using the chemically amplified resist as a mask, the resist film thickness of the mask becomes insufficient, and the patterning of the wiring layer is performed as desired. A problem arises that the shape cannot be made.

In order to avoid this, conventionally, an insulating film having an etching selectivity with respect to the wiring film is formed on the wiring film,
Patterning the insulating film with the resist mask,
Using this patterned insulating film as a hard mask,
A method of forming a wiring pattern by dry etching is used. Normally, a silicon oxide film formed by a low pressure chemical vapor deposition method is used for a hard mask such as polysilicon and tungsten polycide wiring.

On the other hand, in order to form a contact hole near the wiring film, in order to prevent the wiring film from being etched even when misalignment occurs, a stopper film made of a silicon nitride film is formed on the upper surface / side surface of the wiring film. Must be provided. In the dry etching of polysilicon, tungsten polycide, etc., the etching rate of polysilicon and tungsten polycide has a selectivity of 20 or more for a silicon oxide film, but 10 or less for a silicon nitride film. Since only an etching selectivity can be obtained, the silicon nitride film is insufficient as a mask for patterning the wiring film.

Therefore, when forming a conventional self-aligned contact hole for polysilicon and tungsten polycide wiring, a polysilicon / tungsten polycide layer is formed on an interlayer insulating film of a CVD silicon oxide film, and silicon nitride is formed thereon. A film and a CVD silicon oxide film are sequentially formed, and a silicon nitride film and C
The VD silicon oxide film is patterned.

Next, a wiring film is patterned using the patterned silicon nitride film and CVD silicon oxide film as masks, and then a silicon nitride film is formed on the entire surface.
By etching back the silicon nitride film, a sidewall is formed on the side surface of the wiring film, and a contact hole is formed in the interlayer insulating film using the silicon nitride film as a stopper film.

[0009]

However, in a conventional method for manufacturing a semiconductor device, a silicon nitride film and a C
Since a two-layer hard mask of a VD silicon oxide film is required, the height of the wiring layer is increased, and a global step in a memory cell where wirings are dense and a peripheral circuit portion having a low wiring density is increased. There has been a problem that pattern formation failure occurs due to insufficient focus or the like in a lithography process.

Therefore, according to the present invention, the wiring film pattern can be processed into a desired shape without reducing the thickness of the mask film. It is an object of the present invention to prevent a film from being etched and to realize a low step of a wiring layer.

[0011]

A method of manufacturing a semiconductor device according to the present invention comprises a first step of forming a first insulating film on a semiconductor substrate, and a step of forming the first insulating film on the first insulating film. A second step of forming a second insulating film different from the insulating film, a third step of forming a conductive film on the second insulating film, and the first and the second A fourth step of forming a third insulating film different from the second insulating film; and a fourth step different from the second insulating film and the third insulating film on the third insulating film. A fifth step of forming an insulating film, and a step of applying a resist film on the fourth insulating film, and patterning the fourth and third insulating films into a predetermined shape by etching using the resist film as a mask. Sixth step, After the sixth step, a seventh step of removing the resist film,
After the seventh step, an eighth step of patterning the conductive film into a predetermined shape using the third and fourth insulating films as masks, and after the eighth step, removing the fourth insulating film A ninth step, and after the ninth step, a tenth step of forming a fifth insulating film different from the first and second insulating films on the semiconductor substrate; and An eleventh step of etching a film to form a sidewall film on the side surface of the conductive film, and a contact reaching the semiconductor substrate to the first and second insulating films after the eleventh step. And a twelfth step of forming a hole.

Another feature of the present invention is that
After the twelfth step, a thirteenth step of forming a storage node electrode layer connected to the semiconductor substrate through the contact hole, and on the storage node electrode layer,
A fourteenth step of forming a dielectric film and a fifteenth step of forming a cell plate electrode layer on the dielectric film are provided.

Another feature of the present invention is that the first insulating film is a CVD silicon oxide film,
The third insulating film is a silicon nitride film, the fourth insulating film is a CVD silicon oxide film, and the second insulating film is formed on the first insulating film in the second step. A polycrystalline silicon film is formed, and the polycrystalline silicon film is formed by thermal oxidation.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a method of manufacturing a highly integrated semiconductor device according to an embodiment of the present invention in the order of steps. 1 (a), 1 (b), 1 (c)
2 is a sectional view in the direction perpendicular to the word line, FIG.
3B, 3A, and 3B are cross-sectional views in a direction perpendicular to the bit lines.

As shown in FIG. 1A, a necessary impurity is introduced into a necessary region in the vicinity of the main surface of the p-type silicon substrate 1 in advance, and an element isolation region is formed by using a known LOCOS method or STI method. After a field oxide film 101 is formed, the element formation region is thermally oxidized to form a gate oxide film 102. afterwards,
A gate wiring 103d made of a laminated film of a polysilicon film 103a doped with phosphorus, a tungsten silicide film 103b, and a silicon oxide film 103c is formed.

Next, the field oxide film 101, the gate wiring
Arsenic ions or phosphorus ions are implanted using 103 as a mask. Next, after a silicon oxide film is formed by a low pressure chemical vapor deposition method, the silicon oxide film is etched back to form a sidewall 104. Next, the field oxide film 101, the gate wiring 103
Then, arsenic ions or phosphorus ions are implanted using the side wall 104 as a mask to form the N + type source / drain region 105 in a self-aligned manner.

Next, as shown in FIG. 1B, a 100 nm-thick first silicon nitride film is formed by low pressure chemical vapor deposition.
An interlayer insulating film 106 is grown, and a bit contact pattern and a storage node contact pattern are formed using a photoresist (not shown) by a known reduction exposure method. next,
Using a dry etching method, for example, a parallel plate type etching apparatus and a photoresist as a mask, the first interlayer insulating film 106 is formed.
Is etched to form a first bit contact 2a and a first storage node contact 3a that reach the silicon substrate 1.

Next, as shown in FIG. 1 (c), a 100 nm-thick second silicon oxide film is formed by low pressure chemical vapor deposition.
A 400 nm-thick third interlayer insulating film 108 made of a BPSG film is grown on the interlayer insulating film 107 by a normal pressure chemical vapor deposition method, and then is reflowed and flattened. Next, a polysilicon film having a thickness of 50 nm to 100 nm is grown by low pressure chemical vapor deposition.
By annealing at 800 ° C., a fourth interlayer insulating film 109 of a silicon oxide film is formed.

Next, a bit contact pattern is formed on the fourth interlayer insulating film 109 with a photoresist (not shown) in accordance with the first bit contact 2a by a reduced exposure method, and using the bit contact pattern of the photoresist as a mask. The second interlayer insulating film 107, the third interlayer insulating film 108, and the fourth interlayer insulating film 109 are etched by a dry etching method, for example, using a parallel plate type etching device to form a bit contact 2 b reaching the silicon substrate 1.

Next, a 60 nm-thick phosphorus-doped polysilicon film 110 is grown by a low pressure chemical vapor deposition method, and a 200 nm-thick tungsten silicide film 111 is successively grown by a sputtering method or a CVD method.

Next, a 100 nm-thick fifth interlayer insulating film 112 made of a silicon nitride film is grown by low pressure chemical vapor deposition.
Subsequently, a 150 nm-thick sixth interlayer insulating film 113 made of a silicon oxide film is grown.

Next, as shown in FIG.
A bit wiring pattern is formed on the interlayer insulating film 113 using a photoresist (not shown) by a reduced exposure method. Here, to form a fine bit wiring pattern, an anti-reflection film (not shown) and a chemically amplified resist are applied, and exposure and development are performed using KrF excimer laser beam lithography, and dry etching is performed using the chemically amplified resist as a mask. The antireflection film is etched by etching.

The anti-reflection film is used for the purpose of preventing light reflected from the underlying tungsten silicide film 111 at the time of exposure, and preventing thinning and chipping of the bit wiring pattern due to halation or the like.

Next, the fifth interlayer insulating film 112 made of a silicon nitride film and the sixth interlayer insulating film 113 made of a silicon oxide film are dry-etched by using the bit line pattern of the photoresist as a mask, for example, a parallel plate type etching apparatus. After forming a bit wiring pattern on the fifth interlayer insulating film 112 and the sixth interlayer insulating film 113, the anti-reflection film and the chemically amplified resist are ashed on the bit wiring pattern of the photoresist by oxygen plasma. Remove.

Next, using the sixth interlayer insulating film 113 of the bit wiring pattern as a mask, the tungsten silicide film 111 and the phosphorus-doped polysilicon film 110 are dry-etched by a dry etching method, for example, a parallel plate type etching apparatus. Then, the polysilicon film 110 doped with phosphorus is continuously etched to form the bit wiring 4.

FIG. 2B shows a state in which the sixth interlayer insulating film 113 has been etched away by the HF vapor phase method. At this time, by etching the wafer at a wafer temperature of 12 ° C. to 15 ° C. with 0.48% HF concentration vapor, the polysilicon film formed by the low pressure chemical vapor deposition method is annealed to the fourth interlayer of the silicon oxide film. The sixth interlayer insulating film 113, which is a silicon oxide film formed by a low pressure chemical vapor deposition method, can be etched at an etching rate of 100 or more, for example, 15 nm / min with respect to the insulating film 109.

Next, a silicon nitride film having a thickness of 200 nm is formed by a low pressure chemical vapor deposition method, and etched back by a dry etching method to form a silicon nitride film sidewall 5 on the side wall of the bit wiring 3. I do.

Next, as shown in FIG. 3A, a storage node contact pattern 114 is formed on the fourth interlayer insulating film 109, the fifth interlayer insulating film 112, and the sidewalls 5 using a photoresist by a reduced exposure method. The storage node contact pattern 114 of the photoresist, the fifth interlayer insulating film 112 of the silicon nitride film, the sidewall 5,
The second interlayer insulating film 107, the third interlayer insulating film 108, and the fourth interlayer insulating film 109 are etched by dry etching using the third interlayer insulating film 106 on which the storage node contact pattern is formed as a mask, and reach the silicon substrate 1. A self-aligned storage node contact 3b is formed.

In dry etching of a silicon oxide film such as a BPSG film, a CF-based gas is used. However, since F has an etching property with respect to both the silicon oxide film and the silicon nitride film, F is supplied only to the silicon oxide film. Otherwise, the selection ratio is not good. In order to obtain a selectivity between the silicon oxide film and the silicon nitride film, a CF film is deposited as an etching protection film on the silicon nitride film sidewall 5 during etching by mixing a CO gas into an etching gas. The selectivity of the silicon oxide film 108 to the silicon nitride film side wall 5 was about 17.

Thereafter, as shown in FIG. 3B, the storage node 6 made of a phosphorus-doped polysilicon film is formed.
Then, a capacitor insulating film 7 made of an ONO film is formed, and a cell plate 8 made of a phosphorus-doped polysilicon film is formed to form a memory cell.

[0031]

As described above, according to the present invention, a CVD oxide film is patterned on a wiring film by a photolithography method, and the wiring film is patterned using the patterned CVD oxide film as a mask. The wiring film pattern can be processed into a desired shape without reducing the thickness of the mask film.

Also, when a contact hole is formed, a silicon nitride film is formed on the side surface / upper surface of the wiring film even when the mask is misaligned. This silicon nitride film functions as an etching stopper film. The wiring film is not etched.

Further, by providing a thermal oxide film on the interlayer insulating film, after the wiring film is patterned, when the CVD oxide film used as a mask for the wiring film is removed by wet etching, the thermal oxide film is removed. Since it serves as a mask to protect the underlying interlayer insulating film, CVD can be performed with good yield.
The oxide film can be removed, and the step of the wiring layer can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in a direction perpendicular to a word line, showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view in a direction perpendicular to a bit line, illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a cross-sectional view in a direction perpendicular to a bit line, illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2a 1st bit contact 2b Bit contact 3a 1st storage node contact 3b Storage node contact 4 Bit wiring 5 Sidewall 6 Storage node 7 Capacitive insulating film 8 Cell plate 101 Field oxide film 102 Gate oxide film 103a Phosphorus was doped. Polysilicon film 103b tungsten silicide film 103c silicon oxide film 103d gate wiring 104 sidewalls 105a, 105b source / drain regions, 106 first interlayer insulating film, 107 second interlayer insulating film 108 third interlayer insulating film 109 fourth interlayer insulating film 110 Phosphorus-doped polysilicon film 111 Tungsten silicide film 112 Fifth interlayer insulating film 113 Sixth interlayer insulating film 114 Storage node contact pattern

Claims (3)

[Claims] 1. A first step of forming a first insulating film on a semiconductor substrate, and forming a second insulating film different from the first insulating film on the first insulating film. A second step; a third step of forming a conductive film on the second insulating film; and forming a third insulating film different from the first and second insulating films on the conductive film. A fourth step of forming; a fifth step of forming a fourth insulating film different from the second insulating film and the third insulating film on the third insulating film; A sixth step of applying a resist film on the insulating film of the above, patterning the fourth and third insulating films into a predetermined shape by etching using the resist film as a mask, and after the sixth step, the resist A seventh step of removing the film, and after the seventh step, using the third and fourth insulating films as a mask An eighth step of patterning the conductive film into a predetermined shape, and after the eighth step, a ninth step of removing the fourth insulating film, and after the ninth step, on the semiconductor substrate, A tenth step of forming a fifth insulating film different from the first and second insulating films, and a tenth step of etching the fifth insulating film to form a sidewall film on a side surface of the conductive film. One step, and after the eleventh step, on the first and second insulating films,
A twelfth step of forming a contact hole reaching the semiconductor substrate. 2. A thirteenth step of forming a storage node electrode layer connected to the semiconductor substrate via the contact hole after the twelfth step; and forming a dielectric on the storage node electrode layer. 2. The method according to claim 1, further comprising: a fourteenth step of forming a film; and a fifteenth step of forming a cell plate electrode layer on the dielectric film. 3. The method according to claim 1, wherein said first insulating film is a CVD silicon oxide film, said third insulating film is a silicon nitride film, and said fourth insulating film is a silicon nitride film. The film is a CVD silicon oxide film. The second insulating film is formed by forming a polycrystalline silicon film on the first insulating film in the second step, and thermally oxidizing the polycrystalline silicon film. A method for manufacturing a semiconductor device, comprising: