JPH07135249A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device stable and high in contact properties, wherein a contact hole causes do short circuit between an upper wiring layer and a semiconductor substrate even if the contact hole is bored in an element isolating oxide film not aligning with the lower wiring layer when the contact hole is provided to the element isolating oxide film for connecting the upper wiring layer and a lower wiring layer together. CONSTITUTION:A semiconductor device is provided with an element isolating oxide film 102 formed on an Si substrate 101, at least a first insulating film 104 provided to the same region with the oxide film 102, a first wiring 106 formed on the insulating film 104, a second insulating film 107 formed on the first wiring 106, a contact hole 108 which is provided to the second insulating film 107 reaching the first insulating film 104 and the first wiring 106, and a second wiring 110 connected to the first wiring 106 through the intermediary of the contact hole 108, wherein the first insulating film 104 and the second insulating film 107 are two different films.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a contact portion between wirings.

[0002]

2. Description of the Related Art Generally, a semiconductor device uses a multilayer wiring of two or more layers because the circuit structure is complicated. Figure 7
Examples of a conventional semiconductor device having a multilayer wiring structure are shown in (a) and (b). In FIG. 7, (a) is a pattern plan view,
(B) is a sectional view taken along the line YY 'of (a). That is, the element isolation oxide film 402 is formed on the Si substrate 401, and the MOSFET gate electrode and the word line 404 extended therefrom are formed via the gate oxide film 403 on the Si substrate 401. On the word line 404,
Aluminum wiring 408 is formed via the interlayer insulating film 405, and the word line 404 and the aluminum wiring 408 are formed by the interlayer insulating film 4
05 is electrically connected through a contact hole 406 opened.

However, in order to configure as described above,
Misalignment of the mask between the contact hole 406 and the word line 404, the contact hole 406 and the word line 40.
Due to the dimensional variation of No. 4, when the contact hole 406 is opened as shown in FIG.
A short circuit with the substrate 401 may occur. Therefore, in order to prevent this, the contact margin of the word line 404 needs to have a margin ΔL. For example, although ΔL depends on the performance of the stepper, it is desirable that ΔL ≧ 0.3 μm. Therefore, in the portion where the contact hole 406 is formed, the width of the word line 404 is (contact width d ₄ ) +2.
It is necessary to take at least x (alignment margin ΔL). On the other hand, the wiring space S ₄ and the contact width d ₄ are determined by the limit of photolithography. For example, in a KrF excimer laser stepper, S ₄ ≧ 0.3 μm and d ≧ 0.3 μm, respectively. Therefore, the wiring pitch P ₄ of the word lines 404 is d ₄ +
ΔL + S ₄ or more, and applying the above example, P ₄ ≧ 0.
It becomes 9 μm.

[0004]

As described above, in the conventional semiconductor device, when the lower and upper wirings are connected by the contact holes, the margin .DELTA.L.times.2 is aligned with the contact portion of the lower wiring.
Therefore, the wiring pitch P ₄ is smaller than d ₄ + ΔL + S ₄ (for example, 0.9 μ in the above example).
cannot be made smaller than m), and high integration is difficult.

In view of the above point, the present invention can form a contact hole without short-circuiting with the underlying Si substrate without taking a wide area for a margin for a contact portion of a lower wiring. Therefore, it is an object of the present invention to provide a semiconductor device capable of reducing the wiring pitch and achieving high integration, and a manufacturing method thereof.

[0006]

The semiconductor device of the present invention comprises:
An element isolation oxide film formed on a semiconductor substrate, and a first element provided at least in the same region as the element isolation oxide film.
An insulating film, a first wiring formed on the first insulating film, and a second insulating film formed on the first wiring,
A contact hole which is formed in the second insulating film and reaches the first insulating film and the first wiring; and a second wiring which is connected to the first wiring through the contact hole. However, the first insulating film is different from the second insulating film.

Further, it is desirable that the first insulating film is a film whose etching rate at the time of forming the contact hole is 1/3 or less than that of the second insulating film.

Further, the first insulating film is formed on the element isolation oxide film.

Further, it is desirable that the width of the contact hole is equal to or larger than the wiring width of a portion of the first wiring in which the contact hole is formed.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming an element isolation oxide film on a semiconductor substrate and a step of selectively forming at least the same region as the element isolation oxide film in the first region
A step of forming an insulating film of
Forming the wiring, the step of forming a second insulating film on the first wiring, and the step of forming the first insulating film on the second insulating film.
The step of forming a contact hole reaching the insulating film and the first wiring, and the step of forming a second wiring connected to the first wiring through the contact hole, As the insulating film, a film different from the second insulating film is used.

Further, it is desirable that the first insulating film is a film whose etching rate at the time of forming the contact hole is 1/3 or less than that of the second insulating film.

Further, it is desirable that the first insulating film is selectively formed on the element isolation oxide film.
The step of forming the insulating film may include a step of selectively depositing a conductive film only on the element isolation oxide film and a step of oxidizing the conductive film to form the first insulating film. desirable. The conductive film is preferably Al or Cu.

Further, it is preferable that the width of the contact hole is equal to or larger than the wiring width of a portion of the first wiring in which the contact hole is formed.

[0014]

According to the present invention, the first structure is selectively formed in the same region as the device isolation oxide film (for example, either on the device isolation oxide film, under the device isolation oxide film, or in the device isolation oxide film). Forming the insulating film and forming the contact hole on the first insulating film, even if the first wiring is stepped off in the step of forming the contact hole, Since the first insulating film is different (desirably, the etching rate is 1/3 or less),
It serves as an etching stopper and prevents the contact hole from short-circuiting with the semiconductor substrate.

Therefore, when the contact hole is formed,
The process margin can be improved against misalignment and dimensional variation in the photolithography process, and overetching, and it is not necessary to widen the contact portion of the first wiring, and the wiring pitch of the first wiring can be reduced. It can be made small and highly integrated.

[0016]

【Example】

(Embodiment 1) FIGS. 1A and 1B show a semiconductor device having a multilayer wiring structure according to a first embodiment of the present invention. FIG. 1A is a plan view of a pattern, and FIG. a) X
It is a sectional view taken along the line X '.

In FIG. 1, 101 is a Si substrate and 102
Is an element isolation oxide film, 104 is an Al2O3 film, 105 is a gate oxide film, 106 is a gate electrode and a word line extending therefrom, 107 is an interlayer insulating film, 108 is a contact hole,
109 is a W plug filling the contact hole, 110
Is aluminum wiring.

Next, a method of manufacturing the semiconductor device of the first embodiment will be described. First, as shown in FIG. 2A, an element isolation oxide film 102 is formed on a Si substrate 101 which is a semiconductor substrate by, for example, the LOCOS method, and then an Al film 103 is selectively formed only on the element isolation oxide film 102. Form.
At this time, the Al film 103 is selectively deposited only on the oxide film, and S
As a method of not depositing on the i-substrate 101, there is, for example, an optical CVD method using dimethyl aluminum hydride (DMAH) as a raw material. For more details, Proceedings of the 39th Japan Applied Physics Association Joint Lecture (1992) p704,
30a-ZH-7, Hideki Ouchi et al.

Next, as shown in FIG. 2B, the Al film 103 is oxidized by a thermal oxidation method or an anodic oxidation method to form an Al2O3 film 104. After that, a gate oxide film 105, a gate electrode, and a word line 106 extending from the gate oxide film 105 are formed,
An interlayer insulating film 107 is formed on it. In this case, the interlayer insulating film 107 is composed of a SiO ₂ film (lower layer) of about 100 nm and B
A laminated structure of a PSG film (upper layer) was used.

Next, as shown in FIG. 2C, for example, CF ₄
Contact holes 108 are formed on the word lines 106 by a dry etching method using a CHF ₃ -based gas. At this time, the contact hole 108 must be formed only on the element isolation oxide film 102 in order to avoid destruction of the gate oxide film due to plasma damage due to dry etching for forming the contact hole. Therefore, due to mask misalignment and dimensional variations in the photolithography process,
When the word line 106 is stepped off when the contact hole 108 is formed, the Al2O3 film 104 on the element isolation oxide film 102 is reached. Here, the dry etching rate of the Al2O3 film is S
Al2O3 film 10 because it is about 1/7 or less of the iO ₂ film
4 serves as an etching stopper for the interlayer insulating film 107, does not reach the Si substrate 101, and does not short-circuit with the Si substrate 101. Therefore, the contact hole width d ₁ ≧ word line width L ₁ may be satisfied. Thereafter, as shown in FIG. 1, the contact hole 108 is filled with a W plug 109 or the like, and then an aluminum wiring 110 is formed.

Here, the Al film 103 is a metal film that can be selectively formed on the oxide film, and the oxide film is formed by the interlayer insulating film 107 (this oxide film) during dry etching for forming a contact hole. In case of SiO ₂ film or BPSG
Other film may be used as long as the dry etching rate is 1/3 or less than the film). For example, a Cu film may be used, and the Cu film is selectively formed only on the oxide film by the CVD method using Cu (HFA) _{2 as} a raw material. For details, see Y.HAZU
KI et.al., Tungsten and Other Advanced Metals for
See VLSI / ULSI Applications V, p351 (1990). Further, Cu ₂ O can reduce the etching rate to 1/3 or less with respect to SiO ₂ .

If an insulating film having a slower etching rate in dry etching of contact holes than the interlayer insulating film 107, for example, Si ₃ N ₄ or the like can be selectively deposited only on the oxide film, this film is deposited on the Al film 103. Alternatively, the Al ₂ O ₃ film 104 may be directly deposited as an etching stopper without being oxidized.

According to the above structure, the contact hole 1
At the time of forming 08, the contact hole 108 does not short-circuit with the Si substrate 101 and a stable contact can be formed without forming a wide area for a margin for the contact portion of the word line 106. The wiring pitch P _{1 of} 106 can be reduced, and the LSI can be highly integrated.

(Embodiment 2) FIG. 3 is a sectional view of a semiconductor device having a multilayer wiring structure according to a second embodiment of the present invention.

In FIG. 3, 201 is a Si substrate and 202
Is a pad oxide film, 203 is a Si ₃ N ₄ film, 205 is an element isolation oxide film, 206 is a gate oxide film, 207 is a gate electrode and a word line extending therefrom, 208 is an interlayer insulating film,
Reference numeral 209 is a contact hole, 210 is a W plug filling the contact hole, and 211 is an aluminum wiring.

Next, a method of manufacturing the semiconductor device of the second embodiment will be described. First, as shown in FIG. 4A, a groove is formed in an element isolation region on a Si substrate 201 which is a semiconductor substrate by dry etching. After that, a pad oxide film 202 of about 1 to 50 nm and Si _{3 of} about 10 to 500 nm are formed.
N ₄ film 203 and CVD for device isolation of 100 nm or more
An oxide film 204 is formed in this order to fill the groove. Here, the pad oxide film 202 is made of Si ₃ N ₄ film 203.
It is formed in order to relieve the stress on the substrate 201 and prevent the occurrence of defects, but it may not be particularly necessary. Next, full anisotropic etch back or CMP (Chemical Mechanical
Oxide film 204 by P olishing) method, Si ₃ N ₄ film 20
3. The pad oxide film 202 is removed and left only in the element isolation region. Next, as shown in FIG. 4B, the gate oxide film 206, the gate electrode, and the word line 2 extended from the gate oxide film 206.
07, an interlayer insulating film 208 is formed thereon.
In this case, the interlayer insulating film 208 is made of SiO _{2 having a} thickness of about 100 nm.
A laminated structure of a film (lower layer) and a BPSG film (upper layer) was used.

Next, as shown in FIG. 4C, for example, CF ₄
A contact hole 209 is formed on the word line 207 by dry etching using a CHF ₃ -based gas. At this time, as in the first embodiment, the contact hole 209 must be formed only on the element isolation oxide film 205. Therefore, when the contact hole 209 is formed due to mask misalignment and dimensional variation in the photolithography process. When the word line 207 is stepped off, the element isolation oxide film 205
The lower Si ₃ N ₄ film 203 is reached. Since the dry etching rate of the Si ₃ N ₄ film is about ⅕ or less of that of the SiO ₂ film, the Si ₃ N ₄ film 203 serves as an etching stopper for the interlayer insulating film 208 and reaches the Si substrate 201. Therefore, it does not short-circuit with the Si substrate 201. Therefore, the contact hole width d ₂ ≧ word line width L ₂ may be satisfied. After that, as shown in FIG.
Then, the aluminum wiring 211 is formed.
Here, the Si ₃ N ₄ film 203 is used as an interlayer insulating film 208 during the subsequent dry etching for forming a contact hole.
Another film may be used as long as it has a dry etching rate that is 1/3 or less slower than (in this case, a SiO ₂ film or a BPSG film), for example, an Al ₂ O ₃ film or the like.

According to the above structure, the contact hole 2
At the time of forming 09, the contact hole 209 is not short-circuited with the Si substrate 201 and a stable contact can be formed without forming a wide area for the contact portion of the word line 207 so that a stable contact can be formed. The wiring pitch of 207 can be reduced, and the LSI can be highly integrated.

(Embodiment 3) FIG. 5 is a sectional view of a semiconductor device having a multilayer wiring structure according to a third embodiment of the present invention.

In FIG. 5, 301 is a Si substrate and 302 is
Is an element isolation oxide film, 306 is an Al ₂ O ₃ layer, 307 is a gate oxide film, 308 is a gate electrode and a word line extending therefrom, 309 is an interlayer insulating film, 310 is a contact hole,
311 is a W plug for filling the contact hole, 312
Is aluminum wiring.

Next, a method of manufacturing the semiconductor device of the third embodiment will be described. First, as shown in FIG. 6A, pad oxide films 303 and 50
A Si ₃ N ₄ film 304 of 500 nm is formed in this order, and the pad oxide film 303 and the Si ₃ N ₄ film 304 in the element isolation region are removed by photolithography and dry etching. After that, the element isolation oxide film 302 is formed by thermal oxidation (LOCOS method). Next, the pad oxide film 3
03 and the Si ₃ N ₄ film 304 are not removed, and Al ⁺ is ion-implanted using the film as a mask. At this time, the implantation range needs to be set in the element isolation oxide film 302 and further set so as not to penetrate the pad oxide film 303 and the Si ₃ N ₄ film 304. Thus, the Al layer 305 is formed in the element isolation oxide film 302.

Thereafter, as shown in FIG. 6B, the Al layer 305 is oxidized by thermal oxidation again, and the Al ₂ O ₃ layer 3 is formed.
06 is formed. After that, the pad oxide film 303 and Si ₃
The N ₄ film 304 is entirely removed, a gate oxide film 307, a gate electrode and a word line 308 extending therefrom are formed, and an interlayer insulating film 309 is formed thereon. In this case, the interlayer insulating film 309 is a SiO ₂ film (lower layer) with a thickness of about 100 nm.
And a BPSG film (upper layer) are used.

Next, as shown in FIG. 6C, for example, CF ₄
A contact hole 310 is formed on the word line 308 by a dry etching method using a CHF ₃ -based gas. At this time, as in the first embodiment, the contact hole 310 has to be formed only on the element isolation oxide film 302. Therefore, when the contact hole 310 is formed due to mask misalignment and dimensional variation in the photolithography process. When the word line 308 is stepped off, the element isolation oxide film 302
The inner Al ₂ O ₃ layer 306 is reached. Since the dry etching rate of the Al ₂ O ₃ layer is about 1/7 or less that of the SiO ₂ film, the Al ₂ O ₃ layer 306 serves as an etching stopper for the interlayer insulating film 309 and does not reach the Si substrate 301. Therefore, it does not short-circuit with the Si substrate 301. Therefore, the contact hole width d ₃ ≧ word line width L ₃ may be satisfied. Then, as shown in FIG.
Then, the aluminum wiring 312 is formed.

Here, the implantation seed Al ⁺ has an oxide film whose interlayer insulating film 309 (in this case, an SiO ₂ film or a BP film) is formed during dry etching for forming a contact hole.
Another film may be used as long as the dry etching rate is 1/3 or less than that of the SG film).

According to the above construction, the contact hole 3
When forming 10, the contact hole 310 is not short-circuited with the Si substrate 301 and a stable contact can be formed without forming a wide area for a contact portion of the word line 308 to form a stable contact. The wiring pitch of 308 can be reduced, and the LSI can be highly integrated.

[0036]

As described above, according to the semiconductor device of the present invention, it can be formed within the same region as the element isolation oxide film (for example, on the element isolation oxide film, under the element isolation oxide film, or in the element isolation oxide film). Because an insulating film that selectively acts as an etching stopper is formed, when the contact hole is formed on the lower layer wiring on the element isolation oxide film, the width of the contact portion of the lower layer wiring is the width of the contact hole. Since the etching is stopped at the insulating film even when the wiring is stepped off, the contact hole does not short-circuit with the semiconductor substrate, and thus a wide area is provided for the contact portion of the lower layer wiring for a margin. No need to
The wiring pitch can be reduced and high integration can be achieved.

Further, according to the method of manufacturing a semiconductor device of the present invention, a selection is made within the same region as the element isolation oxide film (for example, either on the element isolation oxide film, under the element isolation oxide film, or in the element isolation oxide film). Since it is possible to form an insulating film that serves as an etching stopper, when the contact hole is formed on the wiring above the element isolation oxide film, the wiring is missed due to misalignment or dimensional variation in the photolithography process. However, since the etching is stopped at the insulating film, the contact hole does not short-circuit with the semiconductor substrate, and therefore misalignment and dimensional variation in the photolithography process, and the process margin with respect to overetching are increased, It is not necessary to widen the wiring in the portion where the contact is formed, It is possible to reduce the switch, it can be highly integrated.

[Brief description of drawings]

FIG. 1A is a pattern plan view of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along line XX ′ of the semiconductor device according to the same embodiment.

FIG. 2 is a sectional view of a manufacturing process in the first embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a sectional view of a manufacturing process in the example.

FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a sectional view of a manufacturing process in the embodiment.

FIG. 7A is a pattern plan view of a semiconductor device according to a conventional example, and FIG. 7B is a sectional view taken along line YY ′ of the semiconductor device according to the conventional example.

FIG. 8 is a sectional view of a manufacturing process of a semiconductor device in a conventional example.

[Explanation of symbols]

101 Si substrate 102 Element isolation oxide film 103 Al film 104 Al ₂ O ₃ film 105 Gate oxide film 106 Gate electrode and word line 107 Interlayer insulating film 108 Contact hole 109 W plug 110 Al wiring 201 Si substrate 202 Pad oxide film 203 Si ₃ N ₄ film 204 Oxide film 205 Element isolation oxide film 206 Gate oxide film 207 Gate electrode and word line 208 Interlayer insulating film 209 Contact hole 210 W plug 211 Al wiring 301 Si substrate 302 Element isolation oxide film 303 Pad oxide film 304 Si ₃ N ₄ film 305 Al injection layer 306 Al ₂ O ₃ film 307 Gate oxide film 308 Gate electrode and word line 309 Interlayer insulating film 310 Contact hole 311 W plug 312 Al wiring

Claims (11)

[Claims] 1. An element isolation oxide film formed on a semiconductor substrate, a first insulating film provided at least in the same region as the element isolation oxide film, and an element isolation oxide film formed on the first insulating film. A first wiring, a second insulating film formed on the first wiring, and a contact hole formed in the second insulating film and extending to the first insulating film and the first wiring, And a second wiring connected to the first wiring through the contact hole, wherein the first insulating film is a film different from the second insulating film. . 2. The first insulating film is a film whose etching rate when forming the contact hole is slower than ⅓ of that of the second insulating film. Semiconductor device. 3. The semiconductor device according to claim 1, wherein the first insulating film is formed on the element isolation oxide film. 4. The semiconductor device according to claim 1, wherein a width of the contact hole is equal to or larger than a wiring width of a portion of the first wiring where the contact hole is formed. 5. The first wiring is extended from a gate electrode of a MOSFET.
The semiconductor device described. 6. A step of forming an element isolation oxide film on a semiconductor substrate, a step of selectively forming a first insulating film in at least the same region as the element isolation oxide film, and the first insulating film. A step of forming a first wiring on the first wiring, a step of forming a second insulating film on the first wiring, and a step of forming the second insulating film on the first insulating film and the first wiring. And a step of forming a second wiring connected to the first wiring through the contact hole, wherein the first insulating film is the second insulating film. A method of manufacturing a semiconductor device, characterized in that a film different from the above is used. 7. The first insulating film is a film whose etching rate when forming the contact holes is slower than ⅓ or less of that of the second insulating film. Of manufacturing a semiconductor device of. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the first insulating film is selectively formed on the element isolation oxide film. 9. The step of forming the first insulating film includes the step of selectively depositing a conductive film only on the element isolation oxide film, and the step of oxidizing the conductive film to form the first insulating film. 9. The method for manufacturing a semiconductor device according to claim 8, further comprising a step of forming a film. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the conductive film is Al or Cu. 11. The semiconductor device according to claim 6, wherein a width of the contact hole is equal to or larger than a wiring width of a portion of the first wiring in which the contact hole is formed.