JPH04109654A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent thinning or opening of polysilicon wirings on an upper layer by overetching by providing an aluminum pad to become an etching stopper when a contact hole is formed on at least second and following polysilicon wirings from bottom. CONSTITUTION:An aluminum pad 8 to become an etching stopper when contact holes 11, 12 to an uppermost layer wiring are formed on at least second and following polysilicon wirings 6, 7 from bottom is provided. Accordingly, even if the holes 11, 12 are overetched at the time of etching, the wirings 6, 7 of the upper layer are protected by the pad 8 thereon. Therefore, a malfunction of thinning of the polysilicon wirings or punchthrough of etching can be prevented. Thus, unexpected etching of the wirings of the upper layer when the holes of different etching depths are formed can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a polysilicon multilayer wiring structure and a method for manufacturing the same.

[Prior Art] In a semiconductor device having a multilayer wiring structure, it is necessary to form contact holes in an insulating layer in order to establish electrical connections between the uppermost layer wiring and the lower and middle layer wirings.

For example, as shown in FIG.
When the layer wiring NlA 3, the second layer wiring 6, and the third layer wiring 7 are formed, the silicon dioxide film 2, which is an insulating layer, is used to make an electrical connection with the uppermost layer wiring (not shown). .3
．． Contact holes 10.11.12 are formed in 4.

On the other hand, recently, polysilicon electrodes, which are superior to aluminum electrodes, have come to be used, for example, as gate electrodes of MOS devices.

[Problem to be solved by the invention]

However, when the multilayer wiring as described above is formed of polysilicon, there are the following problems.

That is, when forming contact holes 10, 11, 12 in a multilayer wiring structure as shown in FIG. 4, the silicon dioxide film 2, 3, 4 must be etched. However, since the etching depths of the contact holes 10, 11, and 12 for the first layer wiring 5, the second layer wiring 6, and the third layer wiring 7 are different from each other, for example, the contact hole 2 of the third layer wiring 7 is not etched. Even after this, etching must be continued to open contact holes 11, 10 for the second layer wiring 6 and first layer wiring 5.

In this way, if etching is further performed after the contact hole 12 of the third layer wiring 7 is opened, the polysilicon of the third layer wiring 7 will also be etched, resulting in the polysilicon wiring 7 becoming thinner. Moreover, in some cases, holes may be formed.

The present invention has been made in view of the above problems, and
An object of the present invention is to provide a structure and method that prevents upper layer polysilicon wiring from being accidentally etched when forming contact holes with different etching depths in a semiconductor device having a polysilicon multilayer wiring structure.

[Means for Solving the Problems] In order to solve the above problems, the invention according to claim 1 of the present invention provides a semiconductor device having a polysilicon multilayer wiring structure, in which at least the base layer of the second layer from the bottom is The device is characterized in that an aluminum band is provided on the polysilicon wiring to serve as an etching stopper when forming a contact hole between the top layer wiring and the top layer wiring.

Further, the invention according to claim 2 of the present invention provides a method for manufacturing a semiconductor device having a polysilicon multilayer wiring structure, when forming at least the second layer of polysilicon wiring from the bottom. After patterning, an aluminum film is layered on top of it, and the aluminum film is
This method is characterized in that it includes a step of patterning into a pad shape larger than the contact hole to be formed.

[Effect]

In the present invention, even if excessive etching is performed when etching a contact hole for making an electrical connection with the top layer wiring, the upper layer polysilicon wiring is protected by the aluminum pad above it. Therefore, it is possible to prevent the polysilicon wiring from becoming unexpectedly thin and to prevent defects due to etching penetration.

Further, by performing sufficient etching, formation of defective contact holes due to remaining insulating film can be reliably prevented.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 3.

FIG. 1 shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Three layers of polysilicon wiring 5, 6, and 7 are formed on a semiconductor substrate 1. Then, the second layer of polysilicon wiring 6 formed on the first layer of 5i02 film 2 and the second layer of St
An Al pad 8 is formed on the third layer polysilicon wiring 7 formed on the O□ film 3.

This Al pad 8 is connected to contact holes 11 and 1 formed in the second layer SiO□ film 3 and the third layer SiO2 film 4.
It is formed in advance to be slightly larger than the size of No. 2.

Then, to form the contact holes 10, 11, 12, an etching mask with a predetermined pattern is used to etch the Si.
Etch the O□ film 2.3.4.

At this time, etching may be performed for a period of time to open the contact hole 10 of the polysilicon wiring 5 in the lowermost layer. Second
The layer polysilicon wiring 6 and the third layer polysilicon wiring 7 are not etched because the Al pad 8 exposed in the contact hole 11.12 acts as an etching stopper.

Note that the A1 pad 8 may be provided on the polysilicon wirings 6 and 7 above the second layer, but may also be formed on the polysilicon wiring 5 of the lowest layer. In that case,
Since the AI pad 8 formed on the polysilicon wiring 5 acts as an etching stopper, the contact hole 1
It is no longer necessary to precisely control the etching time for opening holes.

Next, with reference to FIGS. 2 and 3, a method for forming the AI pad 8 will be described, taking the case of the polysilicon wiring 7 as an example.

First, as shown in FIGS. 2(a) and 3(a),
Polysilicon wiring 7 is formed on iO□ film 3 by patterning using microfabrication technology.

Next, as shown in FIG. 2(b), the A1 film 8 is grown to 1,000 to 2
Approximately 000 people will be formed.

In F, as shown in Fig. 2 (C) and Fig. 3 (b),
Contact hole 12 (Fig. 2 (d) and Fig. 3 (C)
(see) An AI pad 8 having a size approximately 0.1 to 0.5 μm larger than the contact hole 12 is formed by patterning using a microfabrication technique in the portion where the hole is to be opened.

Next, as shown in FIG. 2(d) and FIG. 3(C),
After forming the SiO□ film 4, a contact hole 12 is formed by etching.

(Effects of the Invention) As described above, according to the present invention, when forming a contact hole between the uppermost layer wiring in a semiconductor device having a polysilicon multilayer wiring structure, the upper layer polysilicon is etched by excessive etching. It is possible to reliably prevent the wiring from becoming thin or open, and it can also reliably prevent the formation of film residue in the contact holes of the lowest layer polysilicon wiring due to insufficient etching, resulting in connection failures. Therefore, it is possible to provide a semiconductor device with high yield and high multiplication performance.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the wiring structure of a semiconductor device according to an embodiment of the present invention, FIGS. 2(a) to 2(d) are sectional views showing a method of forming polysilicon wiring, and FIGS. (C) is a plan view similar to the above, and FIG. 4 is a cross-sectional view showing the wiring structure of a conventional semiconductor device. In addition, in the reference numerals used in the drawings, 1 . . . semiconductor substrates 2, 3, 4 5.6.7 8 . . . 10, 11, etc. ... SiO□ film ... Polysilicon wiring AI band 12 ... Contact hole

Claims (2)

[Claims] (1) In a semiconductor device having a polysilicon multilayer wiring structure, an aluminum pad is placed on at least the second layer from the bottom to serve as an etching stopper when forming a contact hole between the top layer wiring and the top layer wiring. A semiconductor device characterized by being provided with. (2) In a method for manufacturing a semiconductor device having a polysilicon multilayer wiring structure, when forming at least the second layer of polysilicon wiring from the bottom, after patterning the polysilicon wiring, an aluminum film is laminated on top of the polysilicon wiring. , the aluminum film,
A method characterized by comprising a step of patterning into a pad shape larger than a contact hole to be formed.