JP2699389B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device.

[Conventional technology]

In recent years, there has been a need for more precise alignment of contact holes, which does not contribute to the integration of semiconductor devices.

FIG. 3 is a sectional view of a semiconductor chip for explaining an example of a conventional semiconductor device. As shown in FIG. 3, in the conventional semiconductor device, an oxide film 2 is formed on a semiconductor substrate 1,
Next, after forming a wiring on the oxide film and further forming an oxide film 4 on the entire surface of the substrate, a contact hole 6 reaching the wiring 3 is formed.

[Problems to be solved by the invention]

In the above-described conventional semiconductor device, since the side and top surfaces of the wiring 3 are all formed as the oxide film 4 by a single CVD method, as shown in FIG. In addition to causing a problem in wiring and the like, when a contact hole reaching the wiring 3 is formed, if the alignment accuracy between the wiring 3 and the contact hole 6 is poor, the contact along the side surface of the wiring 3 is caused in the etching of the contact hole 6. A hole is formed, and sometimes the contact hole reaches the lower layer of the wiring, and there is a disadvantage that the reliability of the connection is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which a step of an upper insulating film is reduced and a contact hole is not formed up to a side surface of a wiring even when contact hole alignment accuracy is poor. It is in.

[Means for solving the problem]

The semiconductor device of the present invention includes a step of depositing a first insulating film on a semiconductor substrate, a step of forming wiring on the first insulating film, and a step of depositing a second insulating film on the entire surface of the substrate. ,
Forming a third insulating film on the second insulating film so that a thickness of the wiring at a step side surface portion of the second insulating film is thicker than another portion; Removing the film and the second insulating film in a region other than the side surface of the wiring by anisotropic etching, and depositing a fourth insulating film having a higher etching rate than the second insulating film over the entire surface of the substrate And forming a contact hole reaching the wiring in the fourth insulating film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1E are cross-sectional views of a semiconductor chip showing a method of manufacturing a semiconductor device of a reference example related to the present invention in the order of steps. As shown in FIG. 1A, the semiconductor substrate 1
An oxide film 2 is deposited thereon by a thickness of 0.5 μm by CVD. Next, after depositing 0.5 μm of aluminum by sputtering, patterning is performed by photolithography to form the wiring 3. Next, as shown in FIG. 1B, an oxide film 4 is deposited on the entire surface of the substrate by a CVD method. Next, as shown in FIG. 1C, the oxide film 4 is left only on the side surface of the wiring 3 by anisotropic etching. Next, as shown in FIG. 1D, a plasma nitride film 5 is deposited on the entire surface of the substrate. Next, as shown in FIG. 1 (e), a pattern of the contact hole 6 is formed by photolithography, and CF4 is formed using the resist film as a mask.
Etching is performed using + O2 gas to form a contact hole reaching the wiring 3. Although the positions of the contact holes are depicted as being shifted in the figure, it is desirable that the positions be matched as much as possible. According to the present reference example, even if the resist pattern is formed large or the alignment accuracy is deteriorated, and the etching is performed with the pattern of the wiring 3 deviated, the etching rate of the oxide film 4 and the nitride film 5 with respect to CF4 + O2 is improved. Is different, the etching is delayed in the oxide film 4,
No contact hole is formed on the side surface of the wiring 3.

2 (a) to 2 (c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. Second
As shown in FIG. 5A, after the oxide film 4 is deposited on the entire surface of the substrate, a silica film 7 is further applied in the same manner as in the steps up to FIG. The silica film 7 is deposited particularly thickly on the step side surface of the oxide film 4. Next, as shown in FIG. 2B, the silica film 7 and the oxide film 4 are etched by anisotropic etching. At this time, since the silica film 7 is thick on the side surface of the step, the amount of etching of the oxide film 4 is reduced accordingly, and the step of the oxide film 4 remaining on the side of the wiring is reduced as compared with the case of the reference example. Next, as shown in FIG. 2C, a plasma nitride film 5 is deposited on the entire surface of the substrate, and a contact hole reaching the wiring 3 is formed by photolithography. In this embodiment, since the step of the oxide film 4 on the wiring side is reduced as compared with the above reference example, the step of the upper nitride film 5 can be reduced more effectively. Other effects are the same as those of the above-mentioned reference example.

In the embodiment described above, the oxide film is formed on the side surface of the wiring, and the nitride film is deposited thereon. However, the present invention is also applicable to the case where the nitride film is formed on the side surface of the wiring and the oxide film is deposited thereon. Similar effects can be obtained.

〔The invention's effect〕

As described above, according to the present invention, an insulating film is formed on the side surface of a wiring, and an insulating film made of a material different from that of the insulating film is deposited on the insulating film, so that the step of the upper insulating film is reduced. Even if the alignment accuracy is poor, since the material of the insulating film is different, the etching is blocked by the insulating film on the side surface of the wiring, and the contact hole is not formed on the side surface of the wiring. This has the effect of increasing the yield.

[Brief description of the drawings]

1 (a) to 1 (e) are sectional views showing a method of manufacturing a semiconductor device of a reference example related to the present invention in the order of steps, and FIGS. 2 (a) to 2 (c) explain an embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor chip for explaining an example of a conventional semiconductor device. 1 ... semiconductor substrate, 2 ... oxide film, 3 ... wiring, 4 ...
Oxide film, 5 ... nitride film, 6 ... contact hole

Claims (1)

(57) [Claims] A step of depositing a first insulating film on a semiconductor substrate; a step of forming wiring on the first insulating film; and a step of depositing a second insulating film on the entire surface of the substrate. The second
Forming a third insulating film on the insulating film so that the thickness of the wiring and the second insulating film at a step side surface portion is larger than other portions; and Removing the second insulating film in a region other than the side surface of the wiring by anisotropic etching;
A method of manufacturing a semiconductor device, comprising: depositing a fourth insulating film having an etching rate higher than that of the first insulating film; and forming a contact hole reaching the wiring in the fourth insulating film. .