JPH04139828A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the etching of organic coating and thus prevent the increase in contact resistance by forming a first opening in an organic coating, applying an insulating film over the coating, forming a second opening in the first opening, and applying another insulating film to cover the organic coating completely. CONSTITUTION:A lower wiring layer 2 is formed on a semiconductor substrate coated with a first insulating film 1, and a second insulating film 3 is overlaid. An organic coating 4 is applied to the film 3 and patterned to form a first opening 7A above the lower wiring layer 2. After a third insulating film 5 is formed over the surface including the opening 7A, the third and second insulating films 3 and 5 are etched to form a second opening 8A in the first opening 7A. A conductive film is formed over the whole surface including the opening 8A and patterned into an upper wiring layer 6. This keeps the organic coating 4 unexposed and thus protects its sides against etching, thereby eliminating the increase in contact resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming multilayer wiring.

[Conventional technology]

In a semiconductor device having multilayer wiring, a nitride film formed by plasma CVD or an oxide film formed by atmospheric pressure CVD is mainly used as an interlayer film. However, as the interconnect spacing in the lower layer becomes narrower due to higher integration, planarization technology becomes necessary to improve the step coverage of the upper layer interconnect.

A common planarization technique is to sandwich a silica film between insulating films such as plasma nitride films, but as the integration density has increased in recent years, even more planarization is required, so etchback methods and Multiple application methods of silica films have been used. However, even if these methods are used, planarization is insufficient, so recently, organic coating films such as silicon polyimide have been used.

[Problem to be solved by the invention]

When using an organic coating film such as silicon polyimide for planarization, conventionally, as shown in FIG. After that, an insulating film 3A such as a plasma nitride film is formed, an organic coating film 4 is formed thereon, an opening 7 for connecting the lower layer wiring and the upper layer wiring is formed, and a second Aρ An upper layer wiring consisting of wiring 6 was formed.

Therefore, when forming the upper layer wiring, the organic coating film 4 was exposed. Generally, when forming an upper layer wiring, RF etching is performed in a vacuum before forming a wiring film by sputtering or the like in order to reduce the connection resistance with the lower layer wiring. At the same time, etching is performed, and the etched material re-deposit on the underlying wiring in the opening, resulting in an increase in connection resistance.

Furthermore, since the organic coating film 4 is easily etched by O2 plasma, there is a problem in that it cannot be treated with O2 plasma in a post-process.

In order to solve these problems, there is a method of further forming a second plasma nitride film or the like on the organic coating film 4. However, in this case, since the opening for connecting the lower layer wiring and the upper layer wiring is formed after forming the nitride film, etc., the second plasma nitride film etc. becomes overhanged due to side etching of the organic coating film, and the upper layer This has the disadvantage of deteriorating the step coverage of wiring. Also in this method, the organic coating film is exposed on the side surface of the opening. Therefore, the organic coating film on the side surface of the opening is etched by RF etching before forming the upper wiring film by sputtering or the like, resulting in an increase in connection resistance.

[Means to solve the problem]

In the method for manufacturing a semiconductor device of the present invention, a first
A step of forming a second insulating film after forming a lower layer wiring through the insulating film, forming an organic coating film on the second insulating film, patterning it, and forming a first insulating film on the lower layer wiring. After forming an opening and forming a third insulating film over the entire surface including the first opening, the third insulating film and the second insulating film are etched to form a third insulating film in the first opening. This method includes a step of forming a second opening, and a step of forming a conductive film over the entire surface including the second opening and then patterning it to form an upper layer wiring.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), a 5i02 film 1 is formed on a semiconductor substrate -F on which regions such as active elements are formed, and then a
After forming the ρ film, patterning is performed to form the first Aρ wiring 2. Subsequently, a first SiN film 3 is formed to a thickness of 200 to 5,000 wafers by plasma CVD or the like. Furthermore, apply organic coating Jlj4 such as silicon polyimide to 10,000 to 15
It is formed to a thickness of 0.000 mm and flattened.

Next, as shown in FIG. 1(b), after forming a mask made of a photoresist film, the organic coating film 4 is etched and the first
An opening 7A is formed. Next, as shown in FIG. 1(c), a second SiN film 5 is formed on the entire surface and then patterned to form a second opening smaller than the first opening as shown in FIG. 1(d). Form 8A. Next, as shown in FIG. 1(e), an Aρ film is formed on the entire surface and then patterned to form the second AA wiring 6.

Here, the first opening 7A is formed by etching the organic coating film 4 by RIE using 02, and the second opening 8A is formed by two-step etching of isotropic etching and anisotropic etching. Immediately before sputtering when forming the second A (wiring 6), RF etching is performed at a pressure of several mTorr to reduce the connection resistance with the first Aρ wiring 2.

In this first embodiment, 5iO is used instead of the SiN film.
An N film or a SiO film may also be used. Also, the AA wiring is Af
It can be easily inferred that -3t wiring or A, &-Cu wiring may also be used. Furthermore, the first AiI wiring 2 and the second AiI
The wiring 6 may be an nth Aρ wiring and an (n+1)th AII wiring (n is an integer), respectively. In this way, according to the first embodiment, the organic coating film 4 is made of Si even in the openings.
Since it is covered with an N film, it is unlikely to be etched during RF etching.

FIGS. 2(a) to 2(c) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

The basic manufacturing method is the same as the first example, but the first
The opening is formed as follows.

As shown in FIG. 2(a, ), after forming the organic coating film 4 of silicone polyimide or the like in the same manner as in the first embodiment, a positive photoresist film 9 of 5000 to 1 OOO0 is applied to form the first opening. form a partial pattern. Next, a boss bake is performed at about 150° C. to create a slope at the edge of the opening. Next, as shown in FIG. 2(b), in this state, isotropic etching is performed using 02 plasma to form a first opening 7B. At this time, due to the inclination of the edge of the opening of the photoresist film 9 due to the boss baking at about 150° C. and the isotropic etching of the 02 plasma, a large inclination is formed at the edge of the first opening 7B.

The organic coating film 4, such as silicon polyimide, and the photoresist I film 9 are etched back because the etching rate in the 02 plasma is almost the same, and the organic coating film 4 is almost completely planarized. As shown in FIG. 2(c), after forming the second SiN film 5, the first opening 7B is opened.
After forming the second opening 8B with a smaller width, the first opening 8B is formed.
An Aρ wiring 6 is formed.

In the embodiment of Section 2, since the opening of the organic coating film 4 is sloped, the step coverage of the second Aρ wiring is greatly improved.

〔Effect of the invention〕

As explained above, in a semiconductor device having a multilayer wiring structure using an organic coating film as an interlayer film, the present invention forms a first opening in the organic coating film, and then forms an insulating film on the entire surface.
Subsequently, a second opening is formed inside the first opening so that the organic coating film is entirely covered with an insulating film, thereby reducing the R before forming the upper layer wiring material by sputtering or the like.
During F etching, it is possible to prevent the organic coating film from being etched and re-adhering to the opening for connection to the underlying wiring as in the conventional case. Therefore, it is possible to prevent an increase in connection resistance between the lower layer wiring and the upper layer wiring.

[Brief explanation of drawings]

1 and 2 are cross-sectional views of a semiconductor chip for explaining first and second embodiments of the present invention, and FIG. 3 is a cross-sectional view of a semiconductor chip for explaining a conventional example. 1...5i02 film, 2...1st Aρ wiring, 3...
・First SiN film, 3A... Insulating film, 4... Organic coating film, 5... Second SiN film, 6... Second Aρ wiring, 7... Opening, 7A , 7B...first opening,
8A, 8B... second opening, 9... photoresist film.

Claims (1)

[Claims] A step of forming a lower wiring layer on the semiconductor substrate via the first insulating film and then forming a second insulating film, and forming an organic coating film on the second insulating film and then patterning the lower layer wiring. After forming a first opening on the wiring and forming a third insulating film on the entire surface including the first opening,
etching the third insulating film and the second insulating film;
forming a second opening within the opening of the second opening;
1. A method of manufacturing a semiconductor device, comprising the steps of: forming a conductive film over the entire surface including the opening, and then patterning the conductive film to form an upper layer wiring.