JP2856489B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In a method of manufacturing a semiconductor device, when an insulating film is formed by a spin coating method, a step of an insulating film generated between a metal ring and a wiring layer and between wiring layers is reduced to make the surface flat. To provide a method for manufacturing a semiconductor device which can be improved and can improve the coverage of the next wiring layer and make it difficult to disconnect the semiconductor device. A surface flattening process is performed while leaving the region, and then a scribe line region of the first insulating film is removed and then a metal ring is formed, or the edge of the first insulating film is formed together with the wiring layer. The metal layer formed in the portion is extended to the scribe line region, the surface is flattened, and then the scribe line region portion of the metal layer is removed to form a metal ring.

[Industrial applications]

The present invention relates to a method of manufacturing a semiconductor device, and can be applied to a method of manufacturing a semiconductor device such as a transistor for forming a multilayer wiring around a chip. The present invention relates to a method for manufacturing a semiconductor device capable of reducing the step of an insulating film generated between a metal ring and a wiring layer and between wiring layers when forming the semiconductor device and flattening the surface.

Recently, a surface flattening insulating film made of, for example, PSG containing P (phosphorus) is particularly provided in a region between a field oxide film formed on a substrate around a chip and a scribe line region serving as a cutting region required for dicing. When formed, a metal ring made of, for example, Al is formed so as to cover the side wall of the insulating film in order to prevent moisture from entering from the side wall of the insulating film and to prevent the insulating film from peeling off from the substrate. For this reason, a large step of the metal ring is generated between the metal ring and the substrate.Therefore, when an insulating film such as SOG is formed by a spin coating method, the large step of the metal ring hinders the flow of SOG. There is a problem that a large level difference is generated in the insulating film between the wiring layers and between the wiring layers, so that the surface cannot be flattened. Then, there is a problem in that the coverage of the next wiring layer is deteriorated due to the step, and the disconnection is easily caused.

Therefore, when forming the insulating film by the spin coating method,
A semiconductor device that can reduce the level difference of the insulating film generated between the metal ring and the wiring layer and between the respective wiring layers to flatten the surface, improve the coverage of the next wiring layer, and reduce the possibility of disconnection. Manufacturing methods are required.

[Conventional technology]

3 (a) to 3 (i) are views for explaining a conventional method for manufacturing a semiconductor device. The wiring in the illustrated example is a case where the wiring is applied to a gate wiring of a MOS transistor.

In this figure, 31 is a substrate made of Si or the like, 32 is a field oxide film made of SiO ₂ or the like, 33a is a scribe line region serving as a cutting region required for dicing, 33b is a portion between the scribe line region 33a and the field oxide film 32. Regions, 34a, 34b, 34c are wiring layers made of poly-Si, etc., 35 is PSG
An insulating film for planarizing the surface, etc., 36 is a contact hole formed on the wiring layer 34a, 37 is an opening formed on the substrate 31 with a part of the scribe line region 33a and a part of the region 33b, 38a, 38b and 38c are wiring layers made of, for example, Al, and 39 is Al
Metal ring made of SOG etc., 40 is an insulating film made of SOG etc., 41
Is an interlayer insulating film made of PSG or the like, and 42a and 42b are wiring layers 38a and 38b.
The contact holes 43 formed on the substrate 31 are openings formed on the substrate 31 in the scribe line region 33a, 44a and 44, respectively.
b is a wiring layer made of Al or the like.

 Next, the manufacturing method will be described.

First, as shown in FIG. 3 (a), LOCOS by Si ₃ N
_{After the} field oxide film 32 is formed by oxidizing the silicon substrate 31 around the chip using the film ₄ as a mask, the substrate 31 is etched by etching the Si ₃ N ₄ film and the SiO ₂ film thereunder by, for example, RIE. Expose. At this time, the substrate 31 in the scribe line region 33a serving as a cutting region necessary for dicing and the substrate 31 in the region 33b between the scribe line region 33a and the field oxide film 32 are exposed. Next, after depositing poly-Si on the entire surface by, for example, a CVD method, the poly-Si is selectively etched by, for example, RIE to form wiring layers 34a, 34b, 34c on the field oxide film 32.

Next, as shown in FIG. 3B, for example, PSG is deposited on the entire surface by a CVD method to form an insulating film 35, and then the insulating film 35 is caused to flow by a heat treatment at about 900 ° C. to planarize the surface. Do.

Next, as shown in FIG. 3C, the insulating film 35 is etched, for example, by RIE in the region on the wiring layer 34a and in the region of the scribe line region 33a and a part of the region 33b on the substrate 31. Thereby, a contact hole 36 is formed on the wiring layer 34a, and the scribe line region 33a is formed.
The opening 37 is formed on the substrate 31 and the part of the region 33b.
At this time, the wiring layer 34a is exposed in the contact hole 36, and the substrate 31 of the scribe line region 33a and a part of the region 33b is exposed in the opening 37.

Next, as shown in FIG. 3D, after depositing Al on the entire surface by, for example, a sputtering method, Al is selectively etched by, for example, RIE to form a wiring on the insulating film 35 corresponding to the field oxide film 32. Forming the layers 38a, 38b, 38c,
A metal ring 39 is formed on the side wall of the insulating film 35 in the opening 37. At this time, the wiring layer 38a is in contact with the wiring layer 34a in the contact hole 36, and the metal ring 39 is formed in a region 33b between the scribe line region 33a and the field oxide film 32. The metal ring 39 made of Al here
Is formed so as to cover the side wall of the insulating film 35. This is to prevent moisture from entering here (the insulating film 35 made of PSG) and to prevent the insulating film 35 from peeling off from the substrate 31. ing.

Next, as shown in FIG. 3 (e), the wiring layer 38a, 38b, 38c, the metal ring 39, and the exposed substrate 31 of the scribe line region 33a and a part of the region 33b are covered by a spin coating method. In this manner, the insulating film 40 is formed by applying SOG and curing by baking. Here, the flow direction of the SOG at the time of application is a case where the flow proceeds from the scribe line area 33a toward the element area as indicated by X in FIG. 3 (e), and the application point is usually the scribe line area at the center of the wafer. 33a or the element region, and the flow direction is from the center of the wafer to the peripheral direction of the wafer.

Next, as shown in FIG. 3F, the insulating film 40 is etched back by, for example, RIE to expose the wiring layers 38a, 38b, 38c and the metal ring 39, and to planarize the surface. At this time,
Further, the substrate of the scribe line area 33a and a part of the area 33b
31 is exposed.

Next, as shown in FIG. 3G, an interlayer insulating film 41 is formed by depositing PSG on the entire surface by, for example, a CVD method.

Next, as shown in FIG. 3 (h), for example, the regions on the wiring layers 38a and 38b and the scribe line region 33 are formed by RIE.
In the region a on the substrate 31, a contact hole 42a, 42b is formed on the wiring layer 38a, 38b by etching the interlayer insulating film 41, and an opening 43 is formed on the substrate 31 in the scribe line region 33a. I do. At this time, the wiring layers 38a and 38b are exposed in the contact holes 42a and 42b, and the substrate 31 of the scribe line region 33a is exposed in the opening 43.

Then, after depositing Al on the entire surface by, for example, a sputtering method, Al is selectively etched to form contact with the wiring layers 38a, 38b in the contact holes 42a, 42b by, for example, RIE to form wiring layers 44a, 44b. By doing so, a wiring structure as shown in FIG. 3 (i) can be obtained.

[Problems to be solved by the invention]

The above-described conventional method for manufacturing a semiconductor device employs a metal to prevent moisture from entering from a side wall of an insulating film 35 made of PSG into a region 33b between a field oxide film 32 formed on a substrate 31 around a chip and a scribe line region 33a. Since the ring 39 is formed so as to cover the side wall, the metal ring 39 and the substrate
A large step is generated between 31 as shown by D1 in FIG. For this reason, the insulating film 40 made of SOG is formed by spin coating.
Since the large step D1 of the metal ring 39 obstructs the flow of SOG when forming the metal ring 39, as shown in FIG. 4, between the metal ring 39 and the wiring layer 38c, between the wiring layer 38c and the wiring layer 38b, and between the wiring layer 38b and There is a problem that the steps are large in the insulating film 40 between the wiring layers 38a, such as D2, D3, and D4, and the surface cannot be flattened. Then, if there is such a step, a step is formed even if etch back is performed in the next step, and there is a problem that the coverage of the next wiring layers 44a and 44b is deteriorated due to the step and the disconnection is easily caused. Note that the step on the surface of the insulating film 40 tends to be more conspicuous as the spin coating is performed thinner.

In view of the above, according to the present invention, when forming an insulating film by a spin coating method, it is possible to reduce the level difference of the insulating film generated between the metal ring and the wiring layer and between the respective wiring layers and to planarize the surface, and to form the next wiring layer. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can improve the coverage of the semiconductor device and make it difficult to disconnect.

[Means for solving the problem]

In order to achieve the above object, a method of manufacturing a semiconductor device according to a first aspect of the present invention includes a step of forming a first insulating film over the entire surface of a substrate and a step of forming a wiring layer in a chip region on the first insulating film. Forming a second insulating film on the entire surface of the substrate by a spin coating method so as to cover the wiring layer; and etching back the second insulating film to form a region excluding the wiring layer and the chip region. A step of exposing the first insulating film, a step of forming a third insulating film over the entire surface including the exposed first insulating film, and a scribe line of the third and first insulating films Etching a portion including the region to form an opening on the substrate; and forming a metal ring in the side wall of the third and first insulating films in the opening.

In order to achieve the above object, a method of manufacturing a semiconductor device according to a second aspect of the present invention includes the steps of: forming a first insulating film on a substrate, the opening including a scribe line region; Forming a wiring layer in a chip region on the first insulating film and forming a metal layer extending from the side wall of the first insulating film in the opening to the scribe line region; Forming a second insulating film so as to cover the wiring layer and the metal layer by etching, exposing the wiring layer and the metal layer by etching back the second insulating film, Forming a metal ring in the side wall of the first insulating film in the opening by etching a portion of the layer including the scribe line region; and a chip region including the first wiring layer and the top of the metal ring. Third insulation It is intended to include a step of forming a.

[Action]

In the first invention, as shown in FIGS. 1 (a) to 1 (i),
As the field oxide film 2 is formed on the substrate 1 in the chip region, the scribe line region 3a and the substrate 1 in the region 3b between the scribe line region 3a and the field oxide film 2 are exposed, and the field oxide film 2 An insulating film 5 for flattening the surface is formed so as to cover the scribe line region 3a and the substrate 1 in the region 3b, and wiring layers 7a, 7b, 7c are formed on the insulating film 5 corresponding to the field oxide film 2. After
An insulating film 8 is formed by a spin coating method so as to cover the wiring layers 7a, 7b, 7c and the insulating film 5 formed on the substrate 1 in the scribe line regions 3a and 3b, and the insulating film 8 is etched back. As a result, the wiring layers 7a, 7b, 7c and the insulating films 5 in the scribe line regions 3a and 3b are exposed,
An insulating film 9 is formed so as to cover the first wiring layers 7a, 7b, 7c, the scribe line region 3a, and the second insulating film 5 in the region 3b, a region on the wiring layers 7a, 7b, and a scribe line region. The insulating films 9 and 5 are etched in a region on the substrate 1 between the first wiring layer 3a and a part of the region 3b to form a first wiring layer.
After contact holes 10a and 10b are formed on 7a and 7b and opening 11 is formed on substrate 1 with scribe line region 3a and a part of region 3b, contact holes 10a and 10b are formed.
a, so as to make contact with the wiring layers 7a, 7b in the
The wiring layers 12a and 12b are formed, and the metal ring 13 is formed on the insulating film 9 in the opening 11 and on the side wall.

In the second invention, as shown in FIGS. 2 (a) to (k), a field oxide film 2 is formed on a substrate 1 in a chip region portion, and a scribe line region 3a and a scribe line region 3a are formed. An insulating film 5 for flattening the surface is formed so that the substrate 1 in the region 3b between the field oxide films 2 is exposed and the field oxide film 2 and the scribe line regions 3a and the substrate 1 in the region 3b are covered. The opening 21 is formed by etching the insulating film 5 in a region on the substrate 1 of the line region 3a and a part of the region 3b,
A wiring layer 7a on the insulating film 5 corresponding to the field oxide film 2;
7b and 7c are formed, and after the metal layer 22 is formed on the substrate 1 from the side wall of the insulating film 5 in the opening 21, the wiring layers 7a, 7b, 7c and the metal layer 22 are covered by a spin coating method. An insulating film 8 is formed as shown in FIG. Then, the wiring layers 7a, 7b, 7c and the metal layer 22 are exposed by etching back the insulating film 8, and the metal layer 22 is formed in the scribe line region 3a and a part of the region 3b on the substrate 1. The metal ring 13 is formed on the side wall of the second insulating film 5 in the opening 21 by the etch back, and the wiring layers 7a, 7b, 7c, the metal layer 22, and the scribe line regions 3a and a part of the region 3b are formed. The insulating film 9 is formed so as to cover the substrate 1 with the wiring layer 7a and 7b, and the insulating film 9 is etched in the region on the substrate 1 in the scribe line region 3a and the scribe line region 3a.
a and 7b are formed on the substrate 1 in the scribe line region 3a, and an opening 14 is formed on the substrate 1. Then, the wiring layer 7 in the contact holes 10a and 10b is formed.
Wiring layers 12a and 12b are formed so as to make contact with a and 7b.

Therefore, according to the first and second aspects of the present invention, when forming the insulating film by the spin coating method, it is possible to reduce the steps of the insulating film generated between the metal ring and the wiring layer and between the wiring layers and to flatten the surface. As a result, the coverage of the next wiring layer can be improved and the disconnection can be made difficult. Details will be described in Examples.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

1 (a) to 1 (i) are diagrams for explaining one embodiment of a method for manufacturing a semiconductor device according to the first invention. The wiring in the illustrated example is a case where the wiring is applied to a gate wiring of a MOS transistor.

In this figure, 1 is a substrate made of Si or the like, 2 is a field oxide film, 3a is a scribe line region serving as a cutting region required for dicing, 3b is a region between the scribe line region 3a and the field oxide film 2, 4a, 4b , 4c is poly
Wiring layer made of Si or the like, 5 is an insulating film for flattening the surface made of BPSG or the like, 6 is a contact hole formed on wiring layer 4a, 7a, 7b, 7c is a wiring layer made of Al or the like, 8 is SOG 9 is an insulating film made of PSG or the like, 10a is a wiring layer 7a
A contact hole formed on the wiring layer 7b, a contact hole formed on the wiring layer 7b, an opening 11 formed on the substrate 1 with a part of the scribe line region 3a and a part of the region 3b,
12a and 12b are wiring layers made of Al or the like, 13 is a metal ring made of Al or the like, and 14 is an opening formed on the substrate 1 in the scribe line region 3a.

 Next, the manufacturing method will be described.

First, as shown in FIG. 1 (a), Si ₃ N
₄ film after forming a field oxide film 2 film thickness of, for example, 6000Å of by oxidizing the silicon substrate 1 of the chip peripheral portion as a mask, for example, etching the the Si ₃ N ₄ film and the SiO ₂ film thereunder by RIE By doing so, the substrate 1 is exposed. At this time, the substrate 1 in the scribe line region 3a serving as a cutting region necessary for dicing and the substrate 31 in the region 33b between the scribe line region 3a and the field oxide film 2 are exposed. Next, the field oxide film 2 and the scribe line regions 3a and 3b are formed by, for example, a CVD method.
After poly-Si is deposited so as to cover the substrate 1 of
The polysilicon is selectively etched by E to form wiring layers 4a, 4b and 4c on the field oxide film 2.

Next, as shown in FIG. 1B, wiring layers 4a, 4b, 4c formed on the field oxide film 2 by, for example, the CVD method.
Then, BPSG is deposited so as to cover the substrate 1 in the scribe line region 3a and the region 3b to form an insulating film 5 having a thickness of, for example, 4000.degree. To make the surface flat.

Next, as shown in FIG. 1 (c), a contact hole 6 is formed on the wiring layer 4a by etching the insulating film 5 in a region on the wiring layer 4a by, for example, RIE. At this time, the wiring layer 4a is exposed in the contact hole 6.

Next, as shown in FIG. 1 (d), after depositing Al on the entire surface by, for example, a sputtering method, the Al is selectively etched by, for example, RIE to form a wiring on the insulating film 5 corresponding to the field oxide film 2. The layers 7a, 7b, 7c are formed. At this time, the wiring layer 7a is in contact with the wiring layer 4a in the contact hole 6.

Next, as shown in FIG. 1 (e), wiring layers 7a, 7b, 7c, scribe line area 3a and area
33b so as to cover the insulating film 5 formed on the substrate 1 of 33b.
Is applied and cured by baking to form an insulating film 8. Here, the flow direction at the time of application of SOG is a case where it flows from the scribe line region 3a toward the element region as indicated by Y in FIG. 1 (e).

Next, as shown in FIG. 1 (f), the insulating film 8 is etched back by, eg, RIE to expose the wiring layers 7a, 7b, 7c and the insulating films 5 in the scribe line regions 3a and 3b. Perform surface flattening.

Next, as shown in FIG. 1 (g), PSG is deposited by, for example, a CVD method so as to cover the wiring layers 7a, 7b, 7c and the insulating films 5 in the scribe line regions 3a and 3b. Forms an insulating film 9 of, for example, 3000 °.

Next, as shown in FIG. 1 (h), the insulating films 9 and 5 are formed in the regions on the wiring layers 7a and 7b and the scribe line regions 3a and a part of the region 3b on the substrate 1 by RIE, for example.
Is etched to form contact holes 10a and 10b on the wiring layers 7a and 7b, and an opening 11 is formed on the substrate 1 in the scribe line region 3a and a part of the region 3b.

Then, after depositing Al on the entire surface by, for example, a sputtering method, the Al is selectively etched by, for example, RIE, and the wiring layers 12a, 12b are brought into contact with the wiring layers 7a, 7b in the contact holes 10a, 10b. The wiring structure as shown in FIG. 1 (i) can be obtained by forming the insulating film 9 in the opening 11 and forming the metal ring 13 on the side wall of the opening 11. At this time, an opening 14 is formed on the substrate 1 in the scribe line region 3a, and the substrate 1 in the scribe line region 3a is exposed in the opening 14.

That is, in the above embodiment, as shown in FIGS. 1 (d) and 1 (e), the SO film is formed by the spin coating method in a state where the insulating film 5 is formed on a part of the substrate 1 in the scribe line regions 3a and 3b.
An insulating film 8 made of G is formed. For this reason, when the insulating film 8 made of SOG is formed by the spin coating method, a large step due to a metal ring as in the related art can be eliminated in the region 3b between the scribe line region 3a and the field oxide film 2. Of the insulating film 8 generated between the wiring layers 7a, 7b, 7c can be reduced, and the surface can be flattened. For this reason, the next wiring layers 12a, 1a
It is possible to improve the coverage of 2b and make it difficult to disconnect. Here, the metal ring 13 is formed when the wiring layers 12a and 12b are formed.

By the way, in the present invention, the scribe line area
The same effect as in the above embodiment can be obtained by forming the insulating film 8 made of SOG by the spin coating method in a state where the metal layer is formed on the substrate 1 where the portion 3a and a part of the region 3b are exposed. it can. Hereinafter, a specific description will be given with reference to the drawings.

2 (a) to 2 (k) are diagrams for explaining one embodiment of a method for manufacturing a semiconductor device according to the second invention. The wiring in the illustrated example is a case where the wiring is applied to a gate wiring of a MOS transistor.

In this figure, the same reference numerals as in FIG. 1 denote the same or corresponding parts, 21 denotes an opening formed on the substrate 1 in a part of the scribe line area 3a and a part of the area 3b, and 2 denotes a metal layer made of Al or the like. And 23 are resist films.

 Next, the manufacturing method will be described.

First, as shown in FIG. 2 (a), Si ₃ N
₄ film after forming a field oxide film 2 film thickness of, for example, 6000Å of by oxidizing the silicon substrate 1 of the chip peripheral portion as a mask, for example, etching the the Si ₃ N ₄ film and the SiO ₂ film thereunder by RIE By doing so, the substrate 1 is exposed. At this time, the scribe line region 3a serving as a cutting region required for dicing and the substrate 1 in the region 33b between the scribe line region 3a and the field oxide film 2 are exposed. Next, the field oxide film 2 and the substrate 1 in the scribe line regions 3a and 3b are formed by, for example, a CVD method.
Then, the polysilicon is selectively etched by, eg, RIE to form wiring layers 4a, 4b, 4c on the field oxide film 2.

Next, as shown in FIG. 2B, the wiring layers 4a, 4b, 4c formed on the field oxide film 2 by, for example, the CVD method.
Then, BPSG is deposited so as to cover the substrate 1 in the scribe line region 3a and the region 3b to form an insulating film 5 having a thickness of, for example, 4000.degree. To make the surface flat.

Next, as shown in FIG. 2C, a region on the wiring layer 4a and a scribe line region 3a are formed by RIE, for example.
The contact hole 6 is formed on the wiring layer 4a by etching the insulating film 5 in a region on the substrate 1 with a part of the scribe line region 3b, and an opening is formed on the substrate 1 with the scribe line region 3a and a part of the region 3b. The part 21 is formed. At this time, the wiring layer 4a is exposed in the contact hole 6, and the substrate 1 of the scribe line region 3a and a part of the region 3b is exposed in the opening 21.

Next, as shown in FIG. 2 (d), after depositing Al on the entire surface by, for example, a sputtering method, Al is selectively etched by, for example, R1E to form a wiring on the insulating film 5 corresponding to the field oxide film 2. The layers 7a, 7b and 7c are formed, and the metal layer 22 is formed on the substrate 1 from the side wall of the insulating film 5 in the opening 21. At this time, the wiring layer 7a is in contact with the wiring layer 4a in the contact hole 6.

Next, as shown in FIG. 2 (e), SOG is applied and cured by baking so as to cover the wiring layers 7a, 7b, 7c and the metal layer 22 by a spin coating method to form an insulating film 8.
Here, the flow direction of the application of SOG is a case where the flow is from the scribe line region 3a toward the element region as shown by Z in FIG. 2 (e).

Next, as shown in FIG. 2 (f), the insulating film 8 is etched back by, for example, RIE to expose the wiring layers 7a, 7b, 7c and the metal layer 22, thereby planarizing the surface.

Next, as shown in FIG. 2 (g), after a resist is applied to the entire surface to form a resist film 23, exposure and development are performed to expose the scribe line region 3a and a part of the region 3b on the metal layer 22. The resist film 23 is patterned in the region.

Next, as shown in FIG. 2 (h), the metal layer 22 is etched in the region of the scribe line region 3a and a part of the region 3b on the substrate 1 by, for example, RIE using the resist film 23 as a mask. The metal ring 13 is formed on the side wall of the insulating film 5 in the portion 21. At this time, the substrate 1 in the scribe line area 3a and a part of the area 3b is exposed. Then
The resist film 23 is removed.

Next, as shown in FIG. 2 (i), the PSG is applied to cover the wiring layer 7a, 7b, 7c, the metal layer 22, and the substrate 1 of the scribe line region 3a and a part of the region 3b by, for example, a CVD method. Is deposited to form an insulating film 9 having a thickness of, for example, 3000 °.

Next, as shown in FIG. 2 (j), the insulating film 9 is etched in the region on the wiring layers 7a and 7b and the region of the scribe line region 3a on the substrate 1 by RIE, for example. Contact holes 10a and 10b are formed on 7b, and an opening 14 is formed on substrate 1 in scribe line region 3a.

Then, after depositing Al on the entire surface by, for example, a sputtering method, the Al is selectively etched by, for example, RIE to form the wiring layers 12a, 12b so as to make contact with the wiring layers 7a, 7b in the contact holes 10a, 10b. By doing, the second
A wiring layer structure as shown in FIG.
At this time, the substrate 1 in the scribe line area 3a is
Is exposed.

That is, in the above-described embodiment, as shown in FIGS. Tier 22
Is formed, an insulating film 8 made of SOG is formed by a spin coating method. For this reason, when the insulating film 8 made of SOG is formed by the spin coating method, the area between the scribe line area 3a and the field oxide film 2 in the area 3b is smaller than that of the conventional step formed by the metal ring in FIG. Since the thickness can be reduced by the thickness of the metal layer 22 as shown by a step E, the insulating film 8 formed between the metal layer 22 serving as a metal ring and the wiring layer 7c and between the respective wiring layers 7a, 7b, 7c is formed. The step can be reduced and the surface can be flattened. For this reason, it is possible to improve the coverage of the next wiring layers 12a and 12b and make it difficult to disconnect. Here, the metal ring 13 is formed by etching the metal layer 22.

〔The invention's effect〕

According to the present invention, when forming an insulating film by a spin coating method, it is possible to reduce the steps of the insulating film generated between the metal ring and the wiring layer and between the respective wiring layers and to planarize the surface, and to form the wiring of the next layer. There is an effect that the coverage of the layer can be improved and the disconnection can be made difficult.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the first invention, and FIG. 2 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the second invention. FIG. 3 is a diagram for explaining a conventional manufacturing method, and FIG. 4 is a diagram for explaining a problem of the conventional example. 1 ... substrate, 2 ... field oxide film, 3a ... scribe line area, 3b ... area, 4a, 4b, 4c ... wiring layer, 5
…… Insulating film, 6… Contact hole, 7a, 7b, 7c ……
Wiring layer, 8 insulating film, 9 insulating film, 10a, 10b contact hole, 11 opening, 12a, 12b wiring layer,
13 ... metal ring, 14 ... opening, 21 ... opening, 22 ...
... metal layer.

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205-21/3213 H01L 21/768 H01L 21/78

Claims (2)

(57) [Claims] A step of forming a first insulating film on the entire surface of the substrate, and a step of forming a wiring layer on a chip region on the first insulating film.
forming the wiring layers (7a, 7b, 7c) on the entire surface of the substrate (1) by spin coating.
Forming a second insulating film (8) so as to cover 7c); and etching back the second insulating film (8) to form the wiring layer (7a, 7b, 7c) and the chip region. Excluded area (3a,
3b) exposing the first insulating film (5), and forming a third insulating film (9) on the entire surface including the exposed first insulating film (5); Etching a portion of the third and first insulating films (9, 5) including the scribe line region (3a) to form an opening (11) on the substrate (1); 11) forming a metal ring (13) on the side walls of the third and first insulating films (9, 5) in (11). 2. A step of forming a first insulating film (5) on a substrate (1), wherein an opening (21) is provided in a region including a scribe line region (3a) and covers a chip region. Wiring layers (7a, 7a) are formed in the chip region on the first insulating film (5).
forming a metal layer (22) extending from a side wall of the first insulating film (5) in the opening (21) to the scribe line region (3a); Forming a second insulating film (8) so as to cover the wiring layers (7a, 7b, 7c) and the metal layer (22) by a spin coating method; and forming the second insulating film (8). A step of exposing the wiring layers (7a, 7b, 7c) and the metal layer (22) by etching back; and etching a portion of the metal layer (22) including the scribe line region (3a). Forming a metal ring (13) on the side wall of the first insulating film (5) in the opening (21); and forming the first wiring layer (7a, 7b, 7c) and the metal ring (13). )
Forming a third insulating film (9) in a chip region including the upper portion.