JPH08236608A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To realize finer patterning and higher integration by reducing the dimensional conversion error after patterning at the time of isolation. CONSTITUTION: An insulation film 2, polysilicon and silicon oxide are deposited sequentially on a silicon substrate 1. Resist is then formed thereon by photolithography and the silicon oxide is patterned by wet etching using the resist as a mask thus forming an insulation film 6 overlying the field shield gate. The resist is removed by ashing. Subsequently, the polysilicon is subjected to dry etching using the insulation film 6 as a mask thus forming a field shield gate electrode 7. Finally, the side wall part of the field shield gate electrode 7 is subjected to thermal oxidation thus depositing silicon oxide 8 on the exposed part thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which elements are separated by a field shield technique.

[0002]

2. Description of the Related Art In a semiconductor device, a LOCOS (Local Oxidation of Silicon) method is widely used as a method of electrically isolating elements formed on a silicon substrate (element isolation) from each other. However, in the LOCOS method, a dimensional conversion difference due to so-called bird's beaks that occurs when forming the element isolation region becomes an obstacle to miniaturization and high integration of the integrated circuit. As a method for solving such a problem, a field-shield element isolation technique has been proposed. This is a technique of forming a shield electrode in the element isolation region and fixing the potential of the shield electrode to cut off the potential of the parasitic MOS transistor in the element isolation region. Regarding such technology, for example, “FULLY PLANARIZED 0.5 μm TECHNOLOGIES
FOR 16M DRAM (IEDM Tech. Dig. P246 (1988)) ”.

5 to 8 are schematic sectional views showing a part of a method of manufacturing a semiconductor device based on the field shield technique. This method is performed by the following procedure. First, as shown in FIG. 5, a silicon oxide film 102, a polycrystalline silicon film 103, and a silicon oxide film 104 are sequentially deposited on a silicon substrate 101, and then photolithography is performed to form a resist 201. Here, the width dimension of the resist 201 is b. Next, FIG.
As shown in FIG.
4 and the polycrystalline silicon film 103 are patterned, and the resist 201 is removed.

Next, an oxide film is deposited on the entire surface, and then etched back to the height of the silicon oxide film 104. As a result, the sidewall insulating film 105 is formed on the sidewalls of the polycrystalline silicon film 103 and the silicon oxide film 104, as shown in FIG. Here, the width of the sidewall insulating film 105 is a and the width of the element isolation region is c. As can be seen from FIG. 7, the gate insulating film 102, the polycrystalline silicon film 103, and the silicon oxide film 104 are respectively the gate insulating film of the field shield, the gate electrode,
It becomes the gate upper insulating film.

Further, the gate insulating film 106 and the gate electrode 1
07, the gate upper insulating film 108 is sequentially formed, then the sidewall insulating films 109 are formed on both side surfaces thereof, and the impurity diffusion region 110 is further formed. Finally, source / drain polycrystalline silicon 111 to be a metal wiring layer is deposited to complete a MOS transistor as shown in FIG.
Since a bird's beak unlike the case of manufacturing by the LOCOS method does not occur in a semiconductor device manufactured using the above method,
As a result, the size conversion difference is reduced.

[0006]

However, even when the field shield technique is used, since the side wall insulating film 105 is formed on the inner side wall of the field shield as shown in FIG. Due to the height a, the dimension conversion difference c-b after patterning does not become zero, which has been a problem in achieving miniaturization and high integration of the semiconductor device.

The present invention has been made in view of the above circumstances, and it is possible to further reduce the dimension conversion difference after patterning at the time of element isolation, thereby achieving miniaturization and higher integration than ever before. It is an object of the present invention to provide a method for manufacturing a semiconductor device.

[0008]

In order to solve the above problems, the present invention provides a step of depositing a first insulating film, a polycrystalline silicon film, and a silicon oxide film in this order on a semiconductor substrate, and the silicon oxide film. Patterning the film to form a gate upper insulating film of the field shield; patterning the polycrystalline silicon film using the gate upper insulating film as a mask to form a field shield gate electrode; And a step of thermally oxidizing the exposed side wall portion to form a second insulating film.

[0009]

According to the present invention, the gate electrode of the field shield is formed by the above structure, and the side wall of the gate electrode is thermally oxidized to form the second insulating film, which is used as a MOS transistor formed in the active region. Therefore, it is not necessary to separately form a side wall insulating film on the side wall of the gate electrode of the field shield, unlike the conventional case. Therefore, the dimensional conversion difference can be reduced as compared with the conventional field shield technology.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 4 are schematic cross-sectional views sequentially showing a part of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1, a silicon substrate 1
An insulating film 2, a polycrystalline silicon film 3, and a silicon oxide film 4 are sequentially deposited on the top. Here, the insulating film 2 is a composite film of a silicon nitride film and a silicon oxide film. Next, as shown in FIG. 2, a resist 5 is formed and the oxide film 4 is formed by a photolithography method using the resist 5 as a mask.
Is patterned to form the gate upper insulating film 6 of the field shield. At this time, the cross section of the gate upper insulating film 6 is tapered due to the influence of the resist 5 so that the width thereof becomes wider toward the lower part. Here, the central portion of the figure is the active region 20, and the portions on both sides thereof are the element isolation regions 21.

After that, the resist 5 is removed by ashing (ashing). Next, using the gate upper insulating film 6 of the field shield as a mask, the polycrystalline silicon film 3
Dry etching is performed on the
The gate electrode 7 of the field shield is formed.

Thereafter, thermal oxidation is performed in order to insulate the side wall of the gate electrode 7 of the field shield. By this oxidation, a silicon oxide film 8 is formed on the exposed portion of the side wall of the gate electrode 7, as shown in FIG. The formation of element isolation is completed through the above steps.

Thereafter, in the active region 20, a gate insulating film, a gate electrode, a gate upper insulating film and the like (not shown) are sequentially formed to manufacture a MOS transistor. In this embodiment, the side wall of the gate electrode 7 is formed. Since the silicon oxide film 8 is formed on the substrate, it is not necessary to form the sidewall insulating film 109 as described in the conventional technique of FIG. Therefore, it is possible to suppress the dimensional conversion difference after patterning,
It becomes possible to narrow the element isolation width. Therefore, the ratio of the active region to the entire surface of the wafer can be increased, and the semiconductor device can be miniaturized and highly integrated.

By adjusting the time when the gate upper insulating film 6 of the field shield is wet-etched, the width d of the gate upper insulating film 6 can be made smaller than the exposure limit of photolithography. Accordingly, further miniaturization and higher integration can be achieved accordingly.

[0016]

As described above, according to the present invention,
When performing element isolation with field shield technology,
Since the side wall portion of the field shield gate electrode is oxidized to be insulated and used as an insulating film, it is not necessary to separately form a side wall for insulation on the side wall portion of the field shield gate electrode, unlike the conventional case. Therefore, the dimensional conversion difference due to the thickness of the sidewall is reduced. Further, by adjusting the time when the gate upper insulating film of the field shield is wet-etched, the width of the gate upper insulating film can be made smaller than the exposure limit of photolithography. Therefore, it is possible to provide a method of manufacturing a semiconductor device, which enables further miniaturization and higher integration of the semiconductor device manufactured on the wafer.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view for explaining the manufacturing process of the embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view for explaining a manufacturing process of a conventional technique.

FIG. 6 is a schematic cross-sectional view for explaining the manufacturing process of the conventional technique.

FIG. 7 is a schematic cross-sectional view for explaining the manufacturing process of the conventional technique.

FIG. 8 is a schematic cross-sectional view for explaining the manufacturing process of the conventional technique.

[Explanation of symbols]

 1, 101 Silicon substrate 2, 102 Insulating film 3, 103 Polycrystalline silicon film 4, 104 Silicon oxide film 5 Resist 6 Field shield gate upper insulating film 7 Field shield gate electrode 8 Side wall silicon oxide film 20, 120 Active Regions 21 and 121 Element isolation regions 105 and 109 Side walls 106 Gate insulating film 107 Gate electrode 108 Gate upper insulating film 110 Impurity diffusion layer 111 Source / drain polycrystalline silicon

Claims (1)

[Claims] 1. A step of sequentially depositing an insulating film, a polycrystalline silicon film, and a silicon oxide film on a semiconductor substrate; a step of patterning the silicon oxide film to form a gate upper insulating film of a field shield; Patterning the polycrystalline silicon film using the upper insulating film as a mask to form a gate electrode of a field shield; and a step of thermally oxidizing an exposed sidewall portion of the gate electrode to form a second insulating film, A method of manufacturing a semiconductor device, comprising: