JPH06291178A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form isolation areas by a simple process and improve the integration and yield of a semiconductor device by simultaneously forming a deep trench and a shallow trench by etching process and filling the trenches by deposition process at the same time. CONSTITUTION:An insulating film 13 is formed on the surface of a semiconductor base 10, a plurality of openings with different widths are formed on the insulating film and a plurality of grooves 18 and 19, which have different depths in response to each width of the opening, are formed by etching the semiconductor base 10. Then, dielectric 15 is embedded in the grooves and an insulating isolation areas are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an element isolation region.

[0002]

2. Description of the Related Art When forming a plurality of semiconductor elements on a single semiconductor chip, it is necessary to insulate each element forming region from each other. Element isolation in a semiconductor integrated circuit is roughly classified into a junction isolation by a PN junction and a dielectric isolation (dielectric isolation) with an insulator interposed.
There are S method and isolation using a trench. With the high integration of semiconductor devices, dielectric isolation has come to be used more often. Until now, LOCOS has been used to selectively oxidize a part of the semiconductor surface to form an isolation region.
However, the LOCOS method has a drawback that bird's beaks are generated at the edge of the isolation region and deep element isolation cannot be formed, which limits the miniaturization and speeding up of elements. Therefore, in order to solve these problems, attention has recently been paid to trench isolation.

FIG. 13 shows a sectional view of a bipolar transistor using trench isolation. The illustrated bipolar transistor is usually manufactured by the following steps. That is, after the N ⁺ buried layer 11 is formed on the P-type substrate 10, the N ⁻ epitaxial layer 12 is formed. After that, a deep trench isolation 22 reaching the P-type substrate is formed around the collector. Then, an N ⁺ impurity layer 38 for reducing the collector resistance is formed. After that, a selective oxidation region is formed by the LOCOS method to separate the base and the collector, and the base 26 and the emitter layer 36 are further formed to form a bipolar transistor. The transistor in FIG. 13 can be miniaturized because the distance between adjacent transistors can be shortened by providing trench isolation in a region around the collector, which is isolated from other devices. Further, by providing the trench isolation deeper than the N ⁺ buried layer, the generation of parasitic elements can be suppressed and the speed of the transistor can be increased.

In a bipolar transistor, in order to shorten the separation distance from adjacent elements and suppress the generation of parasitic elements, deep isolation reaching the P-type substrate and shallow isolation isolating the base and collector and having a continuous epitaxial layer. Ration is necessary.

However, in the above-mentioned conventional example, the element isolation between the base and the collector is performed by the LOCOS isolation method.
It is done in 1. Therefore, the separation width between the collector and the base is limited to about 1.5 to 2.0 μm because of the above-described bird's beak generated by the LOCOS separation method.
Limiting miniaturization of a single element. Further, the LOCOS separation method has a defect that crystal defects are generated under the bird's beak.

In order to solve the above drawbacks associated with the combined use of the trench isolation and the LOCOS method, for example, US Pat. Nos. 4,236,294, 3,745,6.
47, 3,975,818 and 3,978,51
As shown in No. 5 and the like, a method of forming an element isolation region of an NPN transistor with a trench and forming a new sub-trench region between a base and a collector has been proposed.

FIG. 14 shows an example thereof. P ^-
Substrate 10 an N ⁺ buried layer 11, N epitaxial layer 12 and the thermal oxide film layer 13 are sequentially formed, as shown in FIG. 14 (a), for the separation between the base and the collector, the N ⁺ buried layer The shallow sub-trench 18 that reaches is formed by etching. Next, the sub-trench 18 is filled with CVD SiO ₂ 24, and as shown in FIG. 14B, a deep trench 19 reaching the P ⁻ substrate 10 for element isolation is formed by etching. Then, as shown in FIG.
A P layer 26 serving as a base region and N ⁺ layers 36 and 38 serving as an emitter region and a collector region, respectively, are formed, and further, their surfaces are covered with CVDSiO ₂ 24 and at the same time the trench 19 is buried. Finally, as shown in FIG. 14D, an electrode 39 is formed on each of the base, the emitter and the collector to produce an NPN transistor having a shallow trench isolation region 20 and a deep trench isolation region 22.

However, in the above-described conventional example, patterning and etching must be performed twice to form the trench, which has the following drawbacks.

(1) Two masks are required for patterning and etching the same trench, which increases the manufacturing cost.

(2) Since patterning is performed twice,
Due to misalignment, collector / base capacitance C _bc
But it fluctuates.

(3) After forming the trench for element isolation and the sub-trench, a step of burying the trench is required respectively, which increases the manufacturing cost.

Further, the trench isolation may have the following problems. That is, there is a problem of a depression that occurs in the insulating film on the upper surface of the trench isolation and a "dot" that occurs in a narrow trench.

FIG. 15 shows a trench for isolation between devices.
An example of the isolation 22 will be shown. An insulating film (thermal oxide film) 2 is formed on the inner surface of the trench and the surface of the N epitaxial layer 12.
1 is formed and the dielectric 24 is buried in the trench, the dielectric other than the part buried in the trench is removed by an etch back method or the like, and then an insulating film 25 is further deposited to form the element isolation region. It was formed. At this time, due to the step of the dielectric 24 embedded in the trench 22, a recess 27 is formed on the insulating film 25.

The recess 27 causes a sharp step, which causes a reduction in the yield of the semiconductor device especially when forming a multi-layer wiring.

Further, as shown in FIG. 16, a thermal oxide film 2 is formed on the dielectric 24 buried in the trench by a thermal oxidation method.
Even if 9 is formed, the step remains, and the yield is reduced when forming the wiring.

Further, in order to flatten the above-mentioned concave portion, a technique of applying an organic insulating material such as SOG or depositing a buried dielectric very thickly is used. There is a drawback that the method of forming the regions becomes very complicated.

In addition, there is a problem of generation of "sun" in the trench isolation having a narrow width.

FIG. 17A shows that the inner surface of the shallow trench 18 and the deep trench 19 shown in FIG. 14 has a thickness of about 100.
A thermal oxide film 21 of 0 Å is formed, and the polysilicon 33 is further deposited by a low pressure CVD method to about 10,000 to 15,000.
It shows the state that 0 Å is deposited and the trench is filled.

After that, the polysilicon 33 other than the buried portion is etched by reactive ion etching, the base region 26, the emitter region 36, and the collector region 38 are formed by an ordinary method, and the oxide film 37 is provided. Figure 1
A bipolar transistor using the element isolation by the trench as shown in FIG. 7B is obtained.

[0020]

However, in the above-mentioned conventional example, when a shallow trench having a narrow width as shown in FIG. 16 is to be filled with a polysilicon film formed by the usual low pressure CVD, " In many cases, the reliability of the finished semiconductor device is reduced.

Further, in the P-N junction isolation, a parasitic element (P-N) between the P-type isolation region (base of the NPN transistor or emitter / collector of the PNP transistor) and P-type isolation region in the N-type epitaxial layer. -P-transistor) may operate, so a sufficient space is required at the time of pattern design. This is a major obstacle to miniaturization of semiconductor devices.

In the trench isolation, there is a step of embedding an oxide film or polycrystalline Si in the trench in the isolation region, but it is difficult to control the sectional shape of the trench.
Since the inside of the trench may not be uniformly filled and a cavity may remain, a warp may occur when the wafer is stressed in another process.

The present invention has been made in view of the above-mentioned technical problems, and an object thereof is to more easily form an element isolation region that can cope with high integration and improve the yield.

Further, an object of the present invention is to form a deep trench and a shallow trench at the same time in one etching process.
It is an object of the present invention to provide a method capable of simultaneously filling those trenches in a single deposition process.

Still another object of the present invention is to provide a method for forming a flat surface of a trench isolation region.

Still another object of the present invention is to provide a method of completely filling the trench isolation region and preventing generation of "su".

Still another object of the present invention is to provide a trench isolation method in which stress is not generated in the trench isolation region.

[0028]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film on the surface of a semiconductor substrate, and a plurality of openings having different widths in the insulating film. A step of forming a plurality of grooves having different depths according to the width of the opening by etching the semiconductor substrate, and filling the plurality of grooves with a dielectric to form an insulating isolation region. It is characterized by having a step of

Furthermore, the method according to the invention comprises the step of introducing into the first region of the surface of the semiconductor substrate a substance which forms a compound with said semiconductor substrate, said first region and a second region other than said first region. Exposing the surface of the semiconductor substrate in the region and covering the surface of the other substrate with a mask material; etching the semiconductor substrate to form a shallow groove in the first region and a deep groove in the second region; It is characterized by including a step of burying a dielectric material in the shallow groove and the deep groove to form an insulating isolation region.

The method according to the present invention comprises the steps of providing an opening in an insulating film formed on the surface of a semiconductor substrate, forming an insulating film in the opening, embedding a dielectric in the opening, and dielectric. Forming an impurity layer thereon, removing the dielectric other than buried in the opening, and thermally oxidizing the semiconductor substrate to selectively form a thermal oxide film on the dielectric. It is characterized by having a process.

The method according to the present invention comprises a step of forming a plurality of grooves having different widths on a semiconductor substrate, a thermal oxide film is formed on the surface of the semiconductor substrate, and the narrow groove is filled with the thermal oxide film. Leaving the unfilled part in the wide groove,
And a step of burying a dielectric material in the unfilled portion.

According to the method of the present invention, a second conductivity type buried region and a first conductivity type buried region are formed in a first conductivity type semiconductor substrate, and a second conductivity type epitaxial semiconductor layer is formed on the semiconductor substrate. Forming step, selectively forming a first-conductivity-type diffusion region reaching the first-conductivity-type buried region from the epitaxial layer surface, the first-conductivity-type diffusion region, and the first-conductivity-type embedding And a step of anodizing the region to make it porous, and a step of oxidizing the porous region to make it a dielectric and separating the side surface of the second conductivity type single crystal layer with a dielectric. .

[0033]

According to the present invention, in forming a trench, the depth of the trench formed is different depending on the width of the trench, so that the trench for element isolation and the sub-trench can be formed by a single patterning and etching process. Since the trenches are formed and the trenches are buried by one-time CVD, the manufacturing cost can be reduced and the transistor characteristics can be stabilized.

Further, according to the present invention, when the compound with the main semiconductor forming substance is selectively formed inside the semiconductor substrate and then the substrate is etched to form the trench, the main semiconductor forming substance and the main semiconductor forming substance are removed. By utilizing the difference in the etching rate of the compound (1), the isolation trenches having different depths can be formed by one etching process.

According to the present invention, the surface of the trench isolation region can be flattened by introducing impurities into the surface of the dielectric layer buried in the trench and utilizing the accelerated oxidation by the impurities.

Further, according to the present invention, by filling the narrow trench with a silicon oxide film formed by thermal oxidation,
It is possible to eliminate a defect such as “spot” that occurs inside the trench.

According to the present invention, a P-type isolation region is formed by diffusing P-type impurities into the N-type epitaxial layer from both upper and lower directions, and the P-type isolation region is anodized from the surface to make it porous. By separating the side surface of the N-type epitaxial layer with a dielectric by oxidizing the porous layer, a good isolation region can be formed, and no stress is generated in the isolation region.

[0038]

Embodiments of the present invention will now be described in detail with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIG.

The N ⁺ buried region 11 is formed on the P-type Si substrate 10.
Is formed, and the N ⁻ epitaxial layer 12 is formed thereon. At this time, the conditions for forming the N ⁺ buried layer 11 are as follows: Sb is used as the N-type diffusion source, Sb ions are implanted at an acceleration voltage of 80 to 100 KeV, and the concentration is 1 to 2 × 10 ¹⁵ / cm 2.
³ N ⁺ buried layers were formed. Furthermore, 1100-12
It was activated by heating at 00 ° C. for 3 to 4 hours. Next, the substrate was thermally oxidized to form an oxide film 13 having a thickness of 5000 to 8000Å. Next, a resist pattern is formed using a mask in which patterns for the sub-trench 18 which is a shallow groove and the element isolation trench 19 are formed. At this time, the pattern size of the sub-trench and the element isolation trench must be sub-trench width <element isolation trench width. The reason is that, as shown in FIG. 2, the depth of the trench etched in the same etching time changes depending on the trench width. This is due to the microloading effect in the commonly described etching. In this embodiment, the sub-trench width = 0.3 μm and the element isolation trench width = 1.0 μm. Using the above mask, as shown in FIG. 1A, the resist can be used as a mask to form the sub-trench 18 and the element isolation trench 19 simultaneously by one-time etching. The depth of the trench at this time is determined by the sub-trench 18
However, the depth of the element isolation trench 19 is 3.5 μm.
It was 6.5 μm. The etching was performed using an ECR type etching device. Next, a thickness of 200 to 1000 is formed inside the sub-trench and the element isolation trench.
A thermal oxide film 21 of Å was formed. Next, as shown in FIG. 1B, a polysilicon film 17 was deposited by LP-CVD. At this time, the thickness of the polysilicon film is 1.0
Is about 2.0 μm. Next, as shown in FIG. 1C, a resist containing a leveling agent was coated on the polysilicon film 17, baked, and then etched back. The etch back conditions were set so that the end point of the etch back was just before reaching the oxide film 13. Next, as shown in FIG. 1C, the polysilicon film 17 on the substrate surface was oxidized by thermal oxidation so that the entire substrate surface was covered with the SiO ₂ film 15. Next, as shown in FIG. 3, a base region 26, an emitter region 36, and a collector region 38 of the transistor are formed. Further, as shown in FIG. 3, a window is opened for making contact with each region, and further wiring is performed. 39 was formed.

As described above, as shown in this embodiment, the sub-trench 18 and the element isolation trench 19 can be formed with the same mask, and both trenches can be filled simultaneously.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIGS. 4A to 4H are sectional views showing a second embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.

First, the resist 4 is formed on the surface of the semiconductor substrate 40.
1 is applied in a thickness of 2 to 4 μm (FIG. 4 (a)). The semiconductor substrate 40 includes, for example, the N ⁺ buried layer 11 shown in FIG.
The N epitaxial layer 12 is included. The resist thickness must be such that a mask effect on the substrate can be expected in ion implantation in the subsequent process.

Next, the resist in the portion corresponding to the region where the shallow trench is formed is selectively removed to form the opening 42. After that, impurities are implanted by ion implantation into the substrate at the shallow trench formation location (FIG. 4B). The introduced impurities are impurities that react with Si in the heat treatment of the next step to form a silicon compound, such as oxygen and nitrogen. For example, when oxygen is ion-implanted and 6000 Å of silicon oxide is provided in the substrate by the heat treatment of the next step, the total dose of O ⁺ ion-implantation is 2.76 × 10 ¹⁸ / cm ² . When actually performing the ion implantation, it is desirable to perform the ion implantation plural times in order to prevent crystal defects of Si around the oxide film after the oxide film is formed. In this experiment, ion implantation was divided into three times, and each condition was a dose amount / accelerating voltage = 9.2 × 10.
¹⁷ /220KeV,9.2×10 ¹⁷ / 170KeV,
It was carried out in 9.2 × 10 ¹⁷ / 130KeV.

Next, in order to activate the ion-implanted impurities, heat treatment is performed in an inert gas atmosphere after the resist is entirely removed. For example, at the time of the oxygen ion implantation described above, the temperature is 1150 to 1350 ° C. and 6 at N ₂ atmosphere.
The heat treatment is performed for 10 hours to activate oxygen to selectively form the SiO ₂ layer 43 inside the semiconductor substrate (FIG. 4C).

After that, the resist 44 is again applied to the entire surface of the substrate and the resist in the formation regions of the shallow trench and the deep trench is selectively removed to form openings 42 and 45 (FIG. 4D). .

Trenches 46 and 47 are formed by anisotropic etching using the remaining resist 44 as a mask material (FIG. 4E). For example, when the filling material 43 is an oxide, Cl ₂ , SF ₆ , CH ₂ F ₂ are generated by ECR plasma.
When etching is performed using this gas, the etching rate of Si is about 1 μm / min, whereas the etching rate of SiO ₂ is about 1/7 slower than that of Si and is 0.14 μm.
/ Min. Due to this difference in etching rate, in the same etching, Si is etched by 4.2 μm while SiO ₂ 43 is etched by 0.6 μm.
A deep trench 47 is formed.

As a result, two types of trenches having different depths can be simultaneously formed by one etching. The trench etch need not stop at the bottom of the oxide 43 and can be deeper or shallower. In the example, in order to prevent residual Si crystal defects due to ion implantation under the oxide 43, 0.4 μm further than the bottom surface of the oxide 43.
The depth of the shallow trench 46 is set to 1 μm, and the depth of the deep trench 47 is set to 4.6 μm.

The residual resist is entirely removed, and an oxide film 48 having a thickness of about 1000Å is formed on the Si surface by thermal oxidation (FIG. 4 (f)).

A dielectric such as polysilicon 49 is deposited by the LPCVD method, and the inside of the trench is filled with a dielectric material (FIG. 4G).

Finally, by etching back to remove the dielectric substance on the surface of the substrate, trench isolation having a flat surface and different depths can be formed (FIG. 4).
(H)).

Next, an embodiment of a method for planarizing the upper portion of the dielectric embedded in the trench will be described.

FIG. 5 is a sectional view showing the steps of this embodiment.
In the figure, 50 is a semiconductor substrate (Si substrate), 51 is an insulating film, 52 is a photosensitizer, 53 is an opening, 54 is an insulating film,
Reference numeral 55 is a buried dielectric, 56 is an impurity, 57 is an impurity diffused on the surface of the dielectric, and 58 is a thermal oxide film. The semiconductor substrate 50 may include the N ⁺ buried layer and the N epitaxial layer shown in FIG. 1.

The process of FIG. 5 will be described. The same figure (a)
At, an insulating film 51 is formed on the semiconductor substrate 50.

As the type of the insulating film, a thermal oxidation method or a CV method is used.
The SiO ₂ , SiN, PSG and BPSG films formed by the D method are mentioned, and the film thickness thereof is 1000 to 10000Å. It is desirable to form a SiO ₂ film of 8000 Å by the thermal oxidation method. Next, patterning is performed in a photolithography process, and a groove 53 is formed in the semiconductor substrate 50 by the RIE method using the photosensitive agent 52 as a mask. The groove 53 has a width of 0.5 to 2 μm and a depth of 2 to 10 μm. In this embodiment, the width is 1.5 μm and the depth is 6 μm (FIG. 2B). Subsequently, the insulating film 51 and the photosensitizer 52 used as the mask are removed (FIG. 7C). After that, the insulating film 54 is formed again so as to cover the entire semiconductor substrate 50 and the groove 53. The insulating film used here is a thermal oxidation method or CV
Examples of SiO ₂ and SiN produced by the D method have a film thickness of 500 to 3000 Å, but in this embodiment, a SiO ₂ film of 1000 Å is formed by the thermal oxidation method (FIG. 3D).

Next, the dielectric 53 is formed in the groove 53 so that there is no void.
Embed with. This dielectric is made of Si by thermal oxidation or CVD.
O ₂ , PSG, BPSG, polycrystalline Si, and the like are included, and the film thickness thereof is 0.3 to 1.5 μm.
8800 Å of polycrystalline Si is deposited by the D method (FIG. 7E). Next, the impurities 56 are introduced onto the dielectric 55 deposited on the semiconductor substrate 50 (FIG. 6F). As impurities to be introduced here, As, B, P, etc. are used. In this embodiment, As is ion-implanted and the implantation amount is 1 × 1.
The condition was 0 ¹⁶ cm ^-2 and the acceleration energy was 40 KeV. Subsequently, the impurities 56 introduced into the surface of the dielectric 55 are diffused to a certain depth, and heat treatment is applied to obtain a desired resistance value. The impurity diffused by this heat treatment is 57 in FIG. The heat treatment used here is N ₂ atmosphere, 950 ° C. to 1050 ° C. in the case of an electric furnace, the treatment time is 5 to 60 min, and temperature is 1000 ° C. to 1100 ° C. and the treatment time is 5 to 60 sec in the case of an apparatus such as RTA. . In this embodiment, an electric furnace is used to obtain a temperature of 1000.
C., the processing time is 20 min, and the impurities 57 are diffused in the entire vicinity of the surface of the dielectric 55. Next, in the photolithography process, only the dielectric 55 having the impurity layer 57 buried in the groove 53 in the vicinity of the surface is left by the etch back method or the like, and the dielectric 55 on the semiconductor 50 including the insulating film 54 is removed. ((H) of the same figure). Next, a thermal oxide film is formed on the entire semiconductor substrate 50 by the thermal oxidation method. By this thermal oxidation, only the impurity layer 57 in the vicinity of the surface of the dielectric 55 buried in the groove 53 is selectively accelerated and oxidized, and the thermal oxide film 109 is formed.
Are formed ((i) in the figure). The thermal oxidation conditions used here are 950 ° C. to 1050 ° C., and the oxidation time by the pyrogenic method is 10 to 60 min.
A thermal oxidation treatment at 000 ° C and 20 'is performed.

FIG. 6 shows the amount of accelerated oxidation. This figure shows H _2
2 shows the oxide film of the polycrystalline silicon layer when it was oxidized at 1000 ° C. while flowing O ₂ and O ₂ at 6 l and 4 l / sec, respectively, and it can be seen that a thick oxide film is formed when the As amount is large.

By the above steps, only the surface of the dielectric 55 buried in the groove 53 is selectively thermally oxidized, so that the recess formed in the upper portion of the dielectric 55 can be filled with the thermal oxide film 58. It becomes possible to flatten, and it is possible to prevent disconnection due to a step when forming a metal wiring later, and at the same time, obtain excellent characteristics in electrical isolation between elements.

As another embodiment according to the present invention, an electrically insulating region having a large area and a deep groove are formed on a semiconductor substrate, and an electrically insulating region having a dielectric material embedded in the groove is combined. When used as above, a thermal oxide film is selectively formed only on the upper portion of the dielectric embedded in the groove to flatten the upper portion of the dielectric.

FIG. 7 is a diagram showing a process of another embodiment according to the present invention, and 59 is an insulating film called a field oxide film.

In FIG. 7A, the insulating film 59 is selectively formed on the semiconductor substrate 50. The formation method is normal LOC
It is formed by the OS oxidation method, and the oxide film thickness is 3000 to 1000.
The thermal oxide film has a thickness of 0Å, and a thermal oxide film of 8000Å is formed in this embodiment. Next, a photoresist 52 such as a resist is applied and patterned in a photolithography process, and the insulating film 59 is etched by using the photoresist 52 as a mask to form a groove 53A (FIG. 5B). Subsequently, the semiconductor substrate 50 is etched by RIE or the like while using the photosensitizer 52 and the insulating film 59 as a mask to form a groove 53B.
At this time, the upper portion of the insulating film 59 is etched by about 1000 to 3000 Å (FIG. 7C). The width of this groove 53B is 0.
8 to 2 μm, depth 3 to 9 μm, width 1 μ in this embodiment.
m and the depth is 6 μm. Next, the insulating film 54 is formed so as to cover the semiconductor substrate 50 and the entire surface of the groove 53B. As a method of forming this insulating film 54, a thermal oxidation method or a CV method is used.
SiO ₂ , SiN, NSG, etc. by the D method are mentioned, and the film thickness has a range of 500 to 3000 Å. In this embodiment, 1000 Å of SiO ₂ is formed by the thermal oxidation method (Fig. 4 (d)).

Next, the dielectric 55 is embedded in the groove 53B so that there is no void. Examples of this dielectric material include SiO ₂ , PSG, BPSG, and polycrystalline Si produced by the thermal oxidation method or the CVD method, and the film thickness thereof is 0.3 to 1.5 μm. 8000Å are deposited ((e) in the same figure). Next, the impurities 56 are introduced onto the dielectric 55 deposited on the semiconductor substrate 50 (FIG. 6F).
As impurities to be introduced here, As, B, P, etc. are used. In this embodiment, As is ion-implanted, and the implantation amount is 1 × 10 ¹⁶ cm ⁻² and the acceleration energy is 40 KeV. Subsequently, the impurities 56 introduced on the dielectric 55 are diffused to a certain depth, and heat treatment is applied to obtain a desired resistance value. The impurity layer diffused by this heat treatment is 57 in FIG. The heat treatment used here is N ₂
In an atmosphere, the electric furnace is 950 ° C. to 1050 ° C., the treatment time is 5 to 60 min, and the apparatus such as RTA has a temperature of 1000 ° C. to 1100 ° C. and the treatment time is 5 to 60 sec.
Becomes In this embodiment, an electric furnace is used to obtain a temperature of 100.
The treatment time is set to 20 sec at 0 ° C., and the impurities 57 are diffused throughout the vicinity of the surface of the dielectric 55. Next, in the photolithography process, only the dielectric 55 having the impurity layer 57 buried in the groove 53B in the vicinity of the surface is left by the etch back method or the like, and the other dielectric 55 is removed (see FIG. h)). Next, a thermal oxide film is formed on the entire semiconductor substrate 50 by the thermal oxidation method. By this thermal oxidation, only the impurity layer 57 in the vicinity of the surface of the dielectric 55 buried in the groove 53B is selectively accelerated and oxidized to form a thermal oxide film 58 (FIG. 9 (i)). The thermal oxidation conditions used here are 950 ° C.
Oxidation time by pyrogenic method is 1 to 1050 ℃
0 to 60 min, in this embodiment, 1000 ° C., 20 mi
n thermal oxidation treatment is performed.

By selectively thermally oxidizing only the surface of the dielectric 55 buried in the above process opening 53B, the recess formed in the upper portion of the dielectric 55 can be filled with the thermal oxide film 58, In addition, the upper part of the insulating film 51 can be flattened by etching, so that disconnection due to a step can be prevented when a metal wiring is formed later, and at the same time, excellent characteristics can be obtained in electrical isolation between elements which require a large area. Can be obtained.

8A to 8E are sectional views for explaining the steps of the third embodiment of the present invention.

First, as shown in FIG. 8A, a thermal oxide film 61 is formed on a silicon substrate 60. The base 60 is
For example, as shown in FIG. 1, an N ⁺ buried layer and an N epitaxial layer may be included. At this time, the film thickness of the thermal oxide film 61 is about 300Å. Further, a silicon nitride film 62 having a thickness of about 1300Å is deposited on the upper portion thereof by using the low pressure CVD method.

Next, using the resist film (not shown) that has been deposited and patterned, as a mask material, windows having different opening widths are formed. At this time, for example, a narrow window has a width of about 0.
A wide window of 5 μm has a width of about 1.5 μm.

Anisotropic etching is performed using the above-mentioned mask material, and as shown in FIG.
And a trench 63 with a width of about 0.5 μm and a width of about 1.5 μm
Trench 64 is formed.

At this time, if etching is performed under the condition that the depth of the trench 64 is set to 4 μm, the trench 63 has a narrow opening, so that the products are not released promptly by the etching and the intrusion of the etchant is disturbed. The depth becomes shallower than that of the trench 64 and becomes about 2 μm.

Next, as shown in FIG. 8C, a portion of the inner wall of the groove where the silicon substrate is exposed is thermally oxidized to form a thermal oxide film 65, using the silicon nitride film 62 as an oxidation resistant mask.

The thermal oxidization may be either wet oxidization or dry oxidization, but it is good to carry out wet oxidization from the start to the middle of the oxidization and then dry oxidization.

At this time, by forming an oxide film having a thickness of about 5500Å, the trench 63 is formed as shown in the figure.
The trench 64 has a structure in which the trench 64 has a groove 66 whose inner wall is covered with a thermal oxide film of silicon.

Subsequently, the silicon nitride film 62 is peeled off using hot phosphoric acid, and then a reduced pressure CV is applied to fill the groove 66.
By method D, as shown in FIG. 8D, a polycrystalline silicon film 67 is deposited by about 8,000 Å to 12,000 Å. Further, anisotropic etching is performed by reactive ion etching to remove the polycrystalline silicon 67 on the surface as shown in FIG. 8 (e). At this stage, two kinds of trenches with different depth and width are completely filled,
Two types of element isolation structures 68 and 69 having different depths are formed.

FIGS. 9A to 9D are sectional views for explaining the steps of another embodiment of the present invention, which will be described below with reference to these figures.

As shown in FIG. 9A, a P type silicon substrate 70 is provided with an N ⁺ buried region 71 by an ion implantation method. Thereafter, the N type epitaxial layer 72 is subjected to low pressure CVD.
Then, a thin silicon thermal oxide film 73 is formed on the surface to a thickness of about 300Å. After that, a silicon nitride film 74 is deposited to a thickness of about 1300Å by the low pressure CVD method.

Here, the silicon thermal oxide film 73 relaxes the stress due to the silicon nitride film and improves the shape defect in the selective oxidation which will be performed later.
Is an anti-oxidation mask material for selective oxidation.

Next, using the deposited resist film (not shown) as a mask material, a window is set at a predetermined position, SF ₆ ,
Trenches 75 and 76 for element isolation are formed by reactive ion etching using a gas such as CH ₂ F ₂ or Cl ₂ .

At this time, the width of the trench 75 is about 1.5 μm.
m, and the width of the trench 76 is about 0.5 μm. At the etching time when the depth of the trench 75 is 4 μm,
Even if etching is performed at the same time, the depth of the trench 76 having a narrow frontage is about 2 μm, which is shallower than that of the trench 75.

Thereafter, in order to make the isolation function of the trench isolation trench 75 more reliable, a P ⁺ isolation region is formed at the bottom of the trench isolation trench by a technique such as ion implantation.
A mold diffusion region 77 is formed.

Subsequently, as shown in FIG. 9B, the exposed portions of silicon inside the trenches 75 and 76 are selectively oxidized. In this case, the thickness of the oxide film 78 is about 60.
If it is 00Å, the inner wall of the trench 75 is covered with an oxide film as shown in the figure, and the trench 76 is completely filled with a thermal oxide film.

Next, as shown in FIG. 9C, the remaining trenches 79 are filled with polysilicon 67 or the like by the low pressure CVD method in order to suppress the distortion due to the heat treatment in the subsequent process. In this case, the groove 79 has an opening width of about 0.8 μm and can be sufficiently filled by the low pressure CVD method without any defect.

Then, by reactive ion etching,
By anisotropically etching the polysilicon 69, the upper layer of the trench isolation portion is flattened as shown in FIG.

Thereafter, the N ⁺ region 38 for the contact of the collector, the intrinsic base region 26, and the emitter region 36 are formed by a conventional method using the ion implantation method, and element isolation is performed by the trench and the modified LOCOS. Moreover, the bipolar transistor shown in FIG. 9D is obtained.

Still another embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 10A, 0.5 to 20Ω
cm specific resistance, preferably 10 to 20 Ωcm of the single crystal silicon substrate 80 with N-type impurities (such as As, Sb,
P) with an N ⁺ -type buried region 81 doped with 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ and a P-type impurity (for example, B) of 5
A p-type buried region 82 doped with x10 ^{16 to} 5x10 ¹⁹ cm ^-3 is formed.

Next, SiH ₂ Cl ₂ and P are deposited on the Si substrate 80.
An N-type epitaxial layer 83 having a specific resistance of 0.1 to 20 Ωcm is formed to a thickness of 1 μm to 10 μm using H ₃ .

Next, a silicon nitride film 84 having a thickness of 500 to 3000 Å is formed on the epitaxial layer 83, and a well-known photolithography technique is used to form an opening at a position to be an element isolation region in the silicon nitride film. 85 and 86 are formed to expose the epitaxial layer 83.

Then, as shown in FIG. 10B, B is doped into the epitaxial layer 83 through the openings 85 and 86 by ion implantation or diffusion to activate the P-type impurity region. 87 is formed so as to reach the buried region 82. At this time, the impurity concentration of the region 87 is 1 ×
It is 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ .

Next, as shown in FIG. 10C, the P-type impurity region 87 and the P-type buried region 82 are anodized to form porous Si 88 through the openings 85 and 86 of the silicon nitride film. As shown in FIG. 11, the anodization is performed by using the Si wafer 91, which has been subjected to the above-described treatment, as an anode and a P
H ₂ O: C ₂ H ₅ COOH: H with the t electrode 92 as a cathode
It can be realized by immersing in a solution 93 of F = 1: 1: 0.3 to 3 and passing an electric current between the positive electrode and the negative electrode. In this anodization, the voltage drop due to the formation current is caused by the built-in pn junction.
The P-type region 87 and the P-type buried region 82 are controlled by controlling the formation current so as not to exceed n potential.
Can be selectively formed into porous Si. Specifically, the formation current is 20 mA / cm ² or less.

Then, the Si substrate 80 is subjected to an oxidation treatment so that the porous region 88 is entirely made of SiO ₂ to form a separation region 89 as shown in FIG. At this time, the oxidation rate of the porous region is about 100 times that of single crystal Si, which is extremely high. Further, since the expansion coefficient of the volume due to the reaction of Si + O ₂ → SiO ₂ depends on the density of the porous region, it is possible to control the porous S by controlling the impurity concentration of the P region to the above-mentioned concentration.
The density of i can be 0.9 to 1.6 g / cm ³ and the volume expansion coefficient can be 0.85 to 1.5. Also, depending on the conditions of the oxidation treatment and the HF concentration of the anodizing solution, SiO ₂ 8
Can control the etching rate of
By performing the oxidation at ˜1100 ° C., it can be suppressed to about 1 to 2 times that of the thermal oxide film.

Next, the SiN film is removed by hot phosphoric acid, and then a thermal oxide film 90 of 200 to 1000 Å is formed. Thereafter, the base 26 and the emitter 3 are formed on the N type epitaxial layer 82.
6, an N-type epitaxial layer having an N-type buried region on a P-type Si substrate and a SiO ₂ element reaching from the surface to the P-type Si substrate A semiconductor device having an isolation region can be manufactured.

[0092]

As described above, according to the present invention, the following effects can be obtained by forming the sub-trench and the element isolation trench with the same mask.

(1) Since the same mask is used, the distance between the sub-trench and the element isolation trench becomes constant, which reduces the variation in collector-base capacitance C _bc between transistors.

(2) Since the sub-trench and the element isolation trench are formed by using the same mask and are buried in one step, the manufacturing cost can be reduced.

(3) By forming trench isolations having different depths, miniaturization of the device can be realized,
There is an effect that the IC can be highly integrated.

Further, according to the present invention, a dielectric material is buried in the opening of the semiconductor substrate, an impurity layer is formed near the surface of the dielectric material, and thermal oxidation treatment is performed. The impurity layer near the surface is acceleratedly oxidized, and only the concave portion of the dielectric is selectively thermally oxidized. Therefore, (4) the impurity layer in the concave portion of the dielectric enables the planarization using the thermal oxide film in a self-aligned manner.

(5) Even when the metal wiring is formed later, the excellent flatness of the base prevents the metal wiring from being broken due to the step, and the metal wiring having high reliability can be formed.

(6) It is possible to manufacture a highly integrated semiconductor device having excellent characteristics in electrical isolation between elements.

The effect is as follows. Further, according to the present invention, when a groove having a narrow width and a shallow depth and two kinds of grooves having a wide width and a deep depth are formed by one-time etching, a narrow groove is formed. (7) The narrow groove is completely filled by filling it with a silicon thermal oxide film, and then filling the remaining portion without filling the wide groove with polysilicon by the low pressure CVD method. Does not cause defects.

(8) Since it is thermal oxidation for filling a narrow groove, the oxide film thickness is at most 5500Å, and defects such as bird's beaks at the upper part of the groove are smaller than those in the normal LOCOS method. Can be miniaturized.

(9) Since this is the oxidation of the grooved portion,
The surface of the semiconductor device after the oxidation is flattened as compared with the usual separation by LOCOS, and the defects in the post-process are reduced.

(10) Compared with the manufacturing process of a bipolar transistor by two types of depth trench isolation in which ordinary substrate etching is performed in two steps, the etching point, the embedding point and the two points are used. Is simplified.

(11) Since the isolation method between the elements of the bipolar type transistor is the dielectric isolation by the deep trench, the element isolation can be surely performed without leakage.

The effect is as follows.

Furthermore, according to the present invention, a P-type buried region is formed on a P-type substrate, an N-type epitaxial layer is formed thereon, and the P-type buried region is reached from the epitaxial layer surface to the P-type buried region. A region is created, and this is anodized to make it porous, and further oxidized to form an element isolation region by an oxide film. Therefore, compared with the conventional device isolation method, (12) Volume expansion of the oxide film The low modulus minimizes stresses on the substrate.

(13) Swelling of the surface due to oxidation can be suppressed.

(14) Since the pattern margin for preventing the operation of the parasitic element is unnecessary as compared with the P-N junction, the element can be miniaturized.

The effect is as follows.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a process of an example of the present invention.

FIG. 2 is a diagram showing a relationship between etching depth and trench width.

FIG. 3 is a cross-sectional view of an example of a semiconductor device manufactured according to the present invention.

FIG. 4 is a cross-sectional view showing a process of an example of the present invention.

FIG. 5 is a cross-sectional view showing a process of an example of the present invention.

FIG. 6 is a diagram showing the amount of accelerated oxidation when an impurity layer is provided on a dielectric and thermal oxidation is performed.

FIG. 7 is a cross-sectional view showing a process of an example of the present invention.

FIG. 8 is a cross-sectional view showing a process of an example of the present invention.

FIG. 9 is a cross-sectional view showing a process of an example of the present invention.

FIG. 10 is a cross-sectional view showing a process of an example of the present invention.

FIG. 11 is a schematic view of an apparatus for performing anodizing treatment.

FIG. 12 is a cross-sectional view of an example of a semiconductor device manufactured according to the present invention.

FIG. 13 is a sectional view of an example of a semiconductor device manufactured by a conventional technique.

FIG. 14 is a cross-sectional view illustrating a conventional technique.

FIG. 15 is a sectional view illustrating a conventional technique.

FIG. 16 is a cross-sectional view illustrating a conventional technique.

FIG. 17 is a sectional view illustrating a conventional technique.

[Explanation of symbols]

10 P-type substrate 11 N ⁺ buried layer 12 N epitaxial layer 13 thermal oxide film 18 sub-trench 19 trench 20, 22 trench isolation region 21 thermal oxide film 24 dielectric 25 insulating film 27 recess 29 thermal oxide film 33 polysilicon 36 emitter layer 38 collector layer 39 electrode 40 Si substrate 41, 44 resist 43 SiO ₂ layer 46, 47 trench 48 oxide film 49 polysilicon 50 Si substrate 51 insulating film 52 photosensitizer 53, 53A, 53B opening 54 insulating film 55 dielectric 56 impurity 57 Impurity Layer 58 Thermal Oxide Film 59 Field Oxide Film 60 Si Substrate 61,65 Thermal Oxide Film 62 Silicon Nitride Film 63,64 Trench 67 Polycrystalline Silicon 68,69 Element Isolation Structure 70 P-type Si Substrate 71 N ⁺ Type Buried Region 72 N type epitaxial layer 73 Con thermal oxide film 74 a silicon nitride film 75, 76 a trench 77 P-type diffusion region 78 silicon thermal oxide film 80 Si substrate 81 N ⁺ -type buried region 82 P type buried region 83 N-type epitaxial layer 84 of silicon nitride film 85 and 86 opening 87 P-type impurity region 88 Porous Si 89 Separation region 90 Thermal oxide film 91 Si wafer 92 Pt electrode 93 Electrolyte

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Yasushi Kawasaku 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Yukihiro Hayakawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Within the corporation

Claims (16)

[Claims] 1. A step of forming an insulating film on the surface of a semiconductor substrate, a step of providing a plurality of openings having different widths in the insulating film, and a step of etching the semiconductor substrate so as to be different according to the width of the opening. A method of manufacturing a semiconductor device, comprising: a step of forming a plurality of grooves having a depth; and a step of burying a dielectric material in the plurality of grooves to form an insulating isolation region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is an NPN transistor. 3. A step of introducing a substance forming a compound with the semiconductor substrate into the first region of the surface of the semiconductor substrate, the first region
And exposing the surface of the semiconductor substrate in the second region other than the first region and covering the surface of the other substrate with a mask material, etching the semiconductor substrate to form a shallow groove in the first region, A method of manufacturing a semiconductor device, comprising: a step of forming a deep groove in the second region; and a step of burying a dielectric in the shallow groove and the deep groove to form an insulating isolation region. 4. A step of forming an opening in an insulating film formed on a surface of a semiconductor substrate, a step of forming an insulating film in the opening, a step of embedding a dielectric in the opening, and an impurity on the dielectric. A step of forming a layer, a step of removing the dielectric other than the one buried in the opening, and a step of thermally oxidizing the semiconductor substrate to selectively form a thermal oxide film on the dielectric. A method of manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 4, wherein the dielectric embedded in the opening is polycrystalline Si. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the impurity used in the impurity layer formed on the surface of the dielectric is arsenic. 7. The method of manufacturing a semiconductor device according to claim 4, wherein the thermal oxide film formed only on the surface of the dielectric is accelerated-oxidized by the impurity layer. Method. 8. A step of forming a plurality of grooves having different widths on a semiconductor substrate, wherein a thermal oxide film is formed on a surface of the semiconductor substrate and the narrow groove is filled with the thermal oxide film, and the wide groove is formed. A method of manufacturing a semiconductor device, comprising: a step of leaving an unfilled portion in the groove; and a step of burying a dielectric material in the unfilled portion. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor substrate is a silicon substrate, and the thermal oxide film is a silicon thermal oxide film. 10. The method for manufacturing a semiconductor device according to claim 8, wherein the dielectric is polysilicon by a low pressure CVD method. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the thermal oxide film is formed by dry oxidation under reduced pressure. 12. The method of manufacturing a semiconductor device according to claim 8, wherein the thermal oxide film is wet-oxidized from the start to the middle of the oxidation, and is dry-oxidized under reduced pressure from the middle. Manufacturing method. 13. The method of manufacturing a semiconductor device according to claim 8, wherein the narrow groove has a width of 0.3 to 0.5 μm,
The depth is 1.5 to 3 μm, and the wide groove has a width of 1 μm.
m to 2 μm, and the width of the groove is 1 to 1
A method for manufacturing a semiconductor device, which is 1.5 times. 14. A step of forming a second-conductivity-type buried region and a first-conductivity-type buried region in a first-conductivity-type semiconductor substrate, and forming a second-conductivity-type epitaxial semiconductor layer on the semiconductor substrate. Selectively forming a diffusion region of a first conductivity type reaching the buried region of the first conductivity type from the surface of the epitaxial layer, the diffusion region of the first conductivity type and the buried region of the first conductivity type being an anode A semiconductor device comprising: a step of chemical conversion to make it porous; and a step of oxidizing the porous region to make it a dielectric and separating the side surface of the second conductivity type single crystal layer with a dielectric. Production method. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the porous region is made of porous Si. 16. The method of manufacturing a semiconductor device according to claim 14, wherein the density of the porous region is 0.9 to 1.6.
A method for manufacturing a semiconductor device, characterized in that g / cm ³ is set.