JP2009177221A - Method for manufacturing vertical mos transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical MOS transistor which achieves high reliability, and to provide its manufacturing method. <P>SOLUTION: A method for manufacturing a vertical MOS transistor forms two kinds of trenches 9, 10 different in width and depth on the same substrate without increasing production processes, and uses: a narrow/shallow trench as a main drive transistor; and a broad/deep trench as a transistor for taking a countermeasure against deterioration with long term reliability. The method for manufacturing vertical MOS transistor prevents the deterioration of characteristic from occurring for a long term, by generating destruction between a drain and a source in the latter. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a vertical MOS transistor having a trench structure.

  FIG. 2 is a schematic cross-sectional view of a vertical MOS transistor having a conventional trench structure. A semiconductor substrate is prepared by epitaxially growing a first conductivity type layer 2 having a lower concentration on a first conductivity type high concentration substrate 1 serving as a drain region, and a second conductivity called a body region is formed from the surface of the semiconductor substrate. The mold diffusion region 3 is formed by impurity implantation and high-temperature heat treatment at 1000 ° C. or higher. Further, a first conductivity type high concentration impurity region 7 which becomes a source region from the surface, and a second conductivity type high concentration body contact region 8 for fixing the potential of the body region by ohmic contact are formed. Here, the source region of the first conductivity type and the body contact region of the second conductivity type are normally at the same potential, so that they are laid out so as to be in contact with each other as shown in FIG. 7 and 8 are electrically connected by one contact hole provided on the region. Then, the single-crystal silicon is etched through the source region of the first conductivity type to form a silicon trench 9, and a polycrystal containing a gate insulating film 5 and a high-concentration impurity serving as a gate electrode in the silicon trench. Silicon 6 is embedded. The first conductivity type high concentration region on the back surface of the semiconductor substrate is connected to the drain metal electrode.

  With the above-described structure, a current flowing from the drain region composed of the first conductivity type high concentration region on the back surface side and the first conductivity type epitaxial region to the source region composed of the first conductivity type high concentration region on the front surface side is trenched. It can function as a vertical MOS transistor controlled by a gate buried in a trench through a gate insulating film on the side wall. This method can cope with both N channel type and P channel type by reversing the conductivity type between N and P.

In addition, the vertical MOS transistor having this trench structure has a feature that it can be applied with a miniaturization technique in the planar direction because the channel is completely formed in the vertical direction. Therefore, with the development of miniaturization technology, the planar transistor occupation area is reduced, and in recent years, the amount of drain current flowing per element unit area tends to increase.
In practice, by forming a plurality of cross-sectional structures as shown in FIG. 2, the channel width is increased, the drain current amount is increased, and a MOS transistor having an arbitrary driving capability is obtained (see, for example, Patent Document 1). ).

U.S. Pat. No. 4,767,722

However, in such a vertical MOS transistor structure, when the drain voltage exceeds the breakdown voltage of the vertical MOS transistor, a high electric field is generated at the drain side end in the vicinity of the gate oxide film in the body region that becomes a channel, and avalanche breakdown occurs. However, when such breakdown is repeatedly generated due to static electricity, noise, or the like, defects or levels are generated in this portion, and transistor characteristics are deteriorated.
Thus, the conventional structure has a problem in the long-term reliability of transistor characteristics.

  The half-eye invention includes a first conductivity type semiconductor substrate as a high concentration drain region, a first conductivity type epitaxial growth layer as a low concentration drain region formed on the semiconductor substrate, and an epitaxial growth layer. The second conductivity type body region, the second conductivity type high-concentration body contact region formed on a part of the surface of the second conductivity type body region, and the second conductivity type. A high-concentration source region of the first conductivity type formed on the surface of the body region other than the high-concentration body contact region, the body region of the second conductivity type, and the first conductivity type. A first silicon trench having a predetermined width formed through the source region and reaching a depth reaching the inside of the first conductivity type epitaxial growth layer, and a width different from that of the first silicon trench. A second silicon trench, a gate insulating film formed along a wall surface and a bottom surface of the silicon trench, and a high-concentration polycrystalline silicon gate embedded in the trench so as to be surrounded by the gate insulating film; Is a vertical MOS transistor characterized by comprising

  With the above structure, when static electricity or noise is input to the transistor, the depletion layer in the deep portion of the silicon trench immediately reaches the high-concentration drain region, and charge is released. That is, the avalanche breakdown of the side of the silicon trench at the interface between the body region and the low concentration drain region is prevented. For this reason, durability becomes long. The reason for this will be described in detail below.

  According to the present invention, it is possible to prevent deterioration in characteristics and long-term reliability of a vertical MOS transistor, and to provide a highly reliable vertical MOS transistor.

It is sectional drawing of the vertical MOS transistor of this invention. It is sectional drawing of the conventional vertical MOS transistor. It is sectional drawing which shows operation | movement of a vertical MOS transistor when a trench is shallow. It is sectional drawing which shows operation | movement of a vertical MOS transistor when a trench is deep. It is sectional drawing of the Example of the vertical MOS transistor of this invention. It is a top view of another Example of the vertical MOS transistor of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. Here, an example in which the N conductivity type is used as the first conductivity type and the P conductivity type is used as the second conductivity type will be described, but the reverse conductivity type can be similarly applied.

  FIG. 1 is a cross-sectional view of an N-channel vertical MOS transistor of the present invention. This forms a semiconductor substrate by epitaxially growing a lower concentration N conductivity type layer 2 (low concentration drain region) on the N conductivity type high concentration substrate 1 serving as a drain region. A P conductivity type diffusion region 3 which becomes a body region from the surface of the N conductivity type layer 2 is formed by impurity implantation and high temperature heat treatment at 1000 ° C. or higher. Further, an N conductivity type high concentration impurity region 7 which becomes a source region from the surface, and a P conductivity type high concentration body contact region 8 for fixing the potential of the body region 3 by ohmic contact are formed. Although not shown, the source region 3 and the body region 8 are electrically connected by a metal wiring, and this is used as a source electrode. Further, a metal wiring is provided on the N conductivity type high concentration substrate 1 on the back surface side, and this is used as a drain electrode.

  As shown in FIG. 1, first and second silicon trenches 9 and 10 that reach the N conductivity type layer 2 are provided at approximately the center of the two source regions 7. The depth and width of the first and second silicon 9 and 10 are different. A gate electrode 6 made of polycrystalline silicon is buried in each of the silicon trenches 9 and 10 via a gate insulating film 5 made of an oxide film. That is, two N channel MOS transistors are formed.

  In the present invention, two trenches are prepared as described above, and the one having a narrow width and a shallow depth is used as a main driving transistor (for calculation, output, and control) as a transistor. The deeper one is used as a transistor for long-term reliability degradation countermeasures (for preventing breakdown degradation due to static electricity and noise).

  In the present invention, two trenches 9 and 10 having different depths are used. This effect will be described with reference to FIGS. It is known that the breakdown voltage and the breakdown characteristics at the time of high drain voltage differ depending on whether the trench depth is usually shallow or deep. Incidentally, the gate voltage and the body-source voltage are 0V here.

  First, the case where the trench of the silicon trench is shallow (first silicon trench 9) will be described with reference to FIG. In the vertical MOS transistor as shown in FIG. 3, when the voltage of the drain region 1 is increased, the depletion layer 4 is shown by the voltage applied between the drain region 1 and the body region 3 and between the drain region 1 and the gate electrode 6. It grows like the dotted line 4 of 3. The depletion layer 4 in FIG. 3 can be classified into three types with respect to how the depletion layer 4 extends with respect to voltage.

  First, since the gate electrode 6 is 0 V, the depletion layer 4 immediately below the first silicon trench 9 is formed with a depletion layer width determined by the voltage of the drain region 1 and the concentration of the epitaxial layer 2 (low concentration drain region).

  Secondly, the depletion layer 4 in the junction of the epitaxial layer 2-body region 3 sufficiently separated from the first trench 9 is formed with a width determined by the voltage of the drain region 1 and the respective concentrations.

  Third, in the same epitaxial layer 2 -body region 3 junction and in the vicinity of the gate oxide film as indicated by the point 11A in FIG. 3, it is also affected by the voltage of the gate electrode 6 via the gate insulating film 5, The depletion layer 4 on the body region 3 side is difficult to extend.

  Therefore, in FIG. 3, the highest electric field among the three types of depletion layers 4 is the epitaxial layer 2 -body region 3 junction in the vicinity of the gate oxide film, and this voltage is applied when an excessive drain electrode 1 voltage is applied. Avalanche breakdown occurs in the part, and current flows.

  Normally, in the specifications of the vertical MOS transistor, a low voltage is set as a use condition so that such an excessive voltage is not applied. However, in actual use, such breakdown phenomenon often occurs due to static electricity or various electric noises. To do. At the point 11A in FIG. 3 where such an avalanche phenomenon occurs, slight defects and levels occur in the silicon in the body region 3 and in the gate insulating film 5. When defects and levels occur in the gate insulating film 5 and the current path in this way, carriers are taken in and out through the gate insulating film 5 and potential barriers are generated due to trapping of carriers therein. As a result, an increase in leakage current, a change in threshold voltage, current drive capability, and breakdown voltage occurs. When such a phenomenon occurs repeatedly, the characteristics fluctuate with time, or in the worst case, it leads to a long-term reliability failure such that the transistor does not operate.

  On the other hand, when the depth of the silicon trench is increased as shown in FIG. 4 (in the case of the second silicon trench 10), the depletion layer 4 immediately below the silicon trench 10 becomes the drain region 1 (when the voltage of the drain region 1 is increased). Since the depletion layer 4 is less likely to extend beyond the high concentration substrate 1), the electric field at the point 12B in FIG. 4 is increased. If the electric field at this point 12B becomes higher than the point 11A in FIG. 3, unlike the case of FIG. 3, this low-concentration drain region 2 (epitaxial layer 2) -drain region when a voltage is applied to an excessive drain region. Current flows due to avalanche breakdown or zener breakdown at the interface of 1 (high concentration substrate 1).

  Since the avalanche breakdown at this place is not a place causing the deterioration of the junction or the gate oxide film as described above, it is difficult to cause the characteristic fluctuation such as the leakage current and the threshold voltage. Further, if the zener is destroyed, deterioration is less likely to occur. That is, as shown in FIG. 4, when the trench depth is deep and the breakdown occurs at the interface between the epitaxial layer and the high concentration substrate, the long-term reliability is excellent. However, the structure of FIG. 4 has the disadvantage that the high frequency characteristics are inferior because the overlap capacitance between the gate electrode 6 and the (low concentration) drain region 2 is increased as compared with FIG.

  In the present invention, transistors having different silicon trench depths are provided on the same substrate as shown in FIG. In addition to the main transistor for mainly determining the characteristics of the product so as not to cause junction breakdown in the vicinity of the gate insulating film 5 of the transistor having a shallow trench in the silicon trench 9 shown in FIG. By forming the silicon trench 10 having a deep groove, a part having a breakdown voltage lower than the junction breakdown voltage in the vicinity of the gate is intentionally provided. This has the effect of preventing characteristic fluctuations and malfunctions due to long-term use. Moreover, since such a part is provided only in a part of the product, the high-frequency characteristics are hardly hindered.

  Further, in order to form silicon trenches 9 and 10 having different depths on the same semiconductor substrate as shown in FIG. 1, the microloading effect at the time of silicon dry etching for forming trench grooves is used. In other words, when the silicon trench width is narrowed, the intrusion of ions for etching is hindered and the etching rate is slowed down, so that the etching depth becomes shallow. Therefore, the trench width of the main transistor part that determines the product characteristics is narrowed, and the low withstand voltage is reduced. The trench width is intentionally widened in the portion to be made. In this way, the silicon trenches 9 and 10 having different depths are realized without increasing the number of manufacturing steps.

  Although the microloading effect depends on the etching conditions and the target trench depth, the silicon exposure width at the time of etching is observed from about 1.0 μm or less. It becomes remarkable at 0.8 μm or less. For example, the difference in etching depth between the etching width of 0.8 μm and 1.3 μm or more is about 0.2 μm.

  When forming a shallow trench like the first silicon trench 9 (when aiming at a shallow width during etching), it is 0.8 μm or less, and when aiming deeply like the second silicon trench 10, it is 1.5 μm or more. It is desirable. Further, when the trench width is increased, it is necessary to deposit a thick polycrystalline silicon corresponding to the trench. For example, when the width of the first silicon trench 9 is 0.8 μm and the width of the second silicon trench 10 is 1.8 μm, the width of the first silicon trench 9 is 1.8 μm or more in accordance with the wider second silicon trench 10. By depositing crystalline silicon, the grooves of the first and second silicon trenches 9 and 10 can be planarized.

  Next, another embodiment of the present invention will be described with reference to FIG. In FIG. 5, a first silicon trench 9 having a narrow groove depth and a narrow width is disposed between main transistor cells that determine drive capability, and a second silicon trench 10 having a large groove width is disposed on the outer periphery of the product chip. In FIG. 5, since the high concentration source region is not connected to the second silicon trench 10, this portion does not contribute to the transistor operation at all. And even if degradation due to avalanche breakdown occurs here, there is an advantage that the transistor performance is not affected at all.

  Yet another embodiment is shown in FIG. FIG. 6 is a plan view showing the substrate surface of one vertical MOS transistor. The hatched portions are the first and second silicon trenches 9 and 10 provided on the substrate surface. Here, the grooves are provided by etching leaving the six island-shaped semiconductor substrate surfaces. A silicon gate electrode 6 is embedded in the trench with a gate insulating film (oxide film) interposed therebetween. That is, six source regions 7 are provided in an island shape so as to surround the body contact region 8. Of course, the body region 3, the low concentration drain region 2 and the high concentration drain region 1 are provided under the body contact region 8 and the source region 7. Further, a low concentration drain region 2 and a high concentration drain region 1 are provided under the first and second silicon trenches 9 and 10.

  In this example, the first and second silicon trenches 9 and 10 are arranged between main transistor cells (in FIG. 6, each consisting of a source region 7 and a body contact region 8) that determine driving capability. Yes. As shown in FIG. 6, the corners of the square transistor cell (consisting of the source region 7 and the body contact region 8) are chamfered. By repeating this arrangement, the channel width is increased. The source region 7 and the body contact region 8 are connected, and each is also connected. The channel width is a length obtained by adding the outer peripheral length of each source region 7. Here, a trench between adjacent (closest) transistor cells is a first silicon trench 9 having a narrow width, and a current mainly flows here. On the other hand, the silicon trench between the transistor cells arranged obliquely becomes the second silicon trench 10 having a large width. This is apparent from FIG. That is, this is a wide second trench. In FIG. 6, the following relationship is always established by taking such a structure for the length A of 13 and the length B of 14.

A <B
That is, by dry etching, the depth of the silicon trench between the adjacent source regions 7 becomes shallow, and the depth of the silicon trench between the source regions 7 formed diagonally increases.

  A current flows through the side wall of the second silicon trench 10 in the same manner as the side wall of the first trench. However, since the ratio to the entire channel width is small, the characteristics change even if this part deteriorates due to an avalanche phenomenon or the like. There is little influence on.

  One advantage of this structure is that the area ratio of the second silicon trench 10 in the chip is larger than that in FIG. 5 and is uniformly distributed in the chip, so that the current caused by the breakdown caused by an excessive drain voltage is obtained. It can be absorbed uniformly in the chip. This leads to, for example, the generation of local heat and the resulting change or destruction of surrounding characteristics.

  The second point is that even when there is intra-chip variation in the trench depth, it is possible to always determine the destructive portion in the second silicon trench 10. For example, in the case where the second trench is only on the outer periphery of the chip as shown in FIG. 5, when the trench depth at the center of the chip becomes deeper due to the variation in the trench depth, the depth of the first trench and the second trench is increased. The relationship may be reversed. However, in the structure as shown in FIG. 6, the second silicon trench 10 is always present near the first silicon trench 9, so that the depth of the second silicon trench 10 is relatively deep. Even if the variation is large, it can be maintained.

  Further, in FIG. 6, it is desirable that the side wall surface of the first silicon trench 9 is a silicon single crystal 100 surface and the side wall surface of the second silicon trench 10 is a silicon single crystal 110 surface. This can be easily realized by adjusting the planar orientation of the transistor cell of FIG. 6 on a silicon substrate having a main surface of 100 planes.

  In general, in a MOS transistor, when the channel surface is 110, it is known that the gate oxide film becomes thicker, the mobility becomes lower, the threshold voltage becomes higher, and the driving ability becomes lower than the 100 surface. . This is due to the difference in atomic density on the crystal plane. In the vertical MOS transistor, by adjusting the trench side wall surface, that is, the channel surface by the method described above, the driving capability of the transistor driven by the second silicon trench 10 is reduced. The influence of characteristic deterioration due to the avalanche phenomenon can be reduced.

  Here, even when the transistor cell is rectangular in FIG. 6, the width of the opposite corners of the transistor cell is larger than the width of the first trench, so that the same effect as described above can be obtained. However, in this case, another undesirable phenomenon such as deterioration of leakage characteristics due to stress concentration at the corners or the like occurs, so that the cell structure is not appropriate. That is, the structure of FIG. 6 in which the corner of the transistor cell is chamfered also has an advantage of preventing characteristic deterioration due to sharpening of the corner.

  As described above, in the present invention, the structure as shown in FIGS. 5 and 6 can prevent the deterioration of the characteristics of the vertical MOS transistor and ensure high long-term reliability. However, FIG. 5 and FIG. Needless to say, the effect of the present invention is further enhanced.

1 First conductivity type high concentration substrate (high concentration drain region)
2 First conductivity type epitaxial layer (low concentration drain region)
3 Second conductivity type body region (body region)
4 Depletion layer 5 Gate insulating film (gate oxide film)
6 silicon gate electrode 7 source region 8 body contact region 9 first silicon trench 10 second silicon trench 11 point A 12 point B 13 width A
14 Width B

Claims (3)

Forming a first conductivity type epitaxial growth layer serving as a low concentration drain region on a first conductivity type semiconductor substrate serving as a high concentration drain region;
A second step of forming a body region of a second conductivity type on the epitaxial growth layer;
A third step of forming a second conductivity type high-concentration body contact region on a portion of the surface of the second conductivity type body region;
A fourth step of forming a high-concentration source region of the first conductivity type on a surface of the second-conductivity-type body region other than the high-concentration body contact region; and A first silicon trench having a depth reaching the inside and a predetermined width, and a second silicon trench having a width greater than that of the first silicon trench and a depth greater than the first silicon trench, and the body region of the second conductivity type and the first silicon trench. A fifth step of simultaneously forming a high-concentration source region of one conductivity type;
A sixth step of forming a gate insulating film along the wall surface and bottom surface of the first and second silicon trenches;
Burying a high-concentration polycrystalline silicon gate in the first and second trenches so as to be surrounded by the gate insulating film.   In the third step and the fourth step, the high-concentration body contact region is in contact with the second silicon trench formed later, and the high-concentration source region is not in contact with the second silicon trench. 2. The method of manufacturing a vertical MOS transistor according to claim 1, wherein the vertical MOS transistor is formed as follows.   2. The longitudinal direction according to claim 1, wherein in the fifth step, the trench width of the first silicon trench is 0.8 μm or less, and the trench width of the second silicon trench is 1.5 μm or more. Type MOS transistor manufacturing method.

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