JP2020064910A - Switching element - Google Patents

Abstract

To provide a technique for relaxing an electric field in the vicinity of a trench in a switching element having a connection region and a bottom region.SOLUTION: A switching element includes a semiconductor substrate, a trench, and a gate insulation film. A side face of the trench has a step portion on the lower side of a body region. On the lower side of the step portion, a width of the trench is narrower than that of the upper side of the step portion. The side face of the trench has a first side face located on the upper side of the step portion and a second side face located on the lower side of the step portion. A p-type impurity concentration in a connection region in contact with the gate insulation film on the first side face is distributed so as to be reduced from the upper side to the lower side and a p-type impurity concentration in a connection region in contact with the gate insulation film on the second side face is distributed so as to be reduced from the upper side to the lower side. A p-type impurity concentration on the lower end of the connection region in contact with the gate insulation film on the second side face is higher than the p-type impurity concentration on the upper end of the connection region in contact with the gate insulation film on the first side face.SELECTED DRAWING: Figure 2

Description

  The technology disclosed in the present specification relates to a switching element.

  Patent Document 1 discloses a switching element having a semiconductor substrate having a trench provided on the upper surface. A gate insulating film and a gate electrode are arranged in the trench. The semiconductor substrate has a p-type body region and an n-type drift region. The body region is in contact with the gate insulating film. The drift region is in contact with the gate insulating film below the body region. Further, the semiconductor substrate has a p-type bottom region which is in contact with the gate insulating film on the bottom surface of the trench, and a p-type connecting region which is in contact with the gate insulating film on the side surface of the trench. The connection region connects the body region and the bottom region. The drift region described above is in contact with the gate insulating film in the range where the connection region does not exist.

  When the switching element is turned off, the depletion layer extends from the body region and the bottom region into the drift region. The depletion layer extending from the bottom region suppresses the concentration of the electric field near the lower end of the trench.

Japanese Unexamined Patent Publication No. 2018-046197

  In the switching element of Patent Document 1, when turned off, a high electric field is generated at the corners at the lower end of the trench. The present specification provides a technique for relaxing an electric field in the vicinity of a trench in a switching element having a connection region and a bottom region.

  A switching element disclosed in the present specification includes a semiconductor substrate, a trench provided on an upper surface of the semiconductor substrate, a gate insulating film arranged in the trench, and a gate insulating film arranged in the trench. A gate electrode is insulated from the semiconductor substrate by a film. The semiconductor substrate has a p-type body region in contact with the gate insulating film, an n-type drift region in contact with the gate insulating film below the body region, and the gate insulating film on the bottom surface of the trench. It has a p-type bottom region that is in contact with the film, and a p-type connection region that is in contact with the trench on the side surface of the trench and that connects the body region and the bottom region. The side surface of the trench has a step portion below the body region. The width of the trench is narrower on the lower side of the step than on the upper side of the step. The side surface of the trench has a first side surface located above the step portion and a second side surface located below the step portion. The p-type impurity concentration of the connection region in contact with the gate insulating film on the first side surface is distributed so as to decrease from the upper side to the lower side, and the p-type impurity concentration on the second side surface affects the gate insulating film. The p-type impurity concentration of the contact regions in contact with each other is distributed so as to decrease from the upper side to the lower side. The p-type impurity concentration at the upper end of the connection region in contact with the gate insulating film on the second side surface is higher than the p-type impurity concentration at the lower end of the connection region in contact with the gate insulating film on the first side surface. high.

  In the above switching element, the side surface of the trench has a step portion below the body region. The width of the trench on the lower side of the step portion is narrower than that on the upper side of the step portion. By providing the step portion, the electric field concentration portions are dispersed in the corner portion at the lower end of the trench and the step portion, so that the electric field at the corner portion at the lower end of the trench can be relaxed.

  Further, in the above switching element, the p-type impurity concentration of the connection region on each side surface (first side surface and second side surface) located above and below the step portion is distributed so as to decrease from the upper side to the lower side. ing. When the switching element is off, the depletion layer spreads in the connection region. Further, in the region where the p-type impurity concentration is high, the depletion layer is less likely to spread than in the region where the p-type impurity concentration is low. Therefore, the width of the depletion layer is narrower in the region where the p-type impurity concentration is higher than in the region where the p-type impurity concentration is low. Therefore, in the region having a high p-type impurity concentration, the width of the non-depleted region (the region not depleted) is wider than that in the region having a low p-type impurity concentration. Therefore, in each of the first side surface and the second side surface, the non-depleted regions are distributed such that the width of the non-depleted region becomes narrower from the upper side to the lower side. Further, the p-type impurity concentration at the upper end of the connection region in contact with the second side face is higher than the p-type impurity concentration at the lower end of the connection region in contact with the first side face. That is, the width of the non-depleted region at the upper end of the connection region in contact with the second side face is wider than the width of the non-depleted region at the lower end of the connection region in contact with the first side face. Therefore, the non-depleted regions are smoothly connected above and below the step. Since the step portion is covered by the non-depleted region that is smoothly connected in this way, it is possible to reduce the electric field concentration at the step portion. Thus, according to this semiconductor device, the electric field concentration near the trench can be relaxed.

The top view of MOSFET10. Sectional drawing in the II-II line of FIG. Sectional drawing in the III-III line of FIG. Sectional drawing which shows distribution of the depletion layer near a trench when MOSFET10 is OFF. 6A to 6D are views for explaining the manufacturing process of the MOSFET 10. 6A to 6D are views for explaining the manufacturing process of the MOSFET 10. 6A to 6D are views for explaining the manufacturing process of the MOSFET 10. 6A to 6D are views for explaining the manufacturing process of the MOSFET 10. 6A to 6D are views for explaining the manufacturing process of the MOSFET 10. 6A to 6D are views for explaining the manufacturing process of the MOSFET 10. 6A to 6D are views for explaining the manufacturing process of the MOSFET 10. Sectional drawing of MOSFET of a modification (FIG. 2 corresponding figure).

  1 and 2 show a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 10 according to an embodiment. The MOSFET 10 includes a semiconductor substrate 12, electrodes, insulating layers, and the like. Note that, in FIG. 1, the electrodes, the insulating layer, and the like on the upper surface 12a of the semiconductor substrate 12 are not shown for the sake of clarity. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as an x direction, a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as ay direction, and a thickness direction of the semiconductor substrate 12 is referred to as az direction. The semiconductor substrate 12 is made of, for example, SiC (silicon carbide). However, the semiconductor substrate 12 may be made of, for example, another semiconductor material such as Si (silicon).

  As shown in FIGS. 1 to 3, a plurality of trenches 22 are provided on the upper surface 12 a of the semiconductor substrate 12. As shown in FIG. 1, each trench 22 extends linearly in the y direction. The plurality of trenches 22 are arranged at intervals in the x direction. As shown in FIG. 2, the inner surface of each trench 22 is covered with a gate insulating film 24. The gate insulating film 24 has a bottom insulating film 24a and a side insulating film 24b. The bottom insulating film 24 a is provided on the bottom of the trench 22. The bottom insulating film 24a covers the bottom surface of the trench 22 and the side surface near the bottom surface. The side surface insulating film 24b covers the side surface of the trench 22 above the bottom insulating film 24a. The thickness of the bottom insulating film 24a (that is, the width between the upper surface and the lower surface of the bottom insulating film 24a (in other words, the distance between the lower end of the gate electrode 26 and the bottom surface of the trench 22)) is the thickness of the side surface insulating film 24b. (I.e., the distance between the side surface of the trench 22 and the side surface of the gate electrode 26). A gate electrode 26 is arranged in each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of each gate electrode 26 is covered with an interlayer insulating film 28.

  As shown in FIGS. 2 and 3, the side surface 23 of the trench 22 has a step portion 40 below the body region 32 (main body region 32b) described later. The width of the trench 22 on the lower side of the step portion 40 is narrower than that on the upper side of the step portion 40. That is, since the step portion 40 is provided, the width of the trench 22 (width in the x direction) becomes narrower from the upper side to the lower side. The step portion 40 is located below the lower end of the gate electrode 26. The step portion 40 extends substantially parallel to the upper surface of the semiconductor substrate 12 (that is, the xy plane). The side surface 23 of the trench 22 has a first side surface 23 a located above the step portion 40 and a second side surface 23 b located below the step portion 40. Of the side surface 23 of the trench 22, the range from the lower end of the body region 32 to the step portion 40 is the first side surface 23a, and the range from the lower end of the trench 22 to the step portion 40 is the second side surface 23b. Each of the first side surface 23a and the second side surface 23b extends in the depth direction (z direction) of the semiconductor substrate 12. The first side surface 23a and the second side surface 23b are connected by the step portion 40.

  The upper electrode 70 is arranged on the upper surface 12 a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 at the portion where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is arranged on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with the lower surface 12b of the semiconductor substrate 12.

  As shown in FIGS. 2 and 3, a plurality of source regions 30, a body region 32, a drift region 34, a drain region 35, a plurality of bottom regions 36 and a plurality of connection regions 38 are provided inside the semiconductor substrate 12. There is.

  Each source region 30 is an n-type region. Each source region 30 is arranged at a position exposed on the upper surface 12a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the side surface insulating film 24b on the side surface 23 of the trench 22. Each source region 30 is in contact with the side surface insulating film 24b at the upper end of the trench 22.

  The body region 32 is a p-type region. The body region 32 is in contact with each source region 30. The body region 32 extends from the range sandwiched by the two source regions 30 to the lower side of each source region 30. The body region 32 has a contact region 32a and a main body region 32b. The contact region 32a has a higher p-type impurity concentration than the main body region 32b. The contact region 32a is arranged in the range sandwiched by the two source regions 30. The contact region 32a is in ohmic contact with the upper electrode 70. The main body region 32b is in contact with the side surface insulating film 24b on the side surface 23 of the trench 22. The main body region 32b is in contact with the side surface insulating film 24b below the source region 30.

  The drift region 34 is an n-type region. The drift region 34 is arranged below the body region 32, and is separated from the source region 30 by the body region 32. As shown in FIG. 3, the drift region 34 is in contact with the side surface insulating film 24b and the bottom insulating film 24a on the side surface 23 of the trench 22. The drift region 34 is in contact with the side surface insulating film 24b and the bottom insulating film 24a below the body region 32.

  The drain region 35 is an n-type region. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 is arranged below the drift region 34. The drain region 35 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72.

  Each bottom region 36 is a p-type region. As shown in FIGS. 2 and 3, each bottom region 36 is arranged in a range exposed at the bottom surface of the corresponding trench 22. Each bottom region 36 is in contact with the bottom insulating film 24a on the bottom surface of the corresponding trench 22. Each bottom region 36 extends in the y direction along the bottom surface of the corresponding trench 22. The periphery of each bottom region 36 is surrounded by the drift region 34. Each bottom region 36 is separated from the body region 32 by a drift region 34 except where the connection region 38 is formed.

  Each connection region 38 is a p-type region. As shown in FIG. 2, each connection region 38 is arranged in a range exposed on the side surface 23 of the corresponding trench 22. Each connection region 38 is in contact with the side surface insulating film 24b and the bottom insulating film 24a on the side surface 23 of the corresponding trench 22. Each connection region 38 extends in the z direction along the side surface 23 of the trench 22. As shown in FIG. 1, for each trench 22, a plurality of connection regions 38 are arranged at intervals in the y direction. As shown in FIG. 2, the upper end of the connection region 38 is connected to the main body region 32b. The lower end of the connection area 38 is connected to the bottom area 36. That is, the body region 32 and the bottom region 36 are connected by the connection region 38. The connection region 38 has a plurality of high concentration regions 42, a plurality of medium concentration regions 44, and a plurality of low concentration regions 46.

  The high concentration region 42 has a higher p-type impurity concentration than the medium concentration region 44. The p-type impurity concentration of the high concentration region 42 is higher than the p-type impurity concentration of the main body region 32b. The medium concentration region 44 has a higher p-type impurity concentration than the low concentration region 46. As shown in FIG. 2, each connection region 38 is in a range in contact with the first side surface 23a of the trench 22, and is a high concentration region 42 (hereinafter, referred to as a first high concentration region 42a) and a medium concentration region 44 (hereinafter, referred to as a first concentration region). It has a first medium concentration region 44a) and a low concentration region 46 (hereinafter referred to as a first low concentration region 46a). In the range in contact with the first side surface 23a of the trench 22, the first high-concentration region 42a constitutes the upper part of the connection region 38, and the first low-concentration region 46a constitutes the lower part of the connection region 38. The medium concentration region 44a constitutes the connection region 38 in the range between the first high concentration region 42a and the first low concentration region 46a. That is, the p-type impurity concentration of the connection region 38 in contact with the trench 22 on the first side face 23a is distributed so as to gradually decrease from the upper side to the lower side. The upper end of the first high concentration region 42a is connected to the main body region 32b. Further, each of the connection regions 38 is in the range in contact with the second side face 23b of the trench 22, the high concentration region 42 (hereinafter, referred to as the second high concentration region 42b) and the medium concentration region 44 (hereinafter, the second medium concentration region 44b). And a low-concentration region 46 (hereinafter referred to as a second low-concentration region 46b). In the range in contact with the second side surface 23b of the trench 22, the second high-concentration region 42b constitutes the upper part of the connection region 38, and the second low-concentration region 46b constitutes the lower part of the connection region 38. The medium-concentration region 44b constitutes the connection region 38 in the range between the second high-concentration region 42b and the second low-concentration region 46b. That is, the p-type impurity concentration of the connection region 38 in contact with the trench 22 on the second side face 23b is distributed so as to gradually decrease from the upper side to the lower side. The upper end of the second high concentration region 42b is connected to the lower end of the first low concentration region 46a and the step portion 40, and the lower end of the second low concentration region 46b is connected to the bottom region 36. The second high concentration region 42b has a higher p-type impurity concentration than the first low concentration region 46a.

  Next, the operation of MOSFET 10 will be described. When the MOSFET 10 is used, the MOSFET 10, the load (for example, a motor), and the power supply are connected in series. A power supply voltage (about 800 V in this embodiment) is applied to the series circuit of the MOSFET 10 and the load. The power supply voltage is applied such that the drain side (lower electrode 72) of MOSFET 10 has a higher potential than the source side (upper electrode 70). When a gate-on potential (potential higher than the gate threshold) is applied to the gate electrode 26, a channel (inversion layer) is formed in the main body region 32b in the range in contact with the side surface insulating film 24b, and the MOSFET 10 is turned on. When a gate-off potential (potential equal to or lower than the gate threshold) is applied to the gate electrode 26, the channel disappears and the MOSFET 10 turns off.

  When the MOSFET 10 is turned off, a reverse voltage is applied to the pn junction at the interface between the drift region 34 and the p-type region (that is, the body region 32, the connection region 38, and the bottom region 36). Therefore, the depletion layer spreads from the pn junction to the drift region 34. The depleted drift region 34 holds the voltage between the body region 32 and the drain region 35. Particularly, since the depletion layer spreads from the bottom region 36 to the periphery thereof, electric field concentration near the lower end of the trench 22 is suppressed. Further, the side surface 23 of the trench 22 has a step portion 40 below the body region 32. By providing the step portion 40, electric field concentration points are dispersed in the corner portion at the lower end of the trench 22 and the step portion 40. Therefore, in MOSFET 10, the electric field at the corner of the lower end of trench 22 can be relaxed more preferably.

  When the MOSFET 10 is turned off, the reverse voltage is also applied to the pn junction at the interface between the connection region 38 and the drift region 34. Then, a depletion layer spreads from the pn junction into the connection region 38. In the MOSFET 10, the connection regions 38 on each of the side faces (the first side face 23a and the second side face 23b) located above and below the step 40 have a high concentration region 42, a medium concentration region 44, and a low concentration region 46, respectively. That is, the p-type impurity concentration of the connection region 38 is distributed so as to decrease from the upper side to the lower side of each of the first side surface 23a and the second side surface 23b. In the region where the p-type impurity concentration is high, the depletion layer is less likely to spread than in the region where the p-type impurity concentration is low. FIG. 4 shows the distribution of the depletion layer 100 and the non-depleted region 102 (non-depleted region). In FIG. 4, the hatched semiconductor region is the non-depleted region 102, and the unhatched semiconductor region is the depleted region 100. As shown in FIG. 4, the width of the depletion layer 100 is narrower in a region having a high p-type impurity concentration than in a region having a low p-type impurity concentration. Therefore, in the region having a high p-type impurity concentration, the width of the non-depleted region 102 becomes wider than in the region having a low p-type impurity concentration. Specifically, in the high concentration region 42, the width of the non-depleted region 102 is wider than in the medium concentration region 44, and in the medium concentration region 44, the width of the non-depleted region 102 is wider than that in the low concentration region 46. Therefore, in each of the first side surface 23a and the second side surface 23b, the non-depleted regions 102 are distributed such that the width of the non-depleted region 102 becomes narrower from the upper side to the lower side. In the MOSFET 10, the p-type impurity concentration of the second high concentration region 42b is higher than the p-type impurity concentration of the first low concentration region 46a. Therefore, the width of the non-depleted region 102 of the second high concentration region 42b becomes wider than the width of the non-depleted region 102 of the first low concentration region 46a. Therefore, the non-depleted regions 102 are smoothly connected above and below the step portion 40. Since the step portion 40 is covered with the non-depleted region 102 that is smoothly connected in this way, electric field concentration in the step portion 40 can be mitigated when the MOSFET 10 is turned off.

  Next, a method of manufacturing MOSFET 10 will be described. First, as shown in FIG. 5, an n-type drain region 35, an n-type drift region 34 arranged on the drain region 35, a p-type main body region 32 b arranged on the drift region 34, A semiconductor substrate 12x having a p-type contact region 32a and an n-type source region 30 arranged on the main body region 32b is prepared. The drift region 34, the main body region 32b, the contact region 32a, and the source region 30 can be formed by a conventionally known method such as ion implantation or epitaxial growth.

  Next, as shown in FIG. 6, a mask 80 having an opening 80a is formed on the upper surface of the semiconductor substrate 12x. The opening 80a forms a connection region 38 in a range in contact with the second side surface 23b of the trench 22 (a range in which the trench 22 is formed by a two-dot chain line is shown in FIG. 6) formed in a later step. It is provided on the upper part of the part that should be. The mask 80 is made of, for example, silicon oxide. Then, p-type impurities are implanted from the upper surface of the semiconductor substrate 12x through the mask 80. In the range where the upper surface of the semiconductor substrate 12x is covered with the mask 80, the mask 80 blocks the implantation of p-type impurities into the semiconductor substrate 12x. Here, the p-type impurity is implanted a plurality of times while changing the dose amount of the p-type impurity and the irradiation energy, so that the second low-concentration region 46b, the second medium-concentration region 44b, and the second high-concentration region 42b are divided into three regions. Forming regions of layers. At this time, the second high concentration region 42b, the second medium concentration region 44b, and the second low concentration region 46b are formed in this order so that the p-type impurity concentration decreases. In addition, the second high-concentration region 42b is formed so as to have a width in the x direction wider than that of the second medium-concentration region 44b and the second low-concentration region 46b.

  Next, as shown in FIG. 7, a mask 82 having an opening 82a is formed on the upper surface of the semiconductor substrate 12x. The width of the opening 82a is provided to be equal to the width of the trench 22 in the x direction at the depth position of the second side surface 23b of the trench 22 to be formed. The mask 82 is made of, for example, silicon oxide. Then, the trench 22a is formed by etching the upper surface of the semiconductor substrate 12x in the opening 82a. Next, as shown in FIG. 8, a protective oxide film 84 is formed so as to cover the inner surface of the trench 22a. Then, p-type impurities are implanted into the bottom surface of the trench 22a through the protective oxide film 84 to form the bottom region 36.

  Next, after removing the protective oxide film 84 and the mask 82, as shown in FIG. 9, a buried oxide film 86 having an opening 86a is formed so as to fill the trench 22a. The opening 86a is provided above the portion where the connection region 38 is to be formed in the range in contact with the second side surface 23b of the trench 22. The buried oxide film 86 is made of, for example, silicon oxide. Then, p-type impurities are implanted from the upper surface of the semiconductor substrate 12x through the buried oxide film 86. In the range where the upper surface of the semiconductor substrate 12x is covered with the buried oxide film 86, the buried oxide film 86 blocks the implantation of p-type impurities into the semiconductor substrate 12x. Here, the first low concentration region 46a, the first medium concentration region 44a, and the first high concentration region 42a are divided into three regions by injecting the p type impurity a plurality of times while changing the dose amount of the p type impurity and the irradiation energy. Forming regions of layers. At this time, the first high-concentration region 42a, the first medium-concentration region 44a, and the first low-concentration region 46a are formed in this order so that the p-type impurity concentration decreases. Further, the first high-concentration region 42a is formed so as to have a width in the x direction wider than that of the first medium-concentration region 44a and the first low-concentration region 46a. The first low concentration region 46a is formed so that the p-type impurity concentration is lower than that of the second high concentration region 42b. As a result, the connection area 38 is formed.

  Next, as shown in FIG. 10, a mask 88 having an opening 88a is formed on the upper surface of the semiconductor substrate 12x and the upper surface of the buried oxide film 86. The opening 88a is provided in the upper part in the range from the position of the first side surface 23a of the trench 22 to be formed to the trench 22a in the x direction. The mask 88 is made of, for example, silicon oxide. Then, the trench 22b is formed by etching the upper surface of the semiconductor substrate 12x in the opening 88a. The trench 22a and the trench 22b become the trench 22. After that, the mask 88 and the buried oxide film 86 are removed, and a bottom insulating film 24a is formed on the bottom surface of the trench 22, as shown in FIG. Next, the side surface insulating film 24b is formed so as to cover the side surface of the trench 22 above the bottom insulating film 24a. Next, the gate electrode 26 is formed inside the trench 22 after the bottom insulating film 24a and the side surface insulating film 24b are formed. The gate electrode 26 is formed such that the lower end of the gate electrode 26 is located below the body region 32 in the cross section where the connection region 38 is not provided.

  After that, the interlayer insulating film 28, the upper electrode 70, and the lower electrode 72 are formed by a conventionally known method to complete the MOSFET 10 of FIGS.

  In the above-described embodiment, the lateral side surface 23 of the trench 22 below the body region 32 is formed by the two side surfaces of the first side surface 23a and the second side surface 23b connected to each other by the step portion 40. Was configured. However, the lateral side surface 23 of the trench 22 below the body region 32 in the lateral direction may be composed of more than two steps. For example, as shown in FIG. 12, the lateral side surface 23 of the trench 22 below the body region 32 further has a third lateral surface 23c connected to the second lateral surface 23b by the step portion 41. Good. In this case, the p-type impurity concentration of the connection region 38 that is in contact with the trench 22 on the third side surface 23c can be distributed so as to gradually decrease from the upper side to the lower side. For example, as shown in FIG. 12, the connection region 38 in the range in contact with the trench 22 on the third side face 23c is connected to the lower end of the second low concentration region 46b and the step portion 41, and the third high concentration region 42c. It may be configured to have a third medium concentration region 44c connected to the third high concentration region 42c and a third low concentration region 46c connected to the third medium concentration region 44c and the bottom region 36. In this case, the third high concentration region 42c may be formed to have a higher p-type impurity concentration than the second low concentration region 46b.

  Further, in the above-described embodiment, the connection region 38 in the range in contact with each of the first side face 23a and the second side face 23b is composed of the three layers of the high concentration region 42, the medium concentration region 44 and the low concentration region 46. However, the connection region 38 may be composed of more than three layers. That is, if the p-type impurity concentration in the connection region 38 is distributed so as to decrease from the body region 32 side toward the bottom region 36 side, the connection region 38 is composed of more than three layers. May be. Further, the p-type impurity concentration in the connection region 38 in a range in contact with each of the first side face 23a and the second side face 23b is configured to gradually decrease from the body region 32 side toward the bottom region 36 side. Good.

  Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings achieves a plurality of purposes at the same time, and achieving the one purpose among them has technical utility.

10: MOSFET, 12: semiconductor substrate, 22: trench, 23: side surface, 23a: first side surface, 23b: second side surface, 23c: third side surface, 24: gate insulating film, 26: gate electrode, 28: interlayer insulation Film, 30: source region, 32: body region, 34: drift region, 35: drain region, 36: bottom region, 38: connection region, 40: step portion, 42: high concentration region, 44: medium concentration region, 46 : Low concentration region, 70: upper electrode, 72: lower electrode

Claims (1)

A switching element,
A semiconductor substrate,
A trench provided on the upper surface of the semiconductor substrate,
A gate insulating film disposed in the trench,
A gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film,
Is equipped with
The semiconductor substrate is
A p-type body region in contact with the gate insulating film,
An n-type drift region below the body region and in contact with the gate insulating film,
A p-type bottom region in contact with the gate insulating film on the bottom surface of the trench,
A p-type connection region that is in contact with the gate insulating film on the side surface of the trench and connects the body region and the bottom region,
Has
The side surface of the trench has a step portion below the body region,
On the lower side of the step portion, the width of the trench is narrower than on the upper side of the step portion,
The side surface of the trench has a first side surface located above the step portion and a second side surface located below the step portion,
The p-type impurity concentration of the connection region in contact with the gate insulating film on the first side surface is distributed so as to decrease from the upper side to the lower side,
The p-type impurity concentration of the connection region in contact with the gate insulating film on the second side surface is distributed so as to decrease from the upper side to the lower side,
The p-type impurity concentration at the upper end of the connection region in contact with the gate insulating film on the second side surface is higher than the p-type impurity concentration at the lower end of the connection region in contact with the gate insulating film on the first side surface. high,
Switching element.

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