JP2020047726A - Semiconductor device - Google Patents

Abstract

To provide a technique capable of reducing switching loss of a semiconductor device stably.SOLUTION: A semiconductor device includes a semiconductor substrate, a trench, a gate insulation film covering the inside of the trench, a first gate electrode placed on the bottom of the trench, an electrode insulation film placed on the top face of the first gate electrode, and a second gate electrode placed on the top face of the electrode insulation film, and insulated from the first gate electrode by the electrode insulation film. The semiconductor substrate has a source region facing the second gate electrode, a body region facing the second gate electrode on the underside of the source region, a drift region facing the second gate electrode on the underside of the body region, and separated from the source region by the body region, a bottom region in contact with the gate insulation film on the bottom face of the trench, and a side part region facing the first gate electrode between the body region and the bottom region.SELECTED DRAWING: Figure 2

Description

  The technology disclosed in this specification relates to a semiconductor device.

  Patent Literature 1 discloses a semiconductor device including a semiconductor substrate having a trench provided on an upper surface. In this semiconductor device, a gate insulating film covering an inner surface of the trench and a gate electrode insulated from the semiconductor substrate by the gate insulating film are arranged in the trench. The semiconductor substrate has an n-type source region, a p-type body region, and an n-type drift region. The source region is in contact with the gate insulating film. The body region is in contact with the gate insulating film below the source region. The drift region is in contact with the gate insulating film below the body region. Further, the semiconductor substrate has a p-type bottom region in contact with the gate insulating film on the bottom surface of the trench, and a p-type side region in contact with the gate insulating film on the side surface of the trench. The side region connects the body region and the bottom region. The drift region is in contact with the gate insulating film in a range where the side region does not exist.

  When the semiconductor device is turned off, holes are discharged from the bottom region to the body region via the side region. Then, a depletion layer extends from the bottom region into the drift region. The concentration of the electric field on the gate insulating film at the bottom of the trench is suppressed by the depletion layer.

  When the semiconductor device is turned on, a channel is formed in the body region, and the depletion layer that has spread in the drift region contracts, so that the semiconductor device is turned on. At this time, holes are supplied from the body region to the bottom region via the side regions. As a result, the depletion layer extending from the bottom region to the drift region contracts toward the bottom region. Therefore, when the semiconductor device is turned on, the resistance of the drift region decreases in a short time.

JP-A-2015-118966

  In this type of semiconductor device, a side region is formed by implanting an impurity into a side surface of a trench. Therefore, for example, when a manufacturing error occurs in the angle of the side surface of the trench, sufficient impurities cannot be implanted into the side region, and the side region is not connected to the bottom region, A side region having an impurity concentration lower than the concentration may be formed. In such a semiconductor device, since the resistance in the side region is high, holes are not easily discharged from the bottom region to the body region when the semiconductor device is turned off. Therefore, switching loss increases. As described above, the structure of the conventional semiconductor device has a problem that the variation in switching loss is large. This specification provides a technique capable of stably reducing switching loss of a semiconductor device.

  The semiconductor device disclosed in this specification includes a semiconductor substrate, a trench, a gate insulating film, a first gate electrode, an electrode insulating film, and a second gate electrode. The trench is provided on an upper surface of the semiconductor substrate. The gate insulating film covers an inner surface of the trench. The first gate electrode is disposed at a bottom of the trench, and is insulated from the semiconductor substrate by the gate insulating film. The electrode insulating film is disposed on an upper surface of the first gate electrode. The second gate electrode is disposed on the upper surface of the electrode insulating film, is insulated from the first gate electrode by the electrode insulating film, and is insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has a source region, a body region, a drift region, a bottom region, and a side region. The source region is an n-type region exposed on the upper surface of the semiconductor substrate and facing the second gate electrode via the gate insulating film. The body region is a p-type region facing the second gate electrode via the gate insulating film below the source region. The drift region is an n-type region facing the second gate electrode below the body region via the gate insulating film and separated from the source region by the body region. The bottom region is a p-type region that is in contact with the gate insulating film on the bottom surface of the trench and is in contact with the drift region. The side region is a p-type region facing the first gate electrode via the gate insulating film between the body region and the bottom region.

  To turn off the semiconductor device, an off potential (that is, a potential lower than the gate threshold) is applied to the second gate electrode. At this time, a negative potential (a lower potential than the source region and the body region) is applied to the first gate electrode. Since the side region faces the first gate electrode via the gate insulating film, when a negative potential is applied to the first gate electrode, holes are drawn into the side region and the periphery thereof. Then, the side region has low resistance, and holes are easily discharged from the bottom region to the body region. Further, even when the side region is not connected to the bottom region, an inversion layer is formed around the side region by the holes drawn around the side region, and the side region is defined as the bottom region by the inversion layer. Connected. Therefore, holes can be discharged from the bottom region to the body region. Therefore, this semiconductor device has a small switching loss.

FIG. 2 is a plan view of the MOSFET 10. FIG. 2 is a longitudinal sectional view taken along line II-II in FIG. 1. FIG. 3 is a vertical sectional view taken along line III-III in FIG. 1. FIG. 4 is a vertical sectional view taken along line IV-IV in FIG. 1. FIG. 3 is a longitudinal sectional view showing an example of a MOSFET in which the side region 38 is not connected to the bottom region 36 (corresponding to FIG. 2). FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 4 is a diagram for explaining a manufacturing process of the MOSFET 10. FIG. 5 is a longitudinal sectional view of a MOSFET according to a modification (corresponding to FIG. 4).

  1 to 4 show a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 10 of the embodiment. The MOSFET 10 includes a semiconductor substrate 12, an electrode, an insulating layer, and the like. In FIG. 1, illustration of an interlayer insulating film 29 and an upper electrode 70, which will be described later, is omitted for the sake of clarity. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as an x direction, a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as a y direction, and a thickness direction of the semiconductor substrate 12 is referred to as a z direction. The semiconductor substrate 12 is made of, for example, SiC (silicon carbide). However, the semiconductor substrate 12 may be made of another semiconductor material such as Si (silicon).

  As shown in FIGS. 1 to 3, a plurality of trenches 22 are provided on the upper surface 12 a of the semiconductor substrate 12. In FIG. 1, the trench 22 is indicated by a broken line. Each trench 22 extends linearly and long in the y direction. The plurality of trenches 22 are arranged at intervals in the x direction. As shown in FIGS. 2 to 4, the inner surface of each trench 22 is covered with a gate insulating film 24.

  As shown in FIGS. 2 and 3, a first gate electrode 26 is disposed at the bottom in each trench 22. The first gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. As shown in FIG. 4, the first gate electrode 26 includes a base 26 a provided along the bottom of the trench 22, a bent part 26 b extending upward from the base 26 a at one end in the longitudinal direction of the trench 22, A lead portion 26c extends from the upper end of the bent portion 26b to the upper surface 12a of the semiconductor substrate 12 via the surface insulating film 40. Although not shown, the lead portion 26c of each first gate electrode 26 is connected to a power supply by a wiring.

  As shown in FIGS. 2 to 4, an electrode insulating film 27 is disposed on the upper surface of the first gate electrode 26. The electrode insulating film 27 is disposed along the base 26a and the bent portion 26b of the first gate electrode 26.

  On the upper surface of the electrode insulating film 27, a second gate electrode 28 is arranged. The second gate electrode 28 is insulated from the first gate electrode 26 by the electrode insulating film 27. The second gate electrode 28 is insulated from the semiconductor substrate 12 by the gate insulating film 24. As shown in FIG. 4, the second gate electrode 28 includes a base 28a provided along the upper surface of the electrode insulating film 27, and a bent portion 28b bent upward from the base 28a at the other longitudinal end of the trench 22. And a lead portion 28c extending from the bent portion 28b to the upper surface 12a of the semiconductor substrate 12 via the surface insulating film 40. Although not shown, the lead portion 28c of each second gate electrode 28 is connected to a power source different from the power source connected to the first gate electrode 26 by wiring. That is, the potentials of the first gate electrode 26 and the second gate electrode 28 are independently controlled. On the second gate electrode 28, an interlayer insulating film 29 is arranged.

  An upper electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. As shown in FIGS. 2 and 3, the upper electrode 70 is in contact with the upper surface 12 a of the semiconductor substrate 12 at a portion where the interlayer insulating film 29 is not provided. The upper electrode 70 is insulated from the first gate electrode 26 and the second gate electrode 28 by the interlayer insulating film 29. The lower electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with the lower surface 12b of the semiconductor substrate 12.

  As shown in FIGS. 2 to 4, a plurality of source regions 30, a body region 32, a drift region 34, a drain region 35, a plurality of bottom regions 36, and a plurality of side regions 38 are provided inside the semiconductor substrate 12. ing.

  Each source region 30 is an n-type region. Each source region 30 is arranged at a position exposed on the upper surface 12 a of the semiconductor substrate 12. Each source region 30 is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the gate insulating film 24 on the side surface of the trench 22. Each source region 30 faces the second gate electrode 28 via the gate insulating film 24 at the upper end of the trench 22.

  Body region 32 is a p-type region. The body region 32 is in contact with each source region 30. The body region 32 extends from the area between the two source regions 30 to the lower side of each source region 30. The body region 32 has a high concentration region 32a and a low concentration region 32b. The high concentration region 32a has a higher p-type impurity concentration than the low concentration region 32b. The high concentration region 32a is arranged in a range between the two source regions 30. The high concentration region 32a is in ohmic contact with the upper electrode 70. The low concentration region 32b is in contact with the gate insulating film 24 on the side surface of the trench 22. That is, the low-concentration region 32b is in contact with the gate insulating film 24 below the source region 30. The low concentration region 32b faces the second gate electrode 28 via the gate insulating film 24.

  Drift region 34 is an n-type region. Drift region 34 is arranged below body region 32, and is separated from source region 30 by body region 32. As shown in FIG. 3, drift region 34 is in contact with gate insulating film 24 on the side surface of trench 22. That is, drift region 34 is in contact with gate insulating film 24 below body region 32. The upper end portion of the drift region 34 faces the second gate electrode 28 via the gate insulating film 24. That is, the interface between the drift region 34 and the body region 32 is located above the interface between the electrode insulating film 27 and the second gate electrode 28. Drift region 34 is distributed from a position in contact with body region 32 to a position below the lower end of each trench 22.

  The drain region 35 is an n-type region. Drain region 35 has a higher n-type impurity concentration than drift region 34. The drain region 35 is disposed below the drift region 34. The drain region 35 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72.

  Each bottom region 36 is a p-type region. Each bottom region 36 is arranged in a range exposed on the bottom surface of the corresponding trench 22. Each bottom region 36 is in contact with gate insulating film 24 at the bottom of corresponding trench 22. As shown in FIG. 4, each bottom region 36 extends long in the y-direction along the bottom surface of the corresponding trench 22. Each bottom region 36 is in contact with gate insulating film 24 over the entire bottom surface of corresponding trench 22. As shown in FIGS. 2 and 3, the periphery of each bottom region 36 is surrounded by the drift region 34. Except where a side region 38 described later is formed, each bottom region 36 is separated from the body region 32 by a drift region 34.

  Each side region 38 is a p-type region. As shown in FIG. 1, each side region 38 is provided along the short side surface of the trench 22 (that is, the side surface located at the end in the short direction and extending along the y direction). Have been. As shown in FIG. 2, the side region 38 extends downward from the body region 32 along the lateral side surface of the trench 22. A plurality of side regions 38 are arranged on the short side surfaces of the trench 22. The side region 38 is also provided on the longitudinal side surface of the trench 22 (that is, the side surface located at the longitudinal end and extending along the x direction). The lower end of each side region 38 is connected to the bottom region 36. That is, the body region 32 and the bottom region 36 are connected by the side region 38. Each side region 38 faces the first gate electrode 26 via the gate insulating film 24 between the body region 32 and the bottom region 36.

  Next, the operation of the MOSFET 10 will be described. When the MOSFET 10 is used, the MOSFET 10, a load (for example, a motor), and a power supply are connected in series. A power supply voltage (about 800 V in this embodiment) is applied to a series circuit of the MOSFET 10 and the load. A power supply voltage is applied such that the lower electrode 72 side of the MOSFET 10 has a higher potential than the upper electrode 70 side. When an on-potential (potential equal to or higher than the gate threshold) is applied to the second gate electrode 28, a channel is formed in the body region 32 (low-concentration region 32b) in a range in contact with the gate insulating film 24, and the MOSFET 10 turns on. When an off potential (the same potential as the upper electrode 70) is applied to the second gate electrode 28, the channel disappears and the MOSFET 10 is turned off. Hereinafter, the operation at the time of turning off and turning on the MOSFET 10 will be described in detail.

  When the MOSFET 10 is turned off, the potential of the second gate electrode 28 is reduced from the ON potential to the OFF potential. Then, the channel disappears and the potential of the lower electrode 72 increases. The potential of the lower electrode 72 rises to a potential higher than the upper electrode 70 by the power supply voltage (that is, about 800 V). During the process of increasing the potential of the lower electrode 72, the potential of the bottom region 36 slightly increases due to capacitive coupling between the bottom region 36 and the lower electrode 72. Then, a hole flows from the bottom region 36 to the upper electrode 70 via the side region 38 and the body region 32. Therefore, the rise in the potential of the bottom region 36 is suppressed, and the potential of the bottom region 36 is maintained at a potential slightly higher than the potential of the upper electrode 70.

  Further, as the potential of the lower electrode 72 increases, the potential of the drift region 34 also increases. When the potential of the drift region 34 rises, a potential difference occurs between the body region 32 and the drift region 34. Therefore, a reverse voltage is applied to the pn junction at the interface between the body region 32 and the drift region 34. Therefore, a depletion layer spreads from body region 32 to drift region 34. When the potential of the drift region 34 rises, a potential difference occurs between the drift region 34 and the bottom region 36 and the side region 38. Therefore, a reverse voltage is applied to the pn junction at the interface between the drift region 34 and the bottom region 36 and the side region 38. Therefore, the depletion layer spreads from the bottom region 36 and the side region 38 to the drift region 34.

  When the MOSFET 10 is turned off, the potential of the second gate electrode 28 is reduced to the off potential, and a negative potential (specifically, a potential lower than that of the upper electrode 70) is applied to the first gate electrode 26. Since the side region 38 faces the first gate electrode 26 via the gate insulating film 24, when a negative potential is applied to the first gate electrode 26, holes are drawn into the side region 38 and the periphery thereof. Then, the side region 38 has a low resistance, and holes are easily discharged from the bottom region 36 to the upper electrode 70 via the body region 32. Therefore, when the MOSFET 10 is turned off, an increase in the potential of the bottom region 36 can be suppressed, and the depletion layer quickly extends from the bottom region 36 to the drift region 34 therearound. Therefore, in the MOSFET 10, current is quickly cut off at the time of turn-off, and switching loss is small.

  Further, the side region 38 may not be connected to the bottom region 36 as shown in FIG. 5 due to a manufacturing error or the like. Even in this case, by applying a negative potential to the first gate electrode 26, an inversion layer is formed around the side region 38 by holes drawn around the side region 38, and the formed inversion layer is formed. The side region 38 and the bottom region 36 are connected. Therefore, holes can be discharged from the bottom region 36 to the upper electrode 70 via the inversion layer. Further, due to a manufacturing error, the p-type impurity concentration may be reduced in a part of the side region 38 and the resistance of the side region 38 may be increased. Even in this case, by applying a negative potential to the first gate electrode 26, holes are drawn to the side region 38, and the resistance of the side region 38 is reduced. Therefore, holes can be discharged from the bottom region 36 to the upper electrode 70. Thus, according to the MOSFET 10, even when the side region 38 is interrupted or when the side region 38 has high resistance, holes can be preferably discharged from the bottom region 36 to the upper electrode 70, Switching loss can be suppressed stably.

  When the MOSFET 10 is turned on, the potential of the second gate electrode 28 is raised from the off potential to the on potential. Then, electrons are attracted to the body region 32 in a range in contact with the gate insulating film 24 on the side surface of the trench 22. Thereby, body region 32 in this range is inverted from p-type to n-type, and a channel is formed. The source region 30 and the drift region 34 are connected by the channel. As a result, the potentials of the drift region 34 and the lower electrode 72 decrease. When the potential of the drift region 34 decreases, the reverse voltage applied to the pn junction at the interface between the body region 32 and the drift region 34 decreases. Therefore, the depletion layer extending from the body region 32 to the drift region 34 contracts toward the body region 32 and disappears. As a result, electrons flow from the upper electrode 70 to the lower electrode 72 via the source region 30, the channel, and the drift region 34. That is, the MOSFET 10 is turned on. In the process of lowering the potential of the drift region 34, holes flow from the upper electrode 70 to the bottom region 36 via the body region 32 and the side region 38. When holes are supplied to the bottom region 36, the depletion layer extending from the bottom region 36 to the drift region 34 contracts toward the bottom region 36.

  When the MOSFET 10 is turned on, the potential of the second gate electrode 28 is raised to the ON potential, and a positive potential (more specifically, a potential higher than the upper electrode 70) is applied to the first gate electrode 26. Since the bottom region 36 faces the first gate electrode 26 via the gate insulating film 24, when a positive potential is applied to the first gate electrode 26, the potential of the bottom region 36 increases. Therefore, the depletion layer extending from the bottom region 36 to the drift region 34 contracts quickly. Therefore, the resistance of the drift region 34 decreases quickly, and electrons easily flow from the upper electrode 70 to the lower electrode 72. For this reason, in the MOSFET 10, the loss generated in the drift region 34 is reduced.

  As described above, in the MOSFET 10 of the present embodiment, the potential of the second gate electrode 28 facing the body region 32 via the gate insulating film 24 is controlled, and the side region 38 via the gate insulating film 24. By controlling the potential of the first gate electrode 26 opposing to the switching power supply, the switching loss generated in the MOSFET 10 can be suitably reduced.

  Next, a method for manufacturing the MOSFET 10 will be described with reference to FIGS. 6 to 12 are cross-sectional views of the semiconductor substrate in the process of manufacturing the MOSFET 10. In FIGS. 6 to 12, figures with an A attached to the figure numbers (FIGS. 6A, 7A, etc.) show cross sections (cross sections corresponding to FIG. 2) along the short direction of the trench 22. Figures with B appended to the figure numbers (FIGS. 6B, 7B, etc.) show cross sections along the longitudinal direction of the trench 22 (cross sections corresponding to FIG. 4).

  First, as shown in FIGS. 6A and 6B, an n-type drift region 34, a p-type low-concentration region 32b disposed on the drift region 34, a source region 30 disposed on the low-concentration region 32b, and a high-concentration region 32b. A semiconductor substrate 12x having a concentration region 32a is prepared. The source region 30, the high concentration region 32a, and the low concentration region 32b can be formed by a conventionally known method such as ion implantation or epitaxial growth.

  Next, as shown in FIGS. 7A and 7B, the upper surface 12a of the semiconductor substrate 12x is partially etched to form the trench 22 that reaches the drift region 34 through the source region 30 and the low-concentration region 32b. Thereafter, as shown in FIGS. 7A and 7B, an oxide film 60 covering the upper surface 12a of the semiconductor substrate 12x and the inner surface of the trench 22 is formed by a CVD (chemical vapor deposition) method.

  Next, a p-type impurity is implanted into the bottom surface of the trench 22, the short side surface of the trench 22, and the long side surface of the trench 22. The p-type impurity penetrates the oxide film 60 and is implanted into the semiconductor substrate 12x. The implantation of the p-type impurity is performed by appropriately tilting the irradiation direction of the p-type impurity with respect to the depth direction of the trench 22. After that, the semiconductor substrate 12x is heat-treated. Then, the p-type impurities implanted into the semiconductor substrate 12x are activated. This forms a bottom region 36 and a side region 38 as shown in FIGS. 8A and 8B.

  Next, a metal layer is deposited on the upper surface 12a of the semiconductor substrate 12x and in the trench 22 by the CVD method, and thereafter, the metal layer is selectively etched. Here, as shown in FIGS. 9A and 9B, the metal layer is left at the bottom of the trench 22. Further, as shown in FIG. 9B, at one end in the longitudinal direction of the trench 22 (the end in the negative y-axis direction), the metal layer is left over from the bottom to the upper end of the trench 22 and the upper surface 12a of the semiconductor substrate 12x. Next, the metal layer is etched. The metal layer remaining at the bottom of the trench 22 becomes the base 26a of the first gate electrode 26, and the metal layer remaining on the side surface at one end in the longitudinal direction of the trench 22 becomes the bent portion 26b of the first gate electrode 26. The metal layer remaining on the upper surface 12a becomes the lead portion 26c of the first gate electrode 26.

  Next, an oxide film layer is deposited by a CVD method on the upper surface 12a of the semiconductor substrate 12x, the upper surface of the lead portion 26c of the first gate electrode 26, and in the trench 22, and thereafter, the oxide film layer is selectively etched. Here, as shown in FIGS. 10A and 10B, the oxide film layer 27a is left in the trench 22 so as to cover the base 26a of the first gate electrode 26. At this time, the oxide film layer 27a is etched to such a depth that the upper surface of the oxide film layer 27a covering the base 26a is located below the interface between the body region 32 and the drift region 34. Further, as shown in FIG. 10B, an oxide film layer is left at one end in the longitudinal direction of the trench 22 so as to cover the bent portion 26b and the lead-out portion 26c of the first gate electrode 26.

  Next, a metal layer is deposited on the upper surface 12a of the semiconductor substrate 12x, the upper surface of the oxide film layer 27a, and the inside of the trench 22 by a CVD method, and thereafter, the metal layer is selectively etched. Here, as shown in FIGS. 11A and 11B, the metal layer is left so that the metal layer is filled up to the upper end of the trench 22. As shown in FIG. 11B, at the other end in the longitudinal direction of the trench 22 (the end in the positive y-axis direction), the upper surface of the oxide film layer 27a extends from the upper end of the trench 22 to the upper surface 12a of the semiconductor substrate 12x. The metal layer is etched so that the metal layer remains. The metal layer remaining in the trench 22 becomes the base portion 28a of the second gate electrode 28, and the metal layer remaining on the other end in the longitudinal direction of the trench 22 becomes the bent portion 28b of the second gate electrode 28. The metal layer remaining on the upper surface 12a becomes the lead portion 28c of the second gate electrode 28.

  Next, as shown in FIG. 12A, the oxide film 60 in a range covering the source region 30 and the high concentration region 32a is removed by etching. Thereby, the source region 30 and the high concentration region 32a are exposed. In addition, as shown in FIG. 12B, the oxide film layer 27a in a range covering the lead portion 26c of the first gate electrode 26 is removed by etching. As a result, the lead portion 26c of the first gate electrode 26 is exposed. The oxide film 60 remaining on the upper surface 12a of the semiconductor substrate 12x (see FIG. 12B) is the surface insulating film 40, and the oxide film 60 remaining on the inner surface of the trench 22 is the gate insulating film 24.

  After that, the interlayer insulating film 29, the upper electrode 70, the drain region 35, and the lower electrode 72 are formed by a conventionally known method. Thus, the MOSFET 10 shown in FIGS. 1 to 4 is completed.

  In the above-described embodiment, the extension 28c of the second gate electrode 28 is located at the end opposite to the extension 26c of the first gate electrode 26 in the longitudinal direction of the trench 22 (the end in the positive y-axis direction). Had been drawn from. However, in the modified example, as shown in FIG. 13, the leading portion 128 c of the second gate electrode 128 is on the same side as the leading portion 26 c of the first gate electrode 26 in the longitudinal direction of the trench 22 (y-axis negative direction). End).

  In the above-described embodiment, a positive potential is applied to the first gate electrode 26 when the MOSFET 10 is turned on. However, a negative potential may be applied to the first gate electrode 26 at all times. Even if the potential of the first gate electrode 26 is controlled in this manner, the MOSFET 10 can operate.

  As described above, specific examples of the present invention have been described in detail, but these are merely examples, and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology illustrated in the present specification or the drawings simultaneously achieves a plurality of objects, and has technical utility by achieving one of the objects.

10: MOSFET, 12: semiconductor substrate, 12a: upper surface, 12b: lower surface, 22: trench, 24: gate insulating film, 26: first gate electrode, 26a: base, 26b: bent portion, 26c: lead portion, 27: Electrode insulating film, 28: second gate electrode, 28a: base, 28b: bent portion, 28c: lead portion, 29: interlayer insulating film, 30: source region, 32: body region, 32a: high concentration region, 32b: low Concentration region, 34: drift region, 35: drain region, 36: bottom region, 38: side region, 40: surface insulating film, 70: upper electrode, 72: lower electrode

Claims (1)

A semiconductor substrate;
A trench provided on the upper surface of the semiconductor substrate,
A gate insulating film covering the inner surface of the trench;
A first gate electrode disposed at the bottom of the trench and insulated from the semiconductor substrate by the gate insulating film;
An electrode insulating film disposed on an upper surface of the first gate electrode;
A second gate electrode disposed on the upper surface of the electrode insulating film, insulated from the first gate electrode by the electrode insulating film, and insulated from the semiconductor substrate by the gate insulating film;
With
The semiconductor substrate,
An n-type source region exposed on the upper surface of the semiconductor substrate and facing the second gate electrode via the gate insulating film;
A p-type body region facing the second gate electrode via the gate insulating film below the source region;
An n-type drift region opposed to the second gate electrode via the gate insulating film below the body region and separated from the source region by the body region;
A p-type bottom region in contact with the gate insulating film at the bottom surface of the trench, and in contact with the drift region;
A p-type side region facing the first gate electrode via the gate insulating film between the body region and the bottom region;
A semiconductor device comprising:

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