JP2020126932A - Trench gate type semiconductor device - Google Patents

Abstract

To provide a technique capable of reducing channel resistance in a trench gate type semiconductor device.SOLUTION: A semiconductor substrate has an n-type first semiconductor region, a p-type body region, and an n-type second semiconductor region which are arranged between a first trench and a second trench. A body region is arranged below the first semiconductor region and extends from a position where it is in contact with a gate insulating film in the first trench to a position where it is in contact with a gate insulating film in the second trench. The second semiconductor region is arranged below the body region. The interval between the first trench and the second trench is 100 nm or less. The body region has a first high-concentration region provided in a range where it is in contact with the gate insulating film in the first trench, a second high-concentration region in a range where it is in contact with the gate insulating film in the second trench, and a low-concentration region which is arranged between the first high-concentration region and the second high-concentration region, and has a p-type impurity concentration lower than those of the first high-concentration region and the second high-concentration region.SELECTED DRAWING: Figure 1

Description

The technology disclosed in the present specification relates to a trench gate type semiconductor device.

Patent Document 1 discloses a trench gate type semiconductor device. This semiconductor device has a semiconductor substrate having a trench provided on the upper surface thereof, and a gate insulating film and a gate electrode arranged in the trench. The gate electrode is insulated from the semiconductor substrate by the gate insulating film. In this semiconductor device, the semiconductor substrate has a first semiconductor region, a body region, and a second semiconductor region. The first semiconductor region is n-type and is in contact with the gate insulating film. The body region is p-type and is in contact with the gate insulating film below the first semiconductor region. The second semiconductor region is n-type, is in contact with the gate insulating film below the body region, and is separated from the first semiconductor region by the body region.

When the semiconductor device of Patent Document 1 is turned on, the potential of the gate electrode is set higher than the gate threshold value. Then, a channel is formed in the body region near the gate insulating film. Electrons flow from the first semiconductor region to the second semiconductor region via the channel, so that the semiconductor device is turned on.

Japanese Unexamined Patent Application Publication No. 2015-159272

In the semiconductor device of Patent Document 1, the channel is formed only near the gate insulating film. Therefore, the electrons flow near the interface between the body region and the gate insulating film. When the electrons flow near the interface between the body region and the gate insulating film, the electrons are scattered. For example, electrons are scattered by the charges trapped in the interface state between the gate insulating film and the body region. In addition, electrons are scattered by the roughness of the interface between the body region and the gate insulating film. Due to the scattering of electrons in this way, there is a problem that the mobility of the electrons flowing through the channel decreases and the channel resistance increases. The present specification provides a technique capable of reducing channel resistance in a trench gate type semiconductor device.

In the trench gate type semiconductor device, by narrowing the interval between two adjacent trenches, when the semiconductor device is turned on, a channel can be formed in almost the entire body region located between the trenches. That is, by narrowing the width of the body region, almost the entire body region located between the trenches can function as a channel. In the present specification, a channel formed in almost the entire body region located between the trenches is referred to as a bulk channel. In the bulk channel, electrons flow even at a position away from the gate insulating film. Therefore, the electrons are less likely to be affected by the scattering caused by the interface between the gate insulating film and the body region. Therefore, the bulk channel can improve electron mobility. However, in the bulk channel type trench gate type semiconductor device, it is necessary to make the concentration of the body region relatively low. Therefore, there is a problem that the gate threshold value is low. In view of the above circumstances, the trench gate type semiconductor device disclosed in this specification has the following configuration.

The trench gate type semiconductor device disclosed in this specification includes a semiconductor substrate, a first trench, a second trench, a gate insulating film, and a gate electrode. The first trench is provided on the upper surface of the semiconductor substrate. The second trench is provided on the upper surface of the semiconductor substrate at a distance from the first trench. The gate insulating film covers the inner surface of the first trench and the inner surface of the second trench. The gate electrode is arranged in the first trench and the second trench, and is insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has a first semiconductor region, a body region and a second semiconductor region. The first semiconductor region is an n-type region arranged between the first trench and the second trench. The body region is disposed between the first trench and the second trench, is disposed below the first semiconductor region, and extends from a position in contact with the gate insulating film in the first trench. The p-type region extends to a position in contact with the gate insulating film in the second trench. The second semiconductor region is arranged between the first trench and the second trench, is arranged below the body region, and is located from a position in contact with the gate insulating film in the first trench. An n-type region that extends to a position in contact with the gate insulating film in the second trench and is separated from the first semiconductor region by the body region. The distance between the first trench and the second trench is 100 nm or less. A first high-concentration region provided in a range where the body region contacts the gate insulating film in the first trench, and a second high-concentration region provided in a range contacting the gate insulating film in the second trench. A region and a low concentration region which is arranged between the first high concentration region and the second high concentration region and has a p-type impurity concentration lower than those of the first high concentration region and the second high concentration region. ..

In the above trench gate type semiconductor device, the body region extends from a position in contact with the gate insulating film in the first trench to a position in contact with the gate insulating film in the second trench. Further, the distance between the first trench and the second trench is 100 nm or less, which is sufficiently narrow to form a bulk channel. Therefore, when the semiconductor device is turned on, a bulk channel is formed in almost the entire body region.

Further, in the above trench gate type semiconductor device, the body region includes the first high concentration region and the second high concentration region, which are provided in a range in contact with the gate insulating film, and the first high concentration region and the second high concentration region. It has a low-concentration region disposed in between. By providing the first high-concentration region and the second high-concentration region in the range in contact with the gate insulating film, it becomes difficult for the inversion layer to spread in the body region. Therefore, the gate threshold value can be made higher than in the conventional case. Further, when the bulk channel is formed in the body region, electrons can flow in the low concentration region where the p-type impurity concentration is low. In the low-concentration region where the p-type impurity concentration is low, electrons are less likely to be scattered by fixed charges (p-type impurities), so that the mobility of electrons is high. Therefore, low channel resistance can be realized. Thus, in this trench gate type semiconductor device, a high gate threshold and a low channel resistance can be realized.

Sectional drawing of the semiconductor device 10 which concerns on an Example. The figure which shows the simulation result of the gate threshold value when changing the width of a high concentration area|region. The figure which shows the simulation result of ON resistance when changing the width of a high concentration area|region. 6A to 6D are views for explaining the manufacturing process of the semiconductor device 10 (Example 1). 6A to 6D are views for explaining the manufacturing process of the semiconductor device 10 (Example 1). 6A to 6D are views for explaining the manufacturing process of the semiconductor device 10 (Example 1). 6A to 6D are views for explaining the manufacturing process of the semiconductor device 10 (Example 1). 6A to 6D are views for explaining the manufacturing process of the semiconductor device 10 (Example 1). 6A and 6B are views for explaining the manufacturing process of the semiconductor device 10 (Example 2). 6A and 6B are views for explaining the manufacturing process of the semiconductor device 10 (Example 2). 6A to 6C are views for explaining the manufacturing process of the semiconductor device 10 (Example 3). 6A to 6C are views for explaining the manufacturing process of the semiconductor device 10 (Example 3).

The trench gate type semiconductor device 10 (hereinafter referred to as the semiconductor device 10) of the first embodiment shown in FIG. 1 is a MOSFET (metal-oxide-semiconductor field effect transistor). The semiconductor device 10 has a semiconductor substrate 12. In this embodiment, the semiconductor substrate 12 is made of silicon carbide (SiC). The material of the semiconductor substrate 12 is not limited to the above, and may be various semiconductor materials such as silicon (Si) and gallium nitride (GaN). Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 (left-right direction in FIG. 1) is referred to as the x direction, and a direction parallel to the upper surface 12a and orthogonal to the x direction (direction perpendicular to the paper surface of FIG. 1) Is called the y direction. As shown in FIG. 1, a plurality of trenches 22 are provided on the upper surface 12 a of the semiconductor substrate 12. Each trench 22 extends long in the y direction. The trenches 22 extend in parallel with each other at intervals in the x direction. The inner surface of each trench 22 is covered with a gate insulating film 24. A gate electrode 26 is arranged inside each trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of each gate electrode 26 is covered with an interlayer insulating film 28. Hereinafter, for convenience of description, the left trench 22 in FIG. 1 may be referred to as a first trench 22a, and the right trench 22 in FIG. 1 may be referred to as a second trench 22b. Although not shown, a plurality of trenches similar to the trench 22 are formed on the left side of the first trench 22a and the right side of the second trench 22b in FIG. In this embodiment, the distance between the trenches 22 is 100 nm or less. Specifically, as shown in FIG. 1, the distance W between the opposing side surfaces of two adjacent trenches 22 is 100 nm or less.

The upper electrode 70 is arranged on the upper surface 12 a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 at the portion where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is arranged on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in contact with substantially the entire lower surface 12b of the semiconductor substrate 12.

Inside the semiconductor substrate 12, a plurality of source regions 30, a body region 32, a drift region 34 and a drain region 35 are provided. Since the internal configuration of the semiconductor substrate 12 between the two adjacent trenches 22 is the same, the configuration located between the two trenches 22a and 22b shown in FIG. 1 will be described below.

The source region 30 is an n-type region. Each source region 30 is arranged at a position exposed on the upper surface 12 a of the semiconductor substrate 12, and is in ohmic contact with the upper electrode 70. The source region 30 includes a first source region 30a in contact with the gate insulating film 24 in the first trench 22a at the upper end of the first trench 22a, and a gate insulating film 24 in the second trench 22b at the upper end of the second trench 22b. Has a second source region 30b in contact with.

The body region 32 is a p-type region. The body region 32 is in contact with each source region 30. The body region 32 extends from the range between the first source region 30a and the second source region 30b to the lower side of each source region 30. The body region 32 has a contact region 32a and a main body region 32b. Contact region 32a has a higher p-type impurity concentration than main body region 32b. The contact region 32a is arranged in a range sandwiched between the first source region 30a and the second source region 30b. The contact region 32a is in ohmic contact with the upper electrode 70. The main body region 32b is arranged below the first source region 30a, the contact region 32a, and the second source region 30b. The main body region 32b extends from a position in contact with the gate insulating film 24 in the first trench 22a to a position in contact with the gate insulating film 24 in the second trench 22b. The main body region 32b has a first high-concentration region 33a, a second high-concentration region 33b, and a low-concentration region 33c.

The first high concentration region 33a is provided in a range in contact with the gate insulating film 24 of the first trench 22a. The first high concentration region 33a is in contact with the gate insulating film 24 in the first trench 22a below the first source region 30a. The second high concentration region 33b is provided in a range in contact with the gate insulating film 24 of the second trench 22b. The second high concentration region 33b is in contact with the gate insulating film 24 in the second trench 22b below the second source region 30b. The p-type impurity concentration of the second high-concentration region 33b is substantially equal to the p-type impurity concentration of the first high-concentration region 33a. The p-type impurity concentration of the first high concentration region 33a and the second high concentration region 33b is not particularly limited, but is, for example, 2×10 ¹⁸ cm ⁻³ . The low concentration region 33c is arranged between the first high concentration region 33a and the second high concentration region 33b. The low concentration region 33c is separated from the gate insulating film 24 in the first trench 22a by the first high concentration region 33a. The low concentration region 33c is separated from the gate insulating film 24 in the second trench 22b by the second high concentration region 33b. The low concentration region 33c is in contact with the contact region 32a. The low concentration region 33c is in contact with the first source region 30a and the second source region 30b. The low-concentration region 33c has a p-type impurity concentration lower than those of the first high-concentration region 33a and the second high-concentration region 33b. The p-type impurity concentration of the low-concentration region 33c is not particularly limited, but is, for example, 2×10 ¹⁶ cm ⁻³ . The width of the first high-concentration region 33a (distance between the gate insulating film 24 in the first trench 22a and the low-concentration region 33c) and the width of the second high-concentration region 33b (gate insulating film in the second trench 22b). The distance between 24 and the low concentration region 33c is not particularly limited, but is 10 nm, for example.

The drift region 34 is an n-type region. The drift region 34 is arranged below the main body region 32b. The drift region 34 is in contact with the first high concentration region 33a, the second high concentration region 33b, and the low concentration region 33c. The drift region 34 extends from a position in contact with the gate insulating film 24 in the first trench 22a to a position in contact with the gate insulating film 24 in the second trench 22b. The drift region 34 is separated from the source region 30 by the main body region 32b. The drift region 34 covers the bottom of the first trench 22a and the bottom of the second trench 22b.

The drain region 35 is an n-type region. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 is arranged below the drift region 34. The drain region 35 is exposed on the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72.

Next, the operation of the semiconductor device 10 will be described. When using the semiconductor device 10, the semiconductor device 10, a load (for example, a motor), and a power supply are connected in series. A power supply voltage is applied to the series circuit of the semiconductor device 10 and the load. The power supply voltage is applied so that the drain side (lower electrode 72) of the semiconductor device 10 has a higher potential than the source side (upper electrode 70). When the semiconductor device 10 is turned on, the potential of the gate electrode 26 is raised to a potential higher than the gate threshold. In the process of raising the potential of the gate electrode 26, first, the first high concentration region 33a and the second high concentration region 33b of the main body region 32b are inverted to n-type. In this embodiment, the distance W between the first trench 22a and the second trench 22b is 100 nm or less. That is, the width of the main body region 32b is 100 nm or less. Since the width of the main body region 32b is sufficiently narrow, when the potential of the gate electrode 26 is further increased, the inversion layer spreads from the first high concentration region 33a and the second high concentration region 33b to the low concentration region 33c, and the low concentration region is reduced. Substantially the entire area of 33c is inverted to the n-type. As a result, a channel (that is, a bulk channel) is formed in the entire main body region 32b between the first trench 22a and the second trench 22b. When the bulk channel is formed in the main body region 32b, the source region 30 and the drift region 34 are connected by the bulk channel. Therefore, electrons flow from the source region 30 to the drift region 34 via the bulk channel. As a result, the semiconductor device 10 is turned on. When the semiconductor device 10 is turned off, a potential lower than the gate threshold value is applied to the gate electrode 26. Then, the bulk channel formed in the main body region 32b disappears, and the semiconductor device 10 is turned off.

In the conventional semiconductor device in which the distance between the adjacent trenches is large, the channel is formed only in the area near the gate insulating film in the body region. Therefore, the electrons flow near the interface between the body region and the gate insulating film. At this time, the electrons are scattered by the charges trapped in the interface state between the gate insulating film and the body region and the roughness of the interface between the body region and the gate insulating film. As a result, the mobility of the electrons flowing in the channel is lowered and the channel resistance is increased.

On the other hand, in the present embodiment, as described above, the bulk channel is formed in the main body region 32b. In the bulk channel, electrons flow not only in the high-concentration regions 33a and 33b near the gate insulating film 24 but also in the low-concentration region 33c distant from the gate insulating film 24. In the low-concentration region 33c distant from the gate insulating film 24, electron scattering due to the interface between the gate insulating film 24 and the main body region 32b does not occur. Further, in the low concentration region 33c where the p-type impurity concentration is low, it is difficult for electrons to be scattered by fixed charges (p-type impurities). Thus, in the low-concentration region 33c, electrons are less likely to be scattered, so that the mobility of electrons is high. Therefore, in the semiconductor device 10 of this embodiment, a low channel resistance can be realized by forming the bulk channel.

In the high-concentration regions 33a and 33b located near the gate insulating film 24, electrons are scattered due to the interface between the gate insulating film 24 and the main body region 32b. Further, in the high-concentration regions 33a and 33b having a high p-type impurity concentration, electrons are easily scattered by fixed charges (p-type impurities). Thus, in the high-concentration regions 33a and 33b, electrons are likely to be scattered, so that the mobility of electrons is low. However, in the semiconductor device 10 of the present embodiment, electrons can flow in the low concentration region 33c having high mobility as described above. Therefore, the semiconductor device 10 has low on-resistance.

Further, in the semiconductor device 10 of the present embodiment, the first high concentration region 33a and the second high concentration region 33b are provided in the range in contact with the gate insulating film 24. Therefore, when increasing the potential of the gate electrode 26, it is difficult for the first high concentration region 33a and the second high concentration region 33b to invert to the n-type. Therefore, unless the potential of the gate electrode 26 is raised to some extent, the first high concentration region 33a and the second high concentration region 33b do not invert to the n-type. Then, after the first high-concentration region 33a and the second high-concentration region 33b are inverted to n-type, the low-concentration region 33c is inverted to n-type to form a bulk channel. Thus, the first high-concentration region 33a and the second high-concentration region 33b are provided in the range in contact with the gate insulating film 24, so that the potential of the gate electrode 26 required to form the bulk channel becomes high. .. Therefore, in this semiconductor device 10, the gate threshold can be made higher than in the conventional case. In the semiconductor device 10 of the present embodiment, a desired gate threshold value can be realized by appropriately adjusting the p-type impurity concentration of the first high concentration region 33a and the second high concentration region 33b.

FIG. 2 shows a result of simulating the gate threshold when the widths of the first high concentration region 33a and the second high concentration region 33b are changed. In FIG. 2 and FIG. 3 described later, the data of the high-concentration region width of 0 nm does not include the first high-concentration region 33a and the second high-concentration region 33b (that is, the main body region 32b includes only the low-concentration region 33c. FIG. 4 shows a simulation result of a semiconductor device (composed of the above). As shown in FIG. 2, when the main body region 32b has the high-concentration regions 33a and 33b, the gate threshold value is increased. Further, the wider the high-concentration regions 33a and 33b, the higher the gate threshold.

FIG. 3 shows a simulation result of the product of the area of the main body region 32b and the on-resistance (RonA) when the widths of the first high concentration region 33a and the second high concentration region 33b are changed. In FIG. 3, RonA is represented by a relative ratio based on the case where the high concentration regions 33a and 33b are not provided. High RonA means that the semiconductor device has high on-resistance. As shown in FIG. 3, the result was that RonA increased as the width of the high-concentration region was increased. Further, if the width of the high concentration region is narrowed to about 1 nm, the result is that RonA as low as that in the case where there is no high concentration region is obtained. Further, even if the width of the high-concentration region is set to about 10 nm, the on-resistance does not increase so much as compared with the case where the high-concentration region does not exist. Thus, it was found that RonA can be maintained at a low value by forming the high-concentration regions 33a and 33b only near the interface between the gate insulating film 24 and the main body region 32b.

As is clear from FIGS. 2 and 3, by providing the high-concentration regions 33a and 33b only near the interface between the gate insulating film 24 and the main body region 32b, it is possible to realize a high gate threshold and a low on-resistance. ..

In the semiconductor substrate 12 made of SiC as in this embodiment, the electron mobility in the vicinity of the interface between the gate insulating film 24 and the main body region 32b is about 10 to 120 cm ² /Vs. On the other hand, the mobility of electrons at a position away from the gate insulating film 24 is about 800 to 1000 cm ² /Vs. Therefore, the channel resistance can be significantly reduced by causing electrons to flow mainly in the low-concentration region 33c at a position distant from the gate insulating film 24, not in the vicinity of the gate insulating film 24. As described above, the technique disclosed in this specification is particularly useful when the semiconductor substrate 12 made of SiC is used.

Next, a method of manufacturing the semiconductor device 10 will be described. First, as shown in FIG. 4, a p-type low concentration region 33c is formed on the drift region 34 by epitaxial growth.

Next, as shown in FIG. 5, a plurality of trenches 50 are formed in the upper surface of the low concentration region 33c by selectively etching the upper surface of the low concentration region 33c. Each trench 50 is formed so that the bottom surface thereof has substantially the same depth as the interface between the low concentration region 33c and the drift region 34. That is, the drift region 34 is exposed on the bottom surface of each trench 50.

Next, as shown in FIG. 6, a p-type high concentration region 33 is formed in each trench 50 by epitaxial growth. The high concentration region 33 is formed to have a higher p-type impurity concentration than the low concentration region 33c.

Next, as shown in FIG. 7, by implanting n-type and p-type impurities from the upper surfaces of the high-concentration region 33 and the low-concentration region 33c, the n-type source region 30 and the p-type contact region 32a are removed. Form.

Next, as shown in FIG. 8, a plurality of trenches 22 are formed in the upper surface of each source region 30 by selectively etching the upper surface of each source region 30. Each trench 22 is formed so as to penetrate the source region 30 and the high concentration region 33 and reach the drift region 34. Each trench 22 is formed such that the source region 30 and the high-concentration region 33 remain in a range in contact with both side surfaces of each trench 22. Here, etching is performed so that the width of the remaining high-concentration region 33 is about 10 nm. Further, each trench 22 is formed such that the interval between two adjacent trenches 22 is 100 nm or less.

After that, the gate insulating film 24, the gate electrode 26, the interlayer insulating film 28, the upper electrode 70, the drain region 35, and the lower electrode 72 are formed by a conventionally known method, whereby the semiconductor device 10 shown in FIG. 1 is completed.

The second embodiment is different from the first embodiment in the method of manufacturing the semiconductor device, but the configuration is the same as that of the first embodiment. In the manufacturing method of the second embodiment, after the low concentration region 33c shown in FIG. 4 of the first embodiment is formed, the upper surface of the low concentration region 33c is selectively etched as shown in FIG. A plurality of trenches 22 are formed on the upper surface of 33c. Each trench 22 is formed so as to penetrate the low concentration region 33c and reach the drift region 34. Further, here, each trench 22 is formed such that the interval between two adjacent trenches 22 is 100 nm or less.

Next, as shown in FIG. 10, p-type impurities are implanted into the side surface of each trench 22. The p-type impurity is implanted by inclining the irradiation direction of the p-type impurity with respect to the depth direction of the trench 22. Thereby, as shown in FIG. 10, the high concentration region 33 is formed on the side surface of each trench 22. Here, the dose amount of the p-type impurity and the irradiation energy are adjusted so that the width of the high concentration region 33 is about 10 nm. After that, the source region 30 and the contact region 32a are formed by ion implantation of various impurities, and the gate insulating film 24, the gate electrode 26, the interlayer insulating film 28, the upper electrode 70, the drain region 35, and the lower electrode 72 are formed by a conventionally known method. The semiconductor device 10 is completed by forming the.

In the third embodiment, the semiconductor device manufacturing method is different from that of the first embodiment, but the configuration is the same as that of the first embodiment. In the manufacturing method of Example 3, first, as shown in FIG. 11, a semiconductor substrate having a drift region 60 is prepared. The drift region 60 has a total thickness of the drift region 34 and the low concentration region 33c in FIG. Next, as shown in FIG. 11, a plurality of trenches 22 are formed in the upper surface of the drift region 60 by selectively etching the upper surface of the drift region 60. Here, each trench 22 is formed such that the distance between two adjacent trenches 22 is 100 nm or less.

Next, as shown in FIG. 12, p-type impurities are implanted into the side surface of each trench 22. The p-type impurity is implanted by appropriately sloping the irradiation direction of the p-type impurity with respect to the depth direction of the trench 22. As a result, as shown in FIG. 12, the high-concentration region 33 is formed in a range in contact with the side surface of each trench 22, and the low-concentration region 33c is formed in a range more distant from the side surface of the trench 22 than the high-concentration region 33. The distance between two adjacent trenches 22 is as narrow as 100 nm or less. Therefore, in this step, the low-concentration region 33c and the high-concentration region 33 can be formed by adjusting the implantation profile of the p-type impurity during the ion implantation into the side surface of the trench 22. That is, when the p-type impurity is implanted into the side surface of the trench 22, the p-type impurity concentration becomes high in the range in contact with the side surface of the trench 22, and the p-type impurity concentration becomes high in the range away from the side surface of the trench 22. A p-type impurity is implanted so that it becomes low. As a result, the low concentration region 33c and the high concentration region 33 are formed. After that, the source region 30 and the contact region 32a are formed by ion implantation of various impurities, and the gate insulating film 24, the gate electrode 26, the interlayer insulating film 28, the upper electrode 70, the drain region 35, and the lower electrode 72 are formed by a conventionally known method. The semiconductor device 10 is completed by forming the.

In the above-described embodiment, the contact region 32a is arranged between the two source regions 30. However, the contact region 32a may be formed at another position and the first source region 30a and the second source region 30b may be connected. That is, the source region 30 extends from a position in contact with the gate insulating film 24 in the first trench 22a to a position in contact with the gate insulating film 24 in the second trench 22b in a range exposed on the upper surface 12a of the semiconductor substrate 12. Good. Even with such a configuration, the same effect as that of the above-described embodiment can be obtained.

Further, in the above-described embodiments, the source region 30 is in contact with the gate insulating film 24. However, the source region 30 does not have to be in contact with the gate insulating film 24. In the technique disclosed in this specification, electrons mainly flow in the low concentration region 33c by utilizing the bulk channel. That is, electrons mainly flow at a position away from the gate insulating film 24. Therefore, even when the source region 30 is not in contact with the gate insulating film 24, electrons are allowed to flow from the upper electrode 70 to the lower electrode 72 via the source region 30, the bulk channel, the drift region 34, and the drain region 35. You can

The first high concentration region 33a and the second high concentration region 33b may be connected at a position not shown.

Further, in the above-described embodiments, the case where the semiconductor device 10 is the MOSFET has been described. However, the semiconductor device 10 may be an IGBT (Insulated Gate Bipolar Transistor). The structure of the IGBT can be obtained by changing the drain region 35 to the p-type region.

The relationship between the components of the above-described embodiment and the components of the claims will be described. The source region 30 of the embodiment is an example of the claimed first semiconductor region. The drift region 34 of the embodiment is an example of the second semiconductor region in the claims.

The technical elements disclosed in this specification are described below. In the configuration of the example disclosed in this specification, the semiconductor substrate may be made of silicon carbide (SiC). In a semiconductor substrate made of SiC, the mobility of electrons is particularly low near the interface with the gate insulating film. Therefore, the bulk channel semiconductor device disclosed in this specification is particularly useful when a semiconductor substrate made of SiC is used.

Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and achieving the one object among them has technical utility.

Reference numeral 10: trench gate type semiconductor device, 12: semiconductor substrate, 12a: upper surface, 12b: lower surface, 22a: first trench, 22b: second trench, 24: gate insulating film, 26: gate electrode, 28: interlayer insulating film, 30: source region, 32: body region, 32a: contact region, 32b: main body region, 33a: first high concentration region, 33b: second high concentration region, 33c: low concentration region, 34: drift region, 35: Drain region, 70: upper electrode, 72: lower electrode

Claims (2)

A trench gate type semiconductor device,
A semiconductor substrate,
A first trench provided on the upper surface of the semiconductor substrate;
A second trench provided on the upper surface of the semiconductor substrate at a distance from the first trench;
A gate insulating film covering the inner surface of the first trench and the inner surface of the second trench;
A gate electrode disposed in the first trench and the second trench and insulated from the semiconductor substrate by the gate insulating film,
Has
The semiconductor substrate is
An n-type first semiconductor region disposed between the first trench and the second trench,
It is arranged between the first trench and the second trench, is arranged below the first semiconductor region, and is arranged in the second trench from a position in contact with the gate insulating film in the first trench. A p-type body region extending to a position in contact with the gate insulating film,
It is arranged between the first trench and the second trench, is arranged below the body region, and is arranged in the second trench from a position in contact with the gate insulating film in the first trench. An n-type second semiconductor region that extends to a position in contact with the gate insulating film and is separated from the first semiconductor region by the body region,
Has
The distance between the first trench and the second trench is 100 nm or less,
The body region is
A first high-concentration region provided in a range in contact with the gate insulating film in the first trench;
A second high-concentration region provided in a range in contact with the gate insulating film in the second trench;
A low-concentration region that is arranged between the first high-concentration region and the second high-concentration region and has a lower p-type impurity concentration than the first high-concentration region and the second high-concentration region;
Have
Trench gate type semiconductor device. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide.

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