JP2020123607A - Semiconductor device - Google Patents

Abstract

To provide a technique capable of reducing channel resistance in a semiconductor device including a trench gate.SOLUTION: A semiconductor substrate has an n-type upper surface region, a p-type body region and an n-type drift region arranged between a first trench and a second trench. At least a part of the body region is constituted so as to display a bulk channel effect. Concentration in the depth direction of a p-type impurity included in the body region is increased in a direction from the upper surface region side to the drift region side and a peak is formed on the drift region side. The drift region includes a low concentration drift region and a high concentration drift region. The high concentration drift region is formed between the low concentration drift region and the body region and is arranged between the first trench and the second trench and the concentration of an n-type impurity of the high concentration drift region is higher than that of the low concentration drift region.SELECTED DRAWING: Figure 1

Description

The technique disclosed in the present specification relates to a semiconductor device including a trench gate.

Patent Document 1 discloses a semiconductor device including a trench gate. This semiconductor device has a semiconductor substrate having a trench on its upper surface, and a gate insulating film and a gate electrode arranged in the trench. The gate electrode is insulated from the semiconductor substrate by the gate insulating film. In this semiconductor device, the semiconductor substrate has an n-type source region, a p-type body region, and an n-type drift region. The source region is arranged on the upper surface of the semiconductor substrate and is in contact with the gate insulating film. The body region is in contact with the gate insulating film below the upper surface region. The drift region is in contact with the gate insulating film below the body region and is separated from the source region by the body region.

When the semiconductor device of Patent Document 1 is turned on, the potential of the gate electrode is set higher than the gate threshold value. Then, a channel is formed in the body region near the gate insulating film. Electrons flow from the source region to the drift region via the channel, so that the semiconductor device is turned on.

Japanese Unexamined Patent Application Publication No. 2015-159272

In the semiconductor device of Patent Document 1, the channel is formed only near the gate insulating film. Therefore, the electrons flow near the interface between the body region and the gate insulating film. When the electrons flow near the interface between the body region and the gate insulating film, the electrons are scattered. For example, electrons are scattered by the charges trapped in the interface state between the body region and the gate insulating film. In addition, electrons are scattered by the roughness of the interface between the body region and the gate insulating film. Due to the scattering of electrons in this way, there is a problem that the mobility of the electrons flowing through the channel decreases and the channel resistance increases. The present specification provides a technique capable of reducing channel resistance in a semiconductor device including a trench gate.

In a semiconductor device having a trench gate, by narrowing a gap between two adjacent trenches, when the semiconductor device is turned on, not only the vicinity of the gate insulating film but also the body region located apart from the gate insulating film is formed. The channels can also be formed. That is, by narrowing the width of the body region, a wide range of the body region can function as a channel. In this specification, such a channel is called a bulk channel, and a phenomenon in which the bulk channel flows is called a bulk channel effect. In the bulk channel, electrons flow even at a position away from the gate insulating film. Therefore, the electrons are less likely to be affected by the scattering caused by the interface between the gate insulating film and the body region. Therefore, the mobility of electrons can be improved by exerting the bulk channel effect. However, in order to exert the bulk channel effect, it is necessary to make the concentration of the body region relatively low. Therefore, when the semiconductor device is off, there is a problem of punch-through in which the depletion layer extending from the pn junction between the body region and the drift region to the source region reaches the source region. In view of the above circumstances, the semiconductor device disclosed in this specification has the following configuration.

The semiconductor device disclosed in this specification includes a semiconductor substrate, a first trench, a second trench, a gate insulating film, and a gate electrode. The first trench is provided on the upper surface of the semiconductor substrate. The second trench is provided on the upper surface of the semiconductor substrate at a distance from the first trench. The gate insulating film covers the inner surface of the first trench and the inner surface of the second trench. The gate electrode is arranged in the first trench and the second trench, and is insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has an upper surface region, a body region, and a drift region. The upper surface region is an n-type region arranged between the first trench and the second trench. The body region is disposed between the first trench and the second trench, is provided below the upper surface region, and is located from a position in contact with the gate insulating film in the first trench to the first trench. 2 is a p-type region extending to a position in contact with the gate insulating film in the trench. The drift region is an n-type region disposed below the body region and separated from the upper surface region by the body region. At least a part of the body region is configured to exhibit a bulk channel effect. The concentration distribution of the p-type impurity contained in the body region in the depth direction has a portion increasing from the upper surface region side toward the drift region side and has a peak on the drift region side. The drift region includes a low concentration drift region and a high concentration drift region. The high-concentration drift region is disposed between the first trench and the second trench, is provided between the low-concentration drift region and the body region, and is more n-type than the low-concentration drift region. High impurity concentration.

In the above semiconductor device, at least a part of the body region is configured to exhibit a bulk channel effect. In addition to that, in the semiconductor device, the concentration distribution of the p-type impurities contained in the body region in the depth direction has a portion increasing from the upper surface region side toward the drift region side, and also on the drift region side. It has a peak. Thus, the body region has a concentration distribution called retrograde. Therefore, when the semiconductor device is off, depletion of the body region due to a depletion layer extending from the pn junction between the body region and the drift region into the body region is suppressed, and punch through is suppressed.

When the body region has a retrograde concentration distribution, the p-type impurity contained in the body region spreads and spreads from the peak along the depth direction so as to be tailed. Therefore, the thickness of the body region in the depth direction is increased by a portion (in the present specification, referred to as a “hemiform portion”) that spreads from the peak of the concentration distribution of the body region toward the drift region side. Tends to grow. If the thickness of the body region is increased, the channel resistance will be increased. The high-concentration drift region is provided on the semiconductor substrate of the semiconductor device. By providing the high-concentration drift region, the bottom portion of the body region is inverted to n-type, and the thickness of the bottom portion of the body region is suppressed. As described above, in the semiconductor device disclosed in the present specification, it is possible to realize low channel resistance while suppressing punch-through which is a problem when a bulk channel is embodied.

1 schematically shows a cross-sectional view of a main part of a semiconductor device of this embodiment. 5 shows a concentration distribution in the depth direction of a semiconductor substrate of the semiconductor device of this embodiment.

The semiconductor device 1 of this embodiment shown in FIG. 1 is a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The semiconductor device 1 has a semiconductor substrate 10. In this embodiment, the semiconductor substrate 10 is made of silicon carbide (SiC). The material of the semiconductor substrate 10 is not limited to the above, and may be various semiconductor materials such as silicon (Si) and gallium nitride (GaN). Hereinafter, one direction parallel to the upper surface 10a of the semiconductor substrate 10 (left-right direction in FIG. 1) is referred to as the x direction, and a direction parallel to the upper surface 10a and orthogonal to the x direction (direction perpendicular to the paper surface of FIG. 1). Is referred to as the y direction, and a direction (depth direction of the semiconductor substrate 10) orthogonal to both the x direction and the y direction is referred to as the z direction.

As shown in FIG. 1, a plurality of trenches 22 are provided on the upper surface 10 a of the semiconductor substrate 10. Each trench 22 extends long in the y direction. The trenches 22 extend in parallel with each other at intervals in the x direction. The inner surface of each trench 22 is covered with a gate insulating film 24. A gate electrode 26 is arranged inside each trench 22. The gate electrode 26 is insulated from the semiconductor substrate 10 by the gate insulating film 24. The upper surface of each gate electrode 26 is covered with an interlayer insulating film 28. Instead of the example of FIG. 1, the interlayer insulating film 28 may be provided so as to cover the upper surface of the gate electrode 26 and fit inside the trench 22. Hereinafter, for convenience of description, the left trench 22 in FIG. 1 may be referred to as a first trench 22a, and the right trench 22 in FIG. 1 may be referred to as a second trench 22b. Although not shown, a plurality of trenches similar to the trench 22 are formed on the left side of the first trench 22a and the right side of the second trench 22b in FIG. In this embodiment, the distance between the trenches 22 is 100 nm or less. Specifically, as shown in FIG. 1, the distance W between the opposing side surfaces of two adjacent trenches 22 is 100 nm or less.

The source electrode 32 is arranged on the upper surface 10 a of the semiconductor substrate 10. The source electrode 32 is in contact with the upper surface 10a of the semiconductor substrate 10 at the portion where the interlayer insulating film 28 is not provided. The source electrode 32 is insulated from the gate electrode 26 by the interlayer insulating film 28. The drain electrode 34 is disposed on the lower surface 10b of the semiconductor substrate 10. The drain electrode 34 is in contact with substantially the entire lower surface 10b of the semiconductor substrate 10.

Inside the semiconductor substrate 10, a plurality of source regions 11, body contact regions 12, body regions 13, drift regions 14 and drain regions 15 are provided.

The source region 11 is an n-type region. Each source region 11 is arranged between the first trench 22a and the second trench 22b, is provided at a position exposed on the upper surface 10a of the semiconductor substrate 10, and is in ohmic contact with the source electrode 32. The source region 11 has a first source region 11a and a second source region 11b. The first source region 11a is in contact with the gate insulating film 24 in the first trench 22a at the upper end of the first trench 22a. The second source region 11b is in contact with the gate insulating film 24 in the second trench 22b at the upper end of the second trench 22b. Each source region 11 is formed by introducing nitrogen as an n-type impurity from the upper surface 10a of the semiconductor substrate 10 using an ion implantation technique. Each source region 11 is an example of the upper surface region described in the claims.

The body contact region 12 is a p-type region. The body contact region 12 is arranged between the first trench 22a and the second trench 22b, and is provided at a position exposed on the upper surface 10a of the semiconductor substrate 10. The concentration of p-type impurities contained in body contact region 12 is higher than the concentration of p-type impurities contained in body region 13. The body contact region 12 is in ohmic contact with the source electrode 32. The body contact region 12 is formed by introducing aluminum as a p-type impurity from the upper surface 10a of the semiconductor substrate 10 using an ion implantation technique.

The body region 13 is a p-type region. The body region 13 is arranged between the first trench 22a and the second trench 22b, and is provided below each source region 11. More specifically, the body region 13 extends from the range between the first source region 11a and the second source region 11b to the lower side of each source region 11, and contacts the side surface and the bottom surface of each source region 11. There is. Furthermore, the body region 13 extends from a position in contact with the gate insulating film 24 in the first trench 22a to a position in contact with the gate insulating film 24 in the second trench 22b. In other words, the body region 13 is provided between the first trench 22a and the second trench 22b that are adjacent to each other. The body region 13 is formed by introducing aluminum as a p-type impurity from the upper surface 10a of the semiconductor substrate 10 using an ion implantation technique. As will be described later, the body region 13 has a concentration distribution called retrograde.

The drift region 14 is an n-type region. Drift region 14 is arranged below body region 13 and is separated from source region 11 by body region 13. The drift region 14 has a high concentration drift region 14a and a low concentration drift region 14b.

The high concentration drift region 14a is arranged between the first trench 22a and the second trench 22b, and is provided between the low concentration drift region 14b and the body region 13. The high-concentration drift region 14a extends from a position in contact with the gate insulating film 24 in the first trench 22a to a position in contact with the gate insulating film 24 in the second trench 22b. In this example, a part of the high concentration drift region 14a covers the bottom of the first trench 22a and the bottom of the second trench 22b. Instead of this example, the high concentration drift region 14a may be arranged only between the first trench 22a and the second trench 22b. The concentration of the n-type impurity contained in the high concentration drift region 14a is higher than the concentration of the n-type impurity contained in the low concentration drift region 14b. The high-concentration drift region 14a is formed by introducing nitrogen as an n-type impurity from the upper surface 10a of the semiconductor substrate 10 using an ion implantation technique. Instead of this example, the high concentration drift region 14a may be formed by crystal growth from the surface of the low concentration drift region 14b using an epitaxial growth technique.

The low-concentration drift region 14b is arranged between the drain region 15 and the high-concentration drift region 14a, and is provided below each trench 22. The low concentration drift region 14b is formed by crystal growth from the surface of the drain region 15 using an epitaxial growth technique.

The drain region 15 is an n-type region. The concentration of the n-type impurity contained in the drain region 15 is higher than the concentration of the n-type impurity contained in the low concentration drift region 14b. The drain region 15 is in contact with the bottom surface of the low concentration drift region 14b and is arranged below the low concentration drift region 14b. The drain region 15 is exposed on the lower surface 10b of the semiconductor substrate 10. The drain region 15 is in ohmic contact with the drain electrode 34.

Next, the operation of the semiconductor device 1 will be described. When using the semiconductor device 1, the semiconductor device 1, a load (for example, a motor), and a power supply are connected in series. A power supply voltage is applied to the series circuit of the semiconductor device 1 and the load. The power supply voltage is applied so that the drain side (drain electrode 34) of the semiconductor device 1 has a higher potential than the source side (source electrode 32). In this embodiment, the distance W between the first trench 22a and the second trench 22b is 100 nm or less. That is, the width of the body region 13 is 100 nm or less. Since the width of the body region 13 is sufficiently narrow, when the potential of the gate electrode 26 is increased, a channel is formed not only in the vicinity of the gate insulating film 24 but also in the body region 13 distant from the gate insulating film 24. Particularly, since the concentration of the body region 13 on the source region 11 side is adjusted to be low, a channel (that is, a bulk channel) is formed over the entire region. In the semiconductor device 1, the source region 11 and the drift region 14 are connected via such a bulk channel. As a result, the semiconductor device 1 is turned on.

When the semiconductor device 1 is turned off, a potential lower than the gate threshold is applied to the gate electrode 26. Then, the channel formed in the body region 13 disappears and the semiconductor device 1 is turned off.

FIG. 2 shows the concentration distribution of n-type impurities (nitrogen) and p-type impurities (aluminum) in the z direction (depth direction) of the semiconductor substrate 10. As shown in FIG. 2, the z-direction concentration of the p-type impurity contained in the body region 13 increases from the source region 11 side toward the drift region 14 side, and has a peak on the drift region 14 side. There is. Thus, the body region 13 has a concentration distribution called retrograde. For this reason, in the semiconductor device 1, when the semiconductor device 1 is off, punch-through in which the depletion layer extending from the pn junction of the body region 13 and the high-concentration drift region 14a to the body region 13 side reaches the source region 11 is suppressed. Therefore, the semiconductor device 1 can have high breakdown voltage characteristics.

As shown in FIG. 2, the peak of the p-type impurity contained in the body region 13 in the z direction is closer to the drift region 14 than the center of the body region 13 in the z direction. Therefore, the range 13A in which the concentration of the p-type impurity contained in the body region 13 is relatively low largely spreads to the source region 11 side of the body region 13. This range 13A is a region in which a bulk channel is formed when the semiconductor device 1 is turned on, together with the distance between the first trench 22a and the second trench 22b being 100 nm or less. As described above, in the semiconductor device 1, since the bulk channel is formed in the wide area of the body region 13, low channel resistance is realized.

Here, consider a case where the high-concentration drift region 14a is not provided in the semiconductor device 1. As shown in FIG. 2, when the body region 13 has a retrograde concentration distribution, the p-type impurity contained in the body region 13 spreads from the peak to the bottom along the depth direction. It is spreading. Particularly, in the retrograde concentration distribution, there is a skirt portion 13B extending from the peak toward the drift region 14 side. When the high-concentration drift region 14a is not provided, this bottom portion 13B also falls within the range of the body region 13. In the example of FIG. 2, the body region 13 is formed to a depth where the concentration of the bottom portion 13B matches the concentration of the low concentration drift region 14b, and the thickness of the body region 13 in the z direction increases. If the thickness of the body region 13 is increased, the channel resistance will be increased. If the peak of the p-type impurity is located at a shallow position on the semiconductor substrate 10, the bottom portion 13B also has a shallow depth, and the thickness of the body region 13 can be reduced. However, when the peak of the p-type impurity is located at a shallow position in the semiconductor substrate 10, the range 13A in which the concentration of the p-type impurity is relatively low becomes small, and the bulk channel reduces the effect of reducing the channel resistance. As described above, when the body region 13 has the retrograde concentration distribution, the channel resistance increases unless the high concentration drift region 14a is provided.

In the semiconductor device 1, since the high-concentration drift region 14a is provided, the bottom portion 13B of the body region 13 is inverted to the n-type, and the thickness of the body region 13 is suppressed. Therefore, in the semiconductor device 1, a low channel resistance is realized.

In the conventional semiconductor device in which the distance between the adjacent trenches is wide, the channel is formed only in the vicinity of the gate insulating film in the body region. Therefore, the electrons flow near the interface between the gate insulating film and the body region. At this time, electrons are scattered by the charges trapped in the interface state between the gate insulating film and the body region and the roughness of the interface between the gate insulating film and the body region. As a result, the mobility of the electrons flowing in the channel is lowered and the channel resistance is increased.

On the other hand, in the present embodiment, the bulk channel is formed in at least a part of the body region 13. In the bulk channel, electrons flow not only in the body region 13 in the vicinity of the gate insulating film 24 but also in the body region 13 in a portion distant from the gate insulating film 24. In the body region 13 separated from the gate insulating film 24, electron scattering due to the interface between the gate insulating film 24 and the body region 13 does not occur. In this way, electrons are less likely to be scattered in the body region 13 in the portion distant from the gate insulating film 24, so that the mobility of electrons is high. Therefore, in the semiconductor device 1 of this embodiment, a low channel resistance can be realized by forming the bulk channel.

As described above, in the semiconductor device 1, the punch-through that may be caused by embodying the bulk channel is suppressed by adopting the retrograde concentration distribution in the body region 13, and the channel that may be caused by the retrograde concentration distribution is suppressed. The increase in resistance can be suppressed by adopting the high concentration drift region 14b. As a result, the semiconductor device 1 can favorably obtain the benefit of the low channel resistance obtained by the bulk channel.

In the semiconductor device 1 of the above-described embodiment, since the high-concentration drift region 14b is provided, even if the peak concentration of the p-type impurity contained in the body region 13 is increased, the body region caused by the bottom portion 13B is generated. The increase in the thickness of 13 can be suppressed. In other words, since the peak concentration of the p-type impurity contained in the body region 13 can be set high, the controllability of the gate threshold voltage can be improved.

Further, in the semiconductor device 1 of the above-described embodiment, since the high concentration drift region 14b is provided, the current flowing in the high concentration drift region 14b can diffuse in the surface direction. Therefore, in the semiconductor device 1, the drift resistance can be reduced.

Further, in the above-described embodiment, the case where the semiconductor device 1 is the MOSFET has been described. However, the semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor).

Further, in the semiconductor device 1 of the above-described embodiment, the semiconductor substrate is made of silicon carbide (SiC). In a semiconductor substrate made of SiC, the mobility of electrons is particularly low near the interface with the gate insulating film. Therefore, the bulk channel semiconductor device disclosed in this specification is particularly useful when a semiconductor substrate made of SiC is used.

Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and achieving the one object among them has technical utility.

1: trench gate type semiconductor device, 10: semiconductor substrate, 10a: upper surface, 12b: lower surface, 22a: first trench, 22b: second trench, 24: gate insulating film, 26: gate electrode, 28: interlayer insulating film, 11: source region, 12: body contact region, 13: body region, 14: drift region, 14a: high concentration drift region, 14b: low concentration drift region, 15: drain region, 32: source electrode, 34: drain electrode

Claims (2)

A semiconductor device,
A semiconductor substrate,
A first trench provided on the upper surface of the semiconductor substrate;
A second trench provided on the upper surface of the semiconductor substrate at a distance from the first trench;
A gate insulating film covering the inner surface of the first trench and the inner surface of the second trench;
A gate electrode disposed in the first trench and the second trench and insulated from the semiconductor substrate by the gate insulating film,
The semiconductor substrate is
An n-type upper surface region disposed between the first trench and the second trench,
The second trench is arranged between the first trench and the second trench, is provided below the upper surface region, and is located in the second trench from a position in contact with the gate insulating film in the first trench. A p-type body region extending to a position in contact with the gate insulating film,
An n-type drift region disposed below the body region and separated from the upper surface region by the body region,
At least a part of the body region is configured to exert a bulk channel effect,
The concentration distribution in the depth direction of the p-type impurity contained in the body region has a portion increasing from the upper surface region side toward the drift region side, and has a peak on the drift region side,
The drift region is
A low concentration drift region,
A high concentration that is arranged between the first trench and the second trench, is provided between the low concentration drift region and the body region, and has a higher concentration of n-type impurities than the low concentration drift region. A drift region and a semiconductor device. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide.

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