JP2011199109A - Power mosfet - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain both low ON resistance and a high source-drain breakdown voltage by an increase in total gate width by fining a gate pitch although, in an in-trench double-gate type vertical power MOSFET having a genuine gate electrode and an embedded field plate electrode in a trench generally, ON resistance reduction effect by fining the gate pitch is reduced when the gate pitch is reduced up to a region of ≤2 micrometers.SOLUTION: The in-trench double-gate type vertical power MOSFET has a trench interval of 0.1 to 1.5 micrometers.

Description

  The present invention relates to a technique effective when applied to a MOSFET device technique in a semiconductor device (or a semiconductor integrated circuit device).

  Japanese Patent Application Laid-Open No. 2004-47923 (Patent Document 1) or US Patent Publication No. 2004-56284 (Patent Document 2) corresponding thereto discloses a field plate connected to a source potential or a gate potential (Field Plate). A lateral power MOSFET with electrodes is disclosed.

  In Japanese Unexamined Patent Application Publication No. 2008-103683 (Patent Document 3) or US Patent Publication No. 2008-42172 (Patent Document 4) corresponding thereto, the source potential is set below a normal trench gate electrode. A power MOSFET having connected field plate electrodes is disclosed.

  Japanese Patent Laid-Open No. 2006-324570 (Patent Document 5) or US Patent Publication No. 2009-230467 (Patent Document 6) corresponding thereto discloses a field connected to a gate potential below a normal trench gate electrode. A power MOSFET having a plate electrode is disclosed.

JP 2004-47923 A US Patent Publication No. 2004-56284 JP 2008-103683 A US Patent Publication No. 2008-42172 JP 2006-324570 A US Patent Publication No. 2009-230467

  Normally, it is effective to reduce the gate pitch in order to reduce the channel resistance of the trench power MOSFET. However, an intrinsic gate electrode (usually simply referred to as “gate electrode”) and a buried field in a deep trench. In a double-gate vertical power MOSFET in a trench having a plate electrode, when the gate pitch is reduced to a region of about 2 micrometers or less, the width of the drift region between trenches, which is a current path, is reduced. Therefore, the on-resistance reduction effect due to the increase in the total gate width is reduced. However, according to various investigations and verifications by the inventors of the present application, the double-gate type vertical power MOSFET in the gate connection type in which the buried field plate electrode is connected to the gate potential is connected to the source potential. It was found that the source-connected double-gate type vertical power MOSFET in the trench is less susceptible to the narrowing of the current path due to miniaturization. For this reason, in the gate-connected in-trench double-gate vertical power MOSFET, there is a possibility that both low on-resistance and high source-drain breakdown voltage can be achieved by increasing the total gate width by reducing the gate pitch.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a semiconductor device such as a power MOSFET capable of realizing a low on-resistance while ensuring a withstand voltage.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, in the double gate type power MOSFET in the trench, the trench interval is 1.5 micrometers or less and 0.1 micrometers or more.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the double-gate power MOSFET in the trench, by setting the trench interval to 1.5 micrometers or less and 0.1 micrometers or more, a low on-resistance can be realized while ensuring a withstand voltage. .

It is a chip | tip top view of the double gate type N channel power MOSFET in a trench of one embodiment of this application. FIG. 2 is an enlarged top view of a cell region cutout portion R1 in FIG. FIG. 3 is a device cross-sectional view corresponding to the X-X ′ cross section of FIG. 2. FIG. 2 is a device cross-sectional view corresponding to a Y′-Y cross section of FIG. 1. FIG. 2 is a device cross-sectional view corresponding to a Y ″ -Y cross section of FIG. 1. FIG. 3 is a device cross-sectional process flow diagram (trench processing hard mask film patterning step) corresponding to the X-X ′ cross section of FIG. 2 of the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (trench processing step) corresponding to the X-X ′ cross section of FIG. 2 of the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (field plate peripheral insulating film forming step) corresponding to the X-X ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (a polysilicon film forming step for field plate electrodes) corresponding to the X-X ′ cross section of FIG. 2 of the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (field plate processing step) corresponding to the X-X ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (field plate peripheral insulating film etch-back step) corresponding to the X-X ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (a gate insulating film forming step) corresponding to the X-X ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (a polysilicon film forming step for a gate electrode) corresponding to the X-X ′ cross section of FIG. FIG. 3 is a device cross-sectional process flow diagram (gate electrode patterning step) corresponding to the X-X ′ cross section of FIG. 2 of the double gate N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (N-channel region forming step) corresponding to the X-X ′ cross-section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (N + source region forming step) corresponding to the X-X ′ cross section of FIG. 2 of the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (interlayer insulating film forming step) corresponding to the X-X ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (contact hole forming step) corresponding to the X-X ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (contact hole extension and N + body contact region forming step) corresponding to the X-X ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (barrier metal film forming step) corresponding to the X-X ′ cross section of FIG. 2 of the double gate N-channel power MOSFET in the trench according to the embodiment of the present application; FIG. 3 is a device cross-sectional process flow diagram (aluminum-based source metal electrode film forming step) corresponding to the X-X ′ cross section of FIG. 2 of the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 3 is a device cross-sectional process flow diagram (polyimide final passivation film forming step) corresponding to the X-X ′ cross section of FIG. 2 of the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 3 is a device cross-sectional process flow diagram (a step of forming a gate pad opening and a source pad opening) corresponding to the X-X ′ cross section of FIG. FIG. 4 is a detailed sectional view showing a more detailed structure of a device section corresponding to FIG. 3. It is a data plot figure which shows the cell pitch dependence of on-resistance in the double gate type N channel power MOSFET in a trench of one embodiment of this application. It is a data plot figure which shows the trench space | interval dependence of on resistance in the double gate type N channel power MOSFET in a trench of one embodiment of this application. It is a simulation result of the electron density distribution of the cell part of the double gate type N channel power MOSFET in the source connection type trench which is a comparative example. It is the simulation result of the electron density distribution of the cell part of the double gate type N channel power MOSFET in the gate connection type | mold trench of one embodiment of this application. It is the simulation result of the current density distribution of the cell part of the double gate type N channel power MOSFET in the source connection type trench which is a comparative example. It is the simulation result of the current density distribution of the cell part of the double gate type N channel power MOSFET in the gate connection type trench of one embodiment of this application. It is a data plot figure which shows the gate source voltage dependence of the gate-source current in the cell part of the source connection type which is a comparative example, and the gate connection type in-gate double gate type N channel power MOSFET of one embodiment of this application.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Power MOSFET including:
(A) a silicon-based semiconductor substrate having one principal surface;
(B) a number of linear trenches provided in the first main surface;
Here, each linear trench has:
(B1) polysilicon linear field plate electrode;
(B2) A polysilicon linear gate electrode provided above the polysilicon linear field plate electrode,
Furthermore, where
(1) The polysilicon linear field plate electrode is connected to substantially the same potential as the polysilicon linear gate electrode,
(2) An interval between adjacent linear trenches of the multiple linear trenches is 1.5 micrometers or less and 0.1 micrometers or more.

  2. In the power MOSFET of item 1, the polysilicon linear field plate electrode is electrically connected to the polysilicon linear gate electrode outside the linear trench.

  3. In the power MOSFET of item 1 or 2, the interval between the adjacent linear trenches of the multiple linear trenches is 1.3 micrometers or less and 0.1 micrometers or more.

  4). In the power MOSFET of item 1 or 2, the interval between the adjacent linear trenches of the plurality of linear trenches is 1.2 micrometers or less and 0.1 micrometers or more.

  5. 5. In the power MOSFET of any one of items 1 to 4, the polysilicon linear field plate electrode is separated from the inner surface of each linear trench by a first insulating film.

  6). 5. In the power MOSFET of item 5, the polysilicon linear gate electrode is separated from the inner surface of each linear trench and the polysilicon linear field plate electrode by a second insulating film thinner than the first insulating film. ing.

  7). 7. The power MOSFET according to any one of 1 to 6, wherein the power MOSFET is an N-channel power MOSFET.

8). A power MOSFET manufacturing method including the following steps:
(A) a step of preparing a silicon-based semiconductor substrate having one principal surface;
(B) forming a large number of linear trenches on the first main surface;
(C) coating the inner surface of each linear trench with a first insulating film;
(D) burying a first polysilicon electrode to be a field plate electrode in each linear trench covered with the first insulating film;
(E) in each linear trench, removing the first insulating film on the inner surface of the upper half to expose the upper surface of the upper half and the upper end of the first polysilicon electrode;
(F) a step of covering the exposed inner surface of the upper half portion and the upper end portion of the first polysilicon electrode with a second insulating film;
(G) After the step (f), a step of embedding a second polysilicon electrode which is thinner than the first insulating film and is to become a gate electrode in the upper half of each linear trench;
here,
(1) The field plate electrode is connected to substantially the same potential as the gate electrode;
(2) The spacing between adjacent linear trenches of the multiple linear trenches is 1.5 micrometers or less and 0.1 micrometers or more.

  9. In the power MOSFET manufacturing method according to the item 8, the field plate electrode is electrically connected to the gate electrode outside the linear trench.

  10. In the method for manufacturing a power MOSFET according to item 8 or 9, an interval between adjacent linear trenches of the plurality of linear trenches is 1.3 micrometers or less and 0.1 micrometers or more.

  11. In the method for manufacturing a power MOSFET according to item 8 or 9, an interval between adjacent linear trenches of the plurality of linear trenches is 1.2 micrometers or less and 0.1 micrometers or more.

  12 12. In the method for manufacturing a power MOSFET according to any one of 8 to 11, the power MOSFET is an N-channel power MOSFET.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “transistor”, “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various transistors (active elements) alone, and mainly a resistor, a capacitor, etc., as a semiconductor chip, etc. The one integrated on (for example, a single crystal silicon substrate). Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. In the present application, the term “MOSFET” includes not only the gate insulating film that is an oxide film, but also those that use other insulating films as the gate insulating film.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or carbon-doped silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In the present application, the term “power semiconductor” refers to a semiconductor device that can handle electric power of several watts or more. Therefore, all normal power MOSFETs are included in this.

  Among power MOSFETs, a “trench gate power MOSFET” is usually a gate electrode made of polysilicon or the like in a trench (relatively long and thin groove) formed on a device surface (first main surface) of a semiconductor substrate. In other words, the channel is formed in the thickness direction (vertical direction) of the semiconductor substrate. In this case, the device surface side of the semiconductor substrate is usually the source, and the back surface side (second main surface side) is the drain. A part of the main part of the gate electrode (a part other than the electrode lead part) may protrude from the trench.

  Among the trench gate power MOSFETs, the “in-trench double gate type power MOSFET” refers to one having a field plate electrode below the gate electrode (intrinsic gate electrode) in the trench. Due to manufacturing problems, there are many cases where the gate electrode (intrinsic gate electrode) and the field plate electrode (field plate gate electrode) are separated in the trench (double gate separation type structure), but the gate electrode and the field plate electrode It is assumed that the structure in which the two are integrated (double gate integrated structure) also belongs to the double gate type power MOSFET in the trench. In addition, the double gate separation type structure has the same potential of the field plate gate electrode as that of the intrinsic gate electrode (connected to the intrinsic gate electrode outside the trench) and the potential of the field plate gate electrode as the source. Same as the electrode (connected to the source electrode outside the trench) and classified as “source connection type”.

  Here, the “field plate electrode” is an electrode having a function of dispersing a steep potential gradient concentrated near the drain side end of the gate electrode, and is usually electrically connected to the source electrode or the gate electrode. Usually, the interface between the field plate electrode and the drift region is formed of an insulating film thicker than the gate insulating film (intrinsic gate insulating film).

  The N-channel power MOSFET handled in the present application is normally a normally-off device from the viewpoint of fail-safe which is a basic requirement for a power device, and the threshold voltage (Vth) is a positive value (based on the source potential). The range of Vth mainly targeted in the present application is about 0.5 to 6 volts.

  7). In the present application, when it is referred to as “linear”, it goes without saying that it includes not only a linear shape but also a bent portion.

  In addition, when referring to “a large number” of trenches, electrodes, etc., it indicates the number that constitutes a repetitive structure, and indicates a number of at least 10 or more. In the repetitive structure of the cell part mainly dealt with in the present application, Represents a numerical value between 100 and 10,000.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  In addition, as a prior patent application by the inventors of the present application which discloses a double gate type power MOSFET in a trench in which a field plate is connected to the same potential as a gate electrode, for example, Japanese Patent Application No. 2010-46452 March 3).

1. Description of device structure of double gate type N-channel power MOSFET in trench according to one embodiment of the present application (mainly FIGS. 1 to 5)
In this example, the trench gate electrode and the field plate electrode are separate from each other. However, since they are the same type of polysilicon and the same material, they may be configured as an integral one. However, if integrated, there is a demerit that it becomes difficult to make a difference in thickness between the gate oxide film 18 (FIG. 3) and the field plate-gate insulating film 19 (FIG. 3). In particular, in a gate-connected in-trench double gate N-channel power MOSFET (the same applies to a gate-connected in-trench double-gate P-channel power MOSFET), the gate electrode 12 (FIG. 3) and the field plate electrode 20 (FIG. 3). And the field plate-gate insulating film 29 (FIG. 3) may be thin, so that the trench gate electrode 12 (FIG. 3) and the field plate electrode 20 (FIG. 3) are separated from each other. The process consistency is higher.

  The characteristics, basic specifications, and the like of the double-gate N-channel power MOSFET in the trench are various. In the present application, the following devices will be mainly described for convenience of explanation. That is, for example, the drive is about 4.5 volts, Vth is about 1.7 volts (the range is about 0.5 to 6 volts), and the source / drain breakdown voltage is about 60 volts, for example, about 30 to 150 volts ( For convenience, the gate breakdown voltage is about 20 volts, the allowable current is about 80 to 160 amperes, the maximum operating frequency is about 10 to 150 kHz, and the cell pitch is about 1.25 micrometers (the range is 0.6 to 2 micrometers). Meter), the gate width is, for example, about 0.65 micrometers (the range is, for example, about 0.2 to 1 micrometer), the on-resistance is, for example, about 40 mΩ / mm 2, and the chip size is, for example, 3 mm in length , About 5mm wide A rectangular shape) shape or a rectangle.

  In the following example (including the example of section 2), description will be made mainly by taking a motor drive device as an example, so that the trench gate electrode and the field plate electrode are electrically connected to each other.

  FIG. 1 is a top view of a chip of a double gate type N-channel power MOSFET in a trench according to an embodiment of the present application. FIG. 2 is an enlarged top view of the cell region cutout portion R1 of FIG. FIG. 3 is a device cross-sectional view corresponding to the X-X ′ cross section of FIG. 2. FIG. 4 is a device cross-sectional view corresponding to the Y′-Y cross section of FIG. 1. FIG. 5 is a device cross-sectional view corresponding to the Y ″ -Y cross section of FIG. 1. Based on these, the device structure of the in-trench double-gate N-channel power MOSFET according to one embodiment of the present application will be described.

  First, the schematic structure of the upper surface 1a of the device chip 2 of the in-trench double gate type N-channel power MOSFET will be described with reference to FIG. As shown in FIG. 1, the ring-shaped electrode that circulates the end of the chip 2 (for example, a silicon-based semiconductor substrate) is a polysilicon guard ring 3, and the inner ring-shaped electrode is a trench gate. It is a gate wiring 4 for drawing out an electrode to the outside. The gate wiring 4 is connected to a gate metal electrode 6, and a gate pad opening 8 opened in a final passivation film 11 (polyimide film) is provided at the center of the gate metal electrode 6. Inside the gate wiring 4 is a source metal electrode 5 that occupies most of the upper surface of the chip, and a little inside the outer edge is the outer edge of the cell region 9. In the central portion of the source metal electrode 5, there is a source pad opening 7 opened in the final passivation film 11 (polyimide film). Since the cell region 9 has a repetitive structure with the same period, FIG. 2 shows an enlarged top view of a part of the cell region 9 cut out, that is, the cell region cutout part R1.

  As shown in FIG. 2, the cell region 9 has a continuous translation property (linear structure) in the vertical direction, and the cell region repetition period T1 is set as a period (gate pitch) in the horizontal direction. It has translational nature (repetitive structure). A linear trench gate electrode 12 and a linear field plate electrode 20 are provided in the linear trench 22. A linear N + source region 14 is provided on both sides of the linear trench gate electrode 12, and a P + body contact region 15 is provided between the pair of linear trench gate electrodes 12. A linear contact groove 24 is provided along the central portion of the P + body contact region 15.

  Next, the cross-sectional structure of the cell region 9 will be described with reference to FIG. 3, which is a cross-sectional view taken along the line X-X ′ of FIG. As shown in FIG. 3, there is an N + silicon single crystal substrate region 1 s on the back surface 1 b side of the semiconductor substrate 1, and a back surface metal drain electrode 13 (semiconductor substrate) as a metal drain electrode is formed on the back surface 1 b of the semiconductor substrate 1. From the side closer to 1, for example, there is a titanium layer 100 nm / nickel layer 200 nm / gold layer 100 nm). An N− drift region 16 (for example, a silicon epitaxial region) is present on the substrate surface 1a side of the N + silicon single crystal substrate region 1s, and a P-type channel region 17 (P− body region) is disposed thereon. There is an N + source region 14 on the substrate surface 1 a side of the P− body region 17, penetrating through the N + source region 14 and the P− body region 17 from the substrate surface 1 a side and inside the N− drift region 16. There is a trench 22 leading to it. In each trench 22, there is an N + polysilicon field plate electrode 20 (a field plate electrode 20 g connected to the gate or gate potential), and a field plate-gate insulating film 29 above the N + polysilicon field plate electrode 20. There is an N + trench gate electrode 12 through. The lower and lateral periphery of the N + polysilicon field plate electrode 20 is surrounded by a field plate peripheral insulating film 19, and gate insulating films 18 are present on both side surfaces of the N + trench gate electrode 12. The upper side of the N + trench gate electrode 12 is capped with an interlayer insulating film 10, and penetrates through the interlayer insulating film 10 and the N + source region 14 to reach the P + body contact region 15 inside the P-type channel region 17. There are 24. A barrier metal film 5b such as a TiW film is formed on the inner surface of the contact groove 24 and the upper surface of the interlayer insulating film 10, and relatively thick aluminum is formed in the contact groove 24 and on the upper surface of the interlayer insulating film 10. A system source metal film 5a is formed. A tungsten plug 34 is embedded in the contact groove 24.

  Here, the trench interval W in FIG. 3 should be about 1.5 micrometers or less in order to enjoy the effect of the accumulation layer current. Moreover, in order to fully exhibit the effect of the accumulation layer current, the trench interval W should be about 1.3 micrometers or less. Furthermore, in order to make maximum use of the effect of the accumulation layer current, the trench interval W should be about 1.2 micrometers or less. Here, in any case, the lower limit value of the trench interval W is considered to be, for example, about 0.1 micrometers in order to balance with other related technologies (see FIG. 26). Details of this will be described in Section 3.

  Next, in order to explain the extraction of the N + trench gate electrode 12n to the outside and the connection with the N + polysilicon field plate electrode 20, the Y′-Y cross section (FIG. 4) and the Y ″ -Y cross section of FIG. (FIG. 5) will be described based on FIG. 4 and FIG. As shown in FIG. 4, the cell of the N + trench gate electrode 12 is placed on the outside lead-out portion of the N + polysilicon field plate electrode 20 extending on the field insulating film 25 through the field plate-gate insulating film 29. An outside lead portion is formed, and is connected to the gate wiring 4 (by the same layer as the source metal electrode) through the trench gate electrode-gate wiring connecting portion 27. On the other hand, as shown in FIG. 5, the lead-out portion of the N + polysilicon field plate electrode 20 and the gate wiring 4 are connected to each other via a field plate-gate wiring connecting portion 28. As a result, the N + polysilicon field plate electrode 20 and the N + trench gate electrode 12 are indirectly electrically connected via the gate wiring 4.

  As shown in FIG. 4 or FIG. 5, the end principal surface of the chip 2 has an outermost peripheral N + region 26 (made by the same process as that of the source region). There is a layer polysilicon guard ring 3. The polysilicon guard ring 3 is electrically connected to the outermost peripheral N + region 26 through the corner portion aluminum-based wiring 30 (same layer as the gate wiring) (the outermost peripheral N + region 26 has the same potential as the drain potential). Is at potential). The inner region of the first main surface 1a of the chip 2 is covered with a final passivation film 11 such as a polyimide film.

2. Description of main part of wafer process of double gate type N-channel power MOSFET in trench according to one embodiment of the present application (mainly FIGS. 6 to 23)
6 is a device cross-sectional process flow diagram (trench processing hard mask film patterning step) corresponding to the XX ′ cross-section of FIG. 2 of the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 7 is a device cross-sectional process flow diagram (trench processing step) corresponding to the XX ′ cross section of FIG. 2 of the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 8 is a device sectional process flow diagram (field plate peripheral insulating film forming step) corresponding to the XX ′ section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 9 is a device cross-sectional process flow diagram (polysilicon film forming step for field plate electrode) corresponding to the XX ′ cross-section of FIG. 2 of the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application. . FIG. 10 is a device cross-sectional process flow diagram (field plate processing step) corresponding to the XX ′ cross-section of FIG. 2 of the double gate N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 11 is a device cross-sectional process flow diagram (field plate peripheral insulating film etch-back step) corresponding to the XX ′ cross-section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 12 is a device cross-sectional process flow diagram (gate insulating film forming step) corresponding to the XX ′ cross-section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 13 is a device cross-sectional process flow diagram (polysilicon film forming process for gate electrode) corresponding to the XX ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 14 is a device cross-sectional process flow diagram (gate electrode patterning step) corresponding to the XX ′ cross-section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 15 is a device cross-sectional process flow diagram (N-channel region forming step) corresponding to the XX ′ cross-section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 16 is a device cross-sectional process flow diagram (N + source region forming step) corresponding to the XX ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 17 is a device cross-sectional process flow diagram (interlayer insulating film forming step) corresponding to the XX ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. 18 is a device cross-sectional process flow diagram (contact hole forming step) corresponding to the XX ′ cross-section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 19 is a device cross-sectional process flow diagram (contact hole extension and N + body contact region forming step) corresponding to the XX ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. . FIG. 20 is a device cross-sectional process flow diagram (barrier metal film forming step) corresponding to the XX ′ cross-section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 21 is a device cross-sectional process flow diagram (aluminum-based source metal electrode film forming step) corresponding to the XX ′ cross-section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 22 is a device cross-sectional process flow diagram (polyimide final passivation film formation step) corresponding to the XX ′ cross-section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 23 is a device cross-sectional process flow diagram (gate pad opening and source pad opening forming step) corresponding to the XX ′ cross section of FIG. 2 of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application. Based on these, the main part of the wafer process of the double gate N-channel power MOSFET in the trench according to the embodiment of the present application will be described.

  Here, a 200 phi low resistance N + type silicon single crystal wafer 1 s (silicon wafer) and a high resistance N − type epitaxial layer 1 e (epitaxial layer has a thickness of about 60 volts, for example) In this example, the N-type epitaxial wafer 1 on which about 6.5 micrometers and the specific resistance are about 0.5 Ωcm, for example, is used as a raw material wafer (the wafer thickness is about 500 to 900 micrometers, for example). As will be described, the diameter of the wafer may be 300 phi, 450 phi, or others. If necessary, it may be a P-type epitaxial wafer, a semiconductor wafer other than silicon, or a substrate.

First, as shown in FIG. 6, a silicon oxide film 21 having a thickness of, for example, about 450 nm is formed on substantially the entire device surface 1a of the wafer 1 by, for example, low pressure CVD (Chemical Vapor Deposition). The silicon oxide film 21 is patterned by, for example, ordinary lithography to form a trench processing hard mask film 21. As an etching gas system, for example, a mixed gas system of Ar, C ₄ F ₈ , O ₂ or the like can be exemplified as a suitable one.

Next, as shown in FIG. 7, using the trench processing hard mask film 21, a trench 22 having a depth of, for example, about 3 micrometers is formed by anisotropic dry etching. As an etching gas system, for example, a gas system such as Cl ₂ , O ₂ system, and HBr system can be exemplified as a preferable one.

  Next, as shown in FIG. 8, a silicon oxide film (for example, a thickness of about 200 nm) to be the field plate peripheral insulating film 19 is formed on the inner surface of the trench 22 and the device surface 1a of the wafer 1 by, for example, thermal oxidation. To do.

  Next, as shown in FIG. 9, highly concentrated phosphorus-doped polysilicon having a thickness of, for example, about 600 nm, which is to become the field plate electrode 20 by CVD or the like, for example, in the trench 22 and almost the entire device surface 1a of the wafer 1. A layer (first layer polysilicon film) is formed.

Next, as shown in FIG. 10, the high concentration phosphorus-doped polysilicon layer 20 is etched back from the main surface of silicon by, for example, about 1.4 micrometers by dry etching using an etching gas such as SF _6. To do.

  Next, as shown in FIG. 11, for example, wet etching is performed using a hydrofluoric acid-based silicon oxide etching solution or the like, so that the upper end portion 38 of the field plate electrode 20 and the Si sidewall of the trench 22 are exposed to the extent that the field is exposed. The plate peripheral insulating film 19 is removed.

  Next, as shown in FIG. 12, a gate insulating film 18 (silicon oxide film) having a thickness of about 50 nm is formed by, eg, thermal oxidation. At the same time, a field plate-gate insulating film 29 (about 100 nm thick) is formed.

  Next, as shown in FIG. 13, the N + trench gate electrode 12 (trench gate polysilicon layer), for example, having a thickness of 600 nm is to be formed in the trench 22 and almost the entire device surface 1a of the wafer 1 by, for example, CVD. A high-concentration phosphorus-doped polysilicon layer (second-layer polysilicon film) is formed.

Next, as shown in FIG. 14, the high concentration phosphorus-doped polysilicon layer 12 is etched back so as to expose the main surface of silicon, for example, by dry etching using an etching gas such as SF ₆ .

Next, as shown in FIG. 15, the device surface 1a side of the wafer 1 is covered with a channel-implanted silicon oxide film 23, for example, by thermal oxidation or the like. Subsequently, boron ions are implanted into the entire surface of the cell region 9 to form a P-type channel region 17 (P-body region). Examples of ion implantation conditions include ion species: boron, implantation energy: about 50 keV to 100 keV, and concentration: about 8 × 10 ¹² / cm ² to about 3 × 10 ¹³ / cm ² . Thereafter, unnecessary thermal oxidation 23 is removed.

Next, as shown in FIG. 16, an N + source region 14 is formed by ion-implanting N-type impurities into the entire surface of the cell region 9. Examples of ion implantation conditions include ion species: arsenic, implantation energy: about 50 keV to 150 keV, and concentration: about 2 × 10 ^{15 to} 9 × 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 17, an interlayer insulating film 10 is formed on almost the entire device surface 1 a of the wafer 1. As the interlayer insulating film 10, for example, an insulating film made of a PSG (Phospho-Silicate Glass) film (for example, a thickness of about 250 to 450 nm) can be exemplified as a preferable example. For example, another insulating film (for example, a silicon oxide SOG film) may be stacked on the upper layer of the PSG film or the like.

  Next, as shown in FIG. 18, an anti-etching mask pattern such as a resist film is formed on the device surface 1a of the wafer 1 by ordinary lithography, and anisotropic dry etching is performed using the mask pattern as a mask. Thus, a contact hole 24 (contact groove) is opened.

Next, as shown in FIG. 19, the contact trench 24 is extended to a position deeper than the N + source region 14 by anisotropic dry etching (for example, a depth of about 0.35 micrometers). Subsequently, P-type impurities are ion-implanted into the bottom of the extended contact trench 24 to form the P + body contact region 15 in a self-aligning manner. Examples of ion implantation conditions include ion species: BF ₂ , implantation energy: about 20 to 50 keV, and concentration: about 1 × 10 ^{15 to} 8 × 10 ¹⁵ / cm ² .

  Next, as shown in FIG. 20, for example, a lower Ti film (for example, about 40 nm in thickness) and an inner surface of the contact groove 24 and almost the entire device surface 1a of the wafer 1 are formed by sputtering film formation, for example. A barrier metal film 5b made of an upper TiN film (for example, about 100 nm thick) or the like is formed. As the barrier metal film, TiW and others other than the Ti / TiN system shown here can be exemplified as suitable ones.

  Next, as shown in FIG. 21, a tungsten film (for example, a thickness of about 300 nm) is formed on almost the entire device surface 1a of the wafer 1 by CVD. Subsequently, the tungsten film is etched back by dry etching to leave the tungsten film in the contact groove 24 (see FIG. 20), thereby forming a tungsten plug 34.

  Next, for example, by sputtering film formation, aluminum is a main component (for example, several percent silicon added, the rest is aluminum) on the inner surface of the contact groove 24 and almost the entire device surface 1a of the wafer 1. A system source metal film 5a (for example, a thickness of about 3.5 to 5.5 micrometers) is formed. Subsequently, the source metal electrode 5 composed of the aluminum-based source metal film 5a and the barrier metal film 5b is patterned by ordinary lithography.

  Next, as shown in FIG. 22, as the final passivation film 11, for example, an organic film containing polyimide as a main component (for example, a thickness of about 2.5 micrometers) or the like is almost the entire device surface 1a of the wafer 1. Apply to.

  Next, as shown in FIG. 23, the source pad opening 7 and the gate pad opening 8 in FIG. 1 and the final passivation film 11 in the peripheral portion of the chip 2 shown in FIGS. To do.

  Next, as shown in FIG. 3, a back grinding process is performed on the back surface 1b of the wafer 1, so that, for example, a wafer thickness of about 500 to 900 micrometers is required, for example, about 300 to 30 micrometers. Thin film. Thereafter, the back electrode 13 is formed by sputtering film formation, for example. Further, the wafer 1 is divided into individual chips 2 by dicing or the like.

3. Detailed description of an in-trench double gate type N-channel power MOSFET (gate connection type) according to an embodiment of the present application (mainly FIGS. 24 to 31)
The explanation in this section is a supplementary explanation to the matters explained in the preceding section, and its mechanism and the like will be explained focusing on a more detailed explanation of the device structure in FIG. In the following, as in the preceding section, a specific description will be given by taking an example centering on a device having a source-drain breakdown voltage of about 60 volts.

  FIG. 24 is a detailed sectional view showing a more detailed structure of the device section corresponding to FIG. FIG. 25 is a data plot diagram showing the cell pitch dependence of the on-resistance in the in-trench double gate N-channel power MOSFET according to the embodiment of the present application. FIG. 26 is a data plot diagram showing the dependency of on-resistance on the trench spacing in the double-gate N-channel power MOSFET in the trench according to the embodiment of the present application. FIG. 27 shows the simulation result of the electron density distribution in the cell portion of the double-gate N-channel power MOSFET in the source-connected trench as a comparative example. FIG. 28 shows the simulation result of the electron density distribution in the cell portion of the double-gate type N-channel power MOSFET in the gate connection type trench according to the embodiment of the present application. FIG. 29 shows a simulation result of the current density distribution in the cell portion of the double-gate N-channel power MOSFET in the source-connected trench as a comparative example. FIG. 30 is a simulation result of the current density distribution in the cell portion of the double-gate N-channel power MOSFET in the gate-connected trench according to the embodiment of the present application. FIG. 31 is a data plot diagram showing the gate-source voltage dependency of the gate-source current in the cell portion of the double-gate N-channel power MOSFET in the gate-connected trench in the gate-connected trench according to the embodiment of the present invention as a comparative example. It is. Based on these, the details of the double gate type N-channel power MOSFET in the trench according to the embodiment of the present application will be described.

  FIG. 24 illustrates a detailed shape and typical main dimensions of the cell portion corresponding to FIG. As shown in FIG. 24, in this example, the cell region repetition period T1 (cell pitch) is, for example, about 1.5 micrometers, the trench depth TD is, for example, about 3 micrometers, and the trench width TW. Is, for example, about 0.75 micrometers, and the trench interval W is, for example, about 0.75 micrometers. The gate depth GD (intrinsic gate depth) occupying the trench depth TD is, for example, about 1.6 micrometers, and the gate width GW is, for example, about 0.65 micrometers. The contact width CW is, for example, about 0.3 micrometers, and the contact trench interval CT is, for example, about 0.2 micrometers. Further, as described above, the wafer or chip thickness WT after back grinding is, for example, about 30 to 300 micrometers, and the thickness ET of the epitaxial layer is, for example, about 6.5 micrometers. It is. Further, the field plate width PW is, for example, about 0.15 micrometers, and the trench taper angle θ is, for example, about 89 to 90 degrees. The gate insulating film thickness GT (film thickness of the second insulating film) is, for example, about 0.05 micrometers (50 nm), and the field plate insulating film thickness PT (film thickness of the first insulating film) is It is thicker, for example, about 0.2 micrometers, and the field plate width PW is, for example, about 0.15 micrometers.

  As can be seen from FIG. 24, the upper end portion 38 of the field plate electrode tends to be sharpened for miniaturization, but in this example (formed in the same layer as the gate insulating film or in the same process). The field plate-gate insulating film (second insulating film) 29 is about the same thickness as the gate insulating film 18 or slightly thicker than the field plate peripheral insulating film (first insulating film) 19. It is considerably thin. However, since the field plate electrode 20 (20 g) is set to substantially the same potential, leakage due to dielectric breakdown or the like becomes a problem between the field plate electrode 20 and the gate electrode 12 as in the source connection type. Absent.

  Next, the behavior of the on-resistance characteristics will be described by narrowing the current path (mainly the drift region) between the trenches (narrowing the trench interval W). FIG. 25 shows the cell pitch dependence of the on-resistance characteristics of a gate-connected in-trench double gate type power MOSFET. Here, the on-resistance value is normalized by the on-resistance of the source-connected double gate type power MOSFET in the trench having the same cell structure. In FIG. 25, in the region where the cell pitch is 2 micrometers or less, in the gate-connected in-trench double gate type power MOSFET, the effect of decreasing the on-resistance due to the increase in the total gate width due to the miniaturization of the device is It appears to be much larger than the double-gate power MOSFET in the trench. This is presumably because in the gate-connected in-trench double gate power MOSFET, an accumulation layer (a layer having a high electron concentration) is formed along the interface with the trench on both sides of the drift region. That is, it is presumed that the slope of the graph line suddenly increases because the storage layer current flowing through this storage layer becomes dominant rapidly.

  Here, the parameter of the cell pitch T1 is a physical quantity that depends on the specific structure of the cell, and a more essential parameter, that is, the trench interval W (more precisely, the trench interval near the lower end of the intrinsic gate electrode). FIG. 26 is a rewrite of FIG. 25 for the horizontal axis. As can be seen from FIG. 26, when the trench spacing W is 1.5 micrometers (the trench spacing upper limit W1 at which the effect of the accumulation layer current starts to become noticeable) or less, the slope of the graph line rapidly becomes steep. This tendency becomes more conspicuous when the trench interval W is 1.3 micrometers (the upper limit of the trench interval W2 at which the effect of the accumulation layer current starts to become dominant) or less, and the trench interval W is 1.2 micrometers (the accumulation layer). Below the upper limit of the trench interval W3) where the effect of current is dominant, it converges to a substantially steep processing line.

  From the conventional recognition, if only a single cell is considered, simply miniaturizing will cause an increase in on-resistance due to narrowing of the current path between the trenches. As a whole, the on-resistance is reduced by increasing the total gate width while keeping the total area of the cells substantially constant. However, as described above, the double gate type power MOSFET in the gate connection type trench is hardly affected by the narrowing of the current path due to the effect of the accumulation layer. It is effective to reduce the interval W at once. This includes not only miniaturization by uniform scaling, but also reducing only the trench interval W and the dimensions of the related parts, while leaving the other parts almost the same.

  The above points will be described in more detail. FIG. 27 is a simulation result of the electron density distribution in the cell portion of the source-connected double gate type power MOSFET in the trench having the same structure as the comparative example. FIG. 27 shows a region 31 having a high electron density, a region 32 having a medium electron density, and a region 33 having a low electron density. It can be seen that there is a break near the lower end.

  On the other hand, when the simulation result of the electron density distribution in the cell portion of the gate-connected in-trench double-gate N-channel power MOSFET according to the embodiment of the present application is seen, as shown in FIG. It can be seen that the channel region and the entire periphery of the trench are formed with a considerable thickness.

  Next, FIG. 29 shows a simulation result of the current density distribution of the cell portion corresponding to FIG. FIG. 29 shows a region 35 having a high current density, a region 36 having a medium current density, and a region 37 having a low current density. From this, in the double gate type power MOSFET in the source connection type trench, It can be seen that the accumulation layer current is extremely small, and the dominant current is borne by the bulk current flowing in a distributed manner in the drift region (epitaxial region) having a high resistance.

  On the other hand, as shown in FIG. 30, in the gate-connected in-trench double-gate N-channel power MOSFET according to one embodiment of the present application, the dominant current path is at the channel region and the subsequent interface with the trench. It can be seen that the current path is a low-resistance current path composed of a storage layer current path through the formed storage layer. Therefore, in the gate-connected in-trench double-gate N-channel power MOSFET according to the embodiment of the present application, the width of the epitaxial region between trenches having a low contribution to the entire current path, that is, the trench interval W is extremely narrow. However, the on-resistance is not easily affected by the narrowing of the current path. Also, in the gate-connected double gate type power MOSFET in the trench, particularly in a product group with a low source-drain breakdown voltage, the epitaxial layer is not so thick with respect to the trench depth. Even if the layer concentration is reduced, the on-resistance is unlikely to increase.

  Next, other advantages of the gate connection type will be described. FIG. 31 shows the gate-source breakdown voltage characteristics of the source connection type in-trench double gate power MOSFET of the same structure as the comparative example and the gate connection type in-trench double gate N-channel power MOSFET according to the embodiment of the present application. The measured value is shown. As can be seen from FIG. 31 (see FIG. 24), in the source connection type, the gate electrode 12 and the field plate electrode 20s (FIG. 27 or FIG. 29) have different potentials. See).

  On the other hand, in the gate connection type, since the gate electrode 12 and the field plate electrode 20g (FIG. 28 or FIG. 30) are at the same potential, the gate-source breakdown voltage is 20 volts or more (see solid line arrow). This is a common problem of the double-gate power MOSFET in the trench, as shown in FIG. 24, although it is difficult to increase the thickness of the field plate-gate insulating film 29 due to the process reason. This is because the upper end portion 38 of the field plate electrode 20g has a strong tendency to be sharp. That is, since the upper end portion 38 becomes sharp, when the gate electrode 12 and the field plate electrode 20s have different potentials, the breakdown voltage between the gate and the source is deteriorated at this portion.

4). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, an N channel type device has been specifically described as an example. However, the present invention is not limited thereto, and it goes without saying that the present invention can also be applied to a corresponding P channel type device. Yes.

  Moreover, in the said embodiment, although the example using doped polysilicon (Doped Poly-silicon) etc. was specifically demonstrated as a polysilicon member of each layer, this invention is not limited to it, both Alternatively, a non-doped polysilicon (Nondoped Poly-silicon) film may be applied, and necessary impurities may be added by ion implantation after the film formation. In this case, the degree of freedom in the process can be increased, for example, by forming a polysilicon diode for ESD protection as an optional device using non-doped polysilicon, but the process cost is increased. On the other hand, when doped polysilicon is used, the degree of process freedom is sacrificed somewhat, but a low-resistance polysilicon layer can be formed relatively easily.

  For example, in the above-described embodiment, the power MOSFET having the double gate structure in the trench has been described. However, the present invention can also be applied to, for example, an IGBT (Insulated Gate Bipolar Transistor) having the double gate structure in the trench.

1 Semiconductor substrate (semiconductor wafer)
DESCRIPTION OF SYMBOLS 1a The surface of a chip or a wafer 1b The back surface of a chip or a wafer 1e N-silicon epitaxial region 1s N + silicon single crystal substrate region 2 Semiconductor chip 3 Guard ring (second layer polysilicon guard ring)
4 Gate wiring (by the same layer as the source metal electrode) 5 Source metal electrode 5a Aluminum-based source metal film 5b Barrier metal film 6 Gate metal electrode 7 Source pad opening 8 Gate pad opening 9 Cell region 10 Interlayer insulating film 11 Final passivation film ( Polyimide film)
12 N + trench gate electrode 13 Back surface metal drain electrode 14 N + source region 15 P + body contact region 16 N- drift region 17 P-type channel region (P-type body region)
18 Gate insulating film (second insulating film)
19 Field plate peripheral insulating film (first insulating film)
20 field plate electrode 20g field plate electrode connected to gate potential 20s field plate electrode connected to source potential 21 hard mask film for trench processing 22 trench 23 silicon oxide film for channel implantation 24 contact hole (contact groove)
25 Field insulating film 26 Outermost peripheral N + region (corresponding to source region) 27 Trench gate electrode-gate wiring connecting portion 28 Field plate-gate wiring connecting portion 29 Field plate-gate connecting layer (same layer as gate insulating film) Insulating film (second insulating film)
30 Corner part aluminum-based wiring 31 Region with high electron density 32 Region with medium electron density 33 Region with low electron density 34 Tungsten plug 35 Region with high current density 36 Region with medium current density 37 Region with low current density 38 Upper end of field plate electrode CT contact trench spacing CW contact width ET epitaxial layer thickness GD gate depth GT gate insulating film thickness GW gate width PT field plate insulating film thickness PW field plate width R1 cell region cutout portion T1 cell region repetition Period TD Trench depth TW Trench width W Trench spacing W1 Upper limit of trench interval at which the effect of the storage layer current begins to become significant W2 Upper limit of trench interval at which the effect of the storage layer current starts to dominate W3 The effect of the storage layer current is dominant Become Upper limit of wrench spacing WT Wafer or chip thickness after backgrinding θ Angle formed with horizontal surface of trench sidewall (trench taper angle)

Claims (12)

Power MOSFET including:
(A) a silicon-based semiconductor substrate having one principal surface;
(B) a number of linear trenches provided in the first main surface;
Here, each linear trench has:
(B1) polysilicon linear field plate electrode;
(B2) A polysilicon linear gate electrode provided above the polysilicon linear field plate electrode,
Furthermore, where
(1) The polysilicon linear field plate electrode is connected to substantially the same potential as the polysilicon linear gate electrode,
(2) An interval between adjacent linear trenches of the multiple linear trenches is 1.5 micrometers or less and 0.1 micrometers or more.     In the power MOSFET of item 1, the polysilicon linear field plate electrode is electrically connected to the polysilicon linear gate electrode outside the linear trench.     In the power MOSFET of the item 2, the interval between the adjacent linear trenches of the plurality of linear trenches is 1.3 micrometers or less and 0.1 micrometers or more.     In the power MOSFET of the item 2, the interval between the adjacent linear trenches of the multiple linear trenches is 1.2 micrometers or less and 0.1 micrometers or more.     In the power MOSFET of item 3, the polysilicon linear field plate electrode is separated from the inner surface of each linear trench by a first insulating film.     5. In the power MOSFET of item 5, the polysilicon linear gate electrode is separated from the inner surface of each linear trench and the polysilicon linear field plate electrode by a second insulating film thinner than the first insulating film. ing.     In the power MOSFET of item 6, the power MOSFET is an N-channel power MOSFET. A power MOSFET manufacturing method including the following steps:
(A) a step of preparing a silicon-based semiconductor substrate having one principal surface;
(B) forming a large number of linear trenches on the first main surface;
(C) coating the inner surface of each linear trench with a first insulating film;
(D) burying a first polysilicon electrode to be a field plate electrode in each linear trench covered with the first insulating film;
(E) in each linear trench, removing the first insulating film on the inner surface of the upper half to expose the upper surface of the upper half and the upper end of the first polysilicon electrode;
(F) a step of covering the exposed inner surface of the upper half portion and the upper end portion of the first polysilicon electrode with a second insulating film;
(G) After the step (f), a step of embedding a second polysilicon electrode which is thinner than the first insulating film and is to become a gate electrode in the upper half of each linear trench;
here,
(1) The field plate electrode is connected to substantially the same potential as the gate electrode;
(2) The spacing between adjacent linear trenches of the multiple linear trenches is 1.5 micrometers or less and 0.1 micrometers or more.     In the power MOSFET manufacturing method according to the item 8, the field plate electrode is electrically connected to the gate electrode outside the linear trench.     In the power MOSFET manufacturing method according to the item 9, the interval between the adjacent linear trenches of the multiple linear trenches is 1.3 micrometers or less and 0.1 micrometers or more.     In the method for manufacturing a power MOSFET according to the item 9, an interval between adjacent linear trenches of the multiple linear trenches is 1.2 micrometers or less and 0.1 micrometers or more.     In the power MOSFET manufacturing method according to the item 9, the power MOSFET is an N-channel power MOSFET.

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