JP2012209330A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a power active element having an insulating gate such as a power MOSFET used for a power source such as a DC-DC converter or for switching of a power converter is required to reduce its gate capacitance as much as possible as the switching becomes faster, and to cope with this, a technique is thought to be effective which takes away a gate electrode at a portion that cannot be a channel to provide a split gate, but, in illustration with an N channel type power MOSFET as an example, an electric field concentrates on the end of a P-type body region to form a channel as a reaction, resulting in degraded punch through resistance.SOLUTION: Relating to a semiconductor device having a power active element containing an insulating gate such as a planer vertical power MOSFET, a field plate that extends in a trench, in short a trench field plate, is provided between split gates in an active cell.

Description

  The present invention is applied to a semiconductor device (or a semiconductor device related to an integrated circuit structure, such as a power MOSFET (Metal Oxide Field Effect Transistor)) or a MISFET (Metal Insulator Semiconductor Field Effect Transistor), etc. .

  Japanese Patent Laid-Open No. 1-291468 (Patent Document 1) has a split gate (Split Gate), in order to lower the on-resistance and suppress the short channel effect, at the upper end of the N-drift region. A planar-vertical power MOSFET or the like in which an N-type region having a higher concentration than the N-drift region is provided is disclosed.

  Japanese Patent Application Laid-Open Publication No. 2006-54483 (Patent Document 2) discloses a split gate having an N-type higher concentration than the N-drift region at the upper end of the N-drift region in order to improve the punch-through breakdown voltage. In a planar-vertical power MOSFET provided with a region, a technique is disclosed in which the N-type region is introduced in a self-aligned manner by ion implantation using a gate electrode as a mask for impurity introduction.

  Japanese Unexamined Patent Publication No. 2001-156294 (Patent Document 3) discloses a planar-vertical power MOSFET having a split gate and an intermediate gate connected to the source therebetween.

JP-A-1-291468 JP 2006-54483 A JP 2001-156294 A

  For example, a power system active element having an insulated gate such as a power MOSFET used for a power source such as a DC-DC converter or switching of a power conversion device has a gate capacitance (mainly a gate-drain capacitance) as the switching speed increases. ) Must be made as small as possible. For this purpose, it is effective to remove the portion of the gate electrode that does not become a channel and use it as a split gate. However, taking an N-channel power MOSFET as an example, as a reaction, the electric field concentrates at the end of the P-type body region that forms the channel, which causes problems such as a decrease in punch-through breakdown voltage.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a semiconductor device capable of high-speed switching.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, one invention of the present application is a semiconductor device having a power system active element having an insulated gate such as a planar-vertical power MOSFET, and extends in a trench between split gates in each active cell. A field plate, that is, a trench field plate is provided.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a semiconductor device having a power system active element having an insulated gate such as a planar-vertical power MOSFET, a trench field plate is provided in each active cell, so that a decrease in punch-through breakdown voltage can be suppressed. .

It is a schematic circuit diagram which shows the circuit structure of the DC-DC converter for computers which is the main application field of the semiconductor device of each embodiment of this application. 1 is an overall top view of a semiconductor chip of a power MOSFET that is an example of a semiconductor device according to an embodiment of the present application (unit cells are spread over the entire active cell region; displayed). It is a chip | tip schematic cross section corresponding to the X-X 'cross section of FIG. FIG. 3 is a simplified enlarged plan view of a unit active cell region 20 of FIG. 2. FIG. 5 is an enlarged detailed plan view of a unit active cell region partial cutout portion R3 of FIG. FIG. 6 is a partial cross-sectional view (unit active cell region) of the semiconductor chip corresponding to the A-A ′ cross section of FIG. 5. FIG. 3 is an enlarged top view of a gate electrode lead-out region R1 in FIG. 2. The active cell region of the semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (N-type low resistance region introducing step) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. FIG. 2 is a partial cross-sectional view of the active cell region of the semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (trench forming process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is. The semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 in the middle of the manufacturing process (gate oxidation and polysilicon film forming process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of an active cell area. A portion of the active cell region of the semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (patterning process such as gate electrode) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is sectional drawing. The active cell region of the semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (P-type body region introducing step) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view. The active cell region of the semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (interlayer insulating film forming process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view. A portion of the active cell region of the semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (source contact hole forming process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is sectional drawing. The active cell region of the semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (P-type body contact region introducing step) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. FIG. The active cell region of the semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (metal electrode film forming process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view. FIG. 3 is an enlarged top view of a gate electrode lead-out region cutout region R1 in FIG. 2 for explaining the structure of a modification (modification 1: field plate gate connection) of the gate lead-out portion of the semiconductor device according to the embodiment of the present application; . A semiconductor corresponding to the AA ′ cross section of FIG. 5 for explaining the structure of a modification of the cross-sectional structure of the semiconductor device of the embodiment of the present application (Modification 2: cell structure without an N-type low resistance region). It is a fragmentary sectional view (unit active cell field) of a chip. FIG. 5 is a partial cross-sectional view of a semiconductor chip corresponding to the AA ′ cross section of FIG. 5 for explaining the structure of a modification (Modification 3: polycide structure) of the cross-sectional structure of the semiconductor device of the embodiment of the present application. Active cell region). In the middle of a manufacturing process (a process for forming a gate oxide and a polysilicon film, etc.) for explaining an example of a manufacturing method corresponding to a modified example (modified example 3: polycide structure) of the cross-sectional structure of the semiconductor device according to the embodiment of the present application. 3 is a partial cross-sectional view of the active cell region of the semiconductor wafer corresponding to the BB ′ cross-section of FIG. FIG. 5 is a partial cross-sectional view of a semiconductor chip corresponding to the AA ′ cross section of FIG. 5 for explaining the structure of a modified example (modified example 4: deep trench) of the cross-sectional structure of the semiconductor device of the embodiment of the present application. Active cell region). 2B in FIG. 2 during the manufacturing process (trench forming process) for explaining an example of the manufacturing method corresponding to the modified example (modified example 4: deep trench) with respect to the cross-sectional structure of the semiconductor device of the embodiment of the present application. It is a fragmentary sectional view of the active cell area | region of the semiconductor wafer corresponding to a B 'cross section. In the middle of a manufacturing process (sacrificial oxidation and sacrificial polysilicon film forming step) for explaining an example of a manufacturing method corresponding to a modified example (modified example 4: deep trench) with respect to the cross-sectional structure of the semiconductor device of the one embodiment of the present application 3 is a partial cross-sectional view of the active cell region of the semiconductor wafer corresponding to the BB ′ cross-section of FIG. In the middle of the manufacturing process (sacrificial oxidation and sacrificial polysilicon film etch-back process) for explaining an example of the manufacturing method corresponding to the modification (modification 4: deep trench) to the cross-sectional structure of the semiconductor device of the one embodiment of the present application 3 is a partial cross-sectional view of the active cell region of the semiconductor wafer corresponding to the BB ′ cross-section of FIG. 2B in FIG. 2 in the middle of the manufacturing process (gate oxidation process) for explaining an example of the manufacturing method corresponding to the modified example (modified example 4: deep trench) of the cross-sectional structure of the semiconductor device according to the embodiment of the present application. It is a fragmentary sectional view of the active cell area | region of the semiconductor wafer corresponding to a B 'cross section. It is a schematic circuit diagram for demonstrating the structure of the modification (modification 5: high resistance field plate) with respect to the planar structure etc. of the semiconductor device of the said one Embodiment of this application. FIG. 5 is an enlarged top view of a gate electrode lead-out portion cutout region R1 in FIG. 2 for explaining the structure of a modification example (modification example 5: high resistance field plate) with respect to the planar structure and the like of the semiconductor device of the embodiment of the present application. . It is a terminal arrangement diagram of an IGBT (Insulated gate Bipolar Transistor) which is an example of another active device to which the embodiments and the like described in the present application are applied. FIG. 19 is a unit cell cross-sectional view of an IGBT which is an example of another active device to which the embodiments and the like described in the present application corresponding to FIG. 18 are applied. It is a schematic circuit diagram which shows the circuit structure of the DC-DC converter for computers which respond | corresponded to FIG. 1 for demonstrating the integration example to the one chip of various embodiment of this application, and also showed the detail of the circuit. FIG. 2 is a chip top surface layout diagram of an integrated power supply element in which main parts of the circuit elements in FIG. FIG. 32 is a chip partial schematic cross-sectional view corresponding to a Y-Y ′ cross section of FIG. 31. It is a package upper surface schematic diagram for demonstrating the integration example to the multichip module etc. of various embodiment of this application (The sealing resin of the upper surface is removed for easy viewing.). FIG. 6 is a partial cross-sectional view (unit active cell region) of a semiconductor chip corresponding to the A-A ′ cross section of FIG. 5 regarding a comparative example (a split gate type vertical power MOSFET having an N-type low resistance region and a planar type field plate). FIG. 35 is a data plot diagram showing the relationship between the comparative example corresponding to FIG. 34 and the breakdown voltage and the depth D of the N-type low resistance region in the embodiment of the present application (FIGS. 6 and 18).

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Semiconductor devices including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region provided in the semiconductor substrate and having a first conductivity type;
(C) an active region provided on the first main surface;
(D) a plurality of unit cell regions provided in the active region in plan view;
Here, each unit cell region penetrates the drift region from above the first main surface and has the following:
(D1) A first body having a second conductivity type opposite to the first conductivity type provided in the semiconductor substrate on the first main surface side of the drift region at a planar interval. A region and a second body region;
(D2) a first gate electrode and a second gate electrode provided on the first main surface of the semiconductor substrate with a space therebetween in a plane via a gate insulating film;
(D3) a trench provided in the drift region between the first body region and the second body region from the side of the first main surface of the semiconductor substrate;
(D4) a field plate electrode provided in the trench via a field plate peripheral insulating film;
(D5) an interlayer insulating film provided on the gate electrode and the field plate electrode;
(D6) a first source region having the first conductivity type provided on the first main surface side surface of the semiconductor substrate and in each of the first body region and the second body region; A second source region;
(D7) A metal source electrode provided on the first main surface of the semiconductor substrate so as to cover the interlayer insulating film.

2. In the semiconductor device according to the item 1, each unit cell region further includes:
(D8) Impurity concentration is higher than that of the drift region provided in the drift region between the first body region and the second body region in the first main surface side surface of the semiconductor substrate. A low resistance region having a high first conductivity type.

  3. In the semiconductor device according to the item 1 or 2, the depth of the low resistance region is shallower than any of the first body region and the second body region, and the depth of the trench is larger than that of the low resistance region. Also shallow.

  4). 3. In the semiconductor device according to the item 1 or 2, the depth of the low resistance region is shallower than any of the first body region and the second body region, and the depth of the trench is the first body region. It is deeper than both the region and the second body region.

  5). 5. In the semiconductor device according to any one of 1 to 4, the thickness of the bottom of the trench in the field plate peripheral insulating film is thicker than the gate insulating film.

  6). 6. In the semiconductor device as described above in any one of 1 to 5, the field plate electrode, the first gate electrode, and the second gate electrode are made of a polysilicon member.

  7). 6. In the semiconductor device as described above in any one of 1 to 5, the field plate electrode, the first gate electrode, and the second gate electrode have a polycide structure.

  8). 8. In the semiconductor device as described above in any one of 1 to 7, the field plate electrode is electrically connected to the metal source electrode.

9. The semiconductor device according to any one of 1 to 8 further includes the following:
(E) a metal gate electrode provided on the interlayer insulating film and electrically connected to the first gate electrode and the second gate electrode in each unit cell region;
(F) a polysilicon gate wiring that electrically connects the metal gate electrode and the first gate electrode and the second gate electrode of each unit cell region;
(G) polysilicon field plate wiring for electrically connecting the field plate electrode and the metal source electrode;
Here, the polysilicon field plate wiring has a higher electric resistance than the polysilicon gate wiring.

  10. 10. The semiconductor device according to any one of 1 to 9, wherein the semiconductor device is a power MOSFET.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of parts and sections for convenience, if necessary. However, unless otherwise specified, they are not independent from each other. Rather, each part of a single example, one of which is a partial detail of the other or a part or all of a modification. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Furthermore, in the present application, the term “semiconductor device” mainly refers to various transistors (active elements) alone, or mainly a resistor, a capacitor, etc. integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate). Things (including multi-chip modules). Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, typical examples of various single transistors include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors). Note that power active elements such as power MOSFETs described in the present application are normally-off type unless otherwise specified.

  In the present application, “semiconductor active element” refers to a transistor, a diode, or the like.

  Also, it is cumbersome to use the expression “MOS” and the expression “MIS” separately, and unless otherwise specified, the word “MOS” is used, including the case where an insulating film other than an oxide is used. The expression shall be used.

  The power MOSFETs are generally roughly classified into a lateral power MOSFET and a vertical power MOSFET. The vertical power MOSFET is classified into a trench gate-vertical power MOSFET and a planar-vertical power MOSFET depending on the presence / absence of a trench gate. Further, a planar-vertical power MOSFET having a split gate is referred to as a split gate planar vertical power MOSFET. A device mainly dealt with in the present application is a semiconductor device having a power system active element having an insulated gate such as a split gate-planar-vertical power MOSFET, and has a field plate extending in a trench, that is, a trench field plate. Is. Note that the planar type is considered to have a smaller gate parasitic capacitance than the trench gate type.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5). “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). The structure of the IGBT is such that a semiconductor region having a conductivity type opposite to the drift region is interposed on the drain side of a normal vertical power MOSFET. Therefore, the gate and the source are structurally almost the same as the vertical power MOSFET, but in practice, the portion corresponding to the terminal with the bipolar transistor is called the emitter terminal. Yes. However, in the present application, unless otherwise specified, each element of the IGBT corresponding to the source of the vertical power MOSFET is referred to as a “source region”, “source electrode”, and “source terminal”. To.

  7). Since a power system active element such as a power MOSFET generally has a structure in which a large number of unit cells are distributed over a wide range, even if it is referred to as an electrical resistance between one element and another element, which part of the element is determined. Unless specified, the value or relationship cannot be said accurately. Therefore, in the present application, the center position (geometric centroid) of the element in question is set as the position of the element, unless otherwise specified.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  For example, Japanese Patent Application Laid-Open No. 2007-228711 (or corresponding US Patent Publication No. 2010-253306) discloses a prior patent application by the present inventors regarding a DC-DC converter used for a computer power supply or the like. Japanese Unexamined Patent Publication No. 2009-22106 (or corresponding US Patent Publication No. 2009-15224), Japanese Unexamined Patent Publication No. 2010-16035 (or corresponding US Patent Publication No. 2010-1790) Etc.

1. Description of main application fields and the like of the semiconductor device of each embodiment of the present application (mainly FIG. 1)
The power MOSFETs and the like described in the following embodiments are exemplified mainly for a low-side switch in a DC-DC converter or the like, but these are used for other purposes (for example, a high-side switch of a similar circuit). Needless to say, it is also effective.

  FIG. 1 is a schematic circuit diagram showing a circuit configuration of a DC-DC converter for a computer, which is a main application field of the semiconductor device of each embodiment of the present application. Based on this, main application fields of the semiconductor device of each embodiment of the present application will be described.

  As shown in FIG. 1, a power supply to a microprocessor or the like in a PC (Personal Computer) or the like is normally a constant voltage source (DC power supply Vin ) Using a VRM (Voltage Regulator Module) such as the DC-DC converter 50, for example, at a low voltage of about 1 volt (currently, for example, about 20 amperes). This amount of current may exceed 100 amperes. For example, a switching signal of about 200 kHz (a typical range is about 300 kHz to about 500 kHz, and a range applied in the past and the near future is about 20 kHz to about 1 MHz) is sent from the control circuit unit 53 to the high side. Complementary pulse signals drive the high-side SW power MOSFET (Qhh) and the low-side SW power MOSFET (Qhl) through the driver 51 and the low-side driver 52, respectively. When the high-side SW power MOSFET (Qhh) is on, a current is supplied through the high-side SW power MOSFET (Qhh) and passes through a smoothing circuit including an output smoothing inductor 54, an output smoothing capacitor 55, and the like. The power supply output terminal Vdd and the ground terminal Vss are supplied to the microprocessor or the like. On the other hand, when the high-side SW power MOSFET (Qhh) is off, the low-side SW power MOSFET (Qhl) is on, and current is supplied through the current path from the low-side SW power MOSFET (Qhl) to the output smoothing inductor 54. . At this time, the voltage is controlled by the length of time during which the high-side SW power MOSFET (Qhh) is turned on. Accordingly, the high-side SW power MOSFET (Qhh) is required to have as low on-resistance characteristics as possible from the viewpoint of supplying a large current.

  On the other hand, since the low-side SW power MOSFET (Qhl) is a synchronous rectification switch that is turned on only when the high-side SW power MOSFET (Qhh) is off, a fast switching speed is required. In order to increase the switching speed, a split gate structure in which the gate electrode is divided and an intermediate portion is removed is effective. However, as a counter-action, there is a problem that the punch-through breakdown voltage deteriorates due to the concentration of the electric field at the end of the P-type body region as much as the field plate effect disappears in the middle part. In the embodiments of the present application, this is dealt with by a trench-type field plate.

2. Description of a power MOSFET structure (cell structure having a deep N-type low resistance region) which is an example of a semiconductor device according to an embodiment of the present application (mainly FIGS. 2 to 7)
In this section, an outline of the structure of the power MOSFET particularly adapted to the low-side switch described in section 1 (also corresponding to the low-side SW power MOSFET Qhl in FIG. 1) will be described.

  FIG. 2 is an overall top view of a semiconductor chip of a power MOSFET that is an example of a semiconductor device according to an embodiment of the present application (unit cells are spread over the entire active cell region. Only in the department). FIG. 3 is a chip schematic cross-sectional view corresponding to the X-X ′ cross section of FIG. 2. FIG. 4 is a simplified enlarged plan view of the unit active cell region 20 of FIG. FIG. 5 is an enlarged detailed plan view of the unit active cell region partial cutout portion R3 of FIG. FIG. 6 is a partial cross-sectional view (unit active cell region) of the semiconductor chip corresponding to the A-A ′ cross section of FIG. 5. 7 is an enlarged top view of the gate electrode lead-out region R1 in FIG. Based on these, the structure of a power MOSFET that is an example of a semiconductor device according to an embodiment of the present application will be described.

  First, the upper surface structure of the semiconductor chip will be described. As shown in FIG. 2, the peripheral end of the semiconductor chip 2 (for example, the chip size is about 2 mm in length, about 3 mm in width, and about 0.1 mm in thickness) has a ring shape around the end. A guard ring 27 (for example, composed of the same layer as the aluminum-based metal electrode film 30) is provided, and almost all of the inside thereof includes a gate wiring portion 24 and a metal source electrode 15 (these are also, for example, And the same layer as the aluminum-based metal electrode film 30). A part of the gate wiring portion 24 is a gate pad portion 25 for attaching a bonding wire or the like, and the vicinity of the center of the metal source electrode 15 is similarly a source pad portion 26 for attaching a bonding wire or the like. Yes. Also, as shown in FIG. 4, the upper surface main part of the semiconductor chip 2 below the metal source electrode 15 is mainly composed of a large number of unit cell regions 20 (for example, a unit cell repetition period, that is, a unit cell). The active region 12 (active cell region) is spread with a width of about 3 micrometers, for example, and a linear trench 5 is formed in the center thereof, for example.

Next, FIG. 3 shows a cross section taken along line XX ′ of FIG. As shown in FIG. 3, the lower half of the semiconductor chip 2 has, for example, a relatively high concentration first conductivity type, that is, an N-type semiconductor substrate region 1s (for example, an N-type single crystal silicon substrate, that is, an N-type drain region). N-epitaxial region 1e (for example, with a withstand voltage of 30 with a thickness corresponding to the required withstand voltage is formed on the front surface 1a (first main surface) side of the N-type semiconductor substrate region 1s, that is, on the opposite side of the back surface 1b. If the thickness is about volts, the thickness is about 2.5 micrometers, the additive impurity is, for example, phosphorus, and the concentration is, for example, about 4 × 10 ¹⁶ / cm ³ ). It corresponds to. The peripheral portion of the semiconductor chip 2 is mainly an edge termination region 28, and the active region 12 is almost occupied by the internal region of the semiconductor chip 2, and the active region 12 has a strip shape (three-dimensional) in plan view. A unit cell region 20 of a rectangular parallelepiped) is spread.

  Next, FIG. 5 shows the unit active cell region partial cutout portion R3 of FIG. 4, and FIG. 6 shows the A-A 'cross section thereof. As shown in FIGS. 5 and 6, the unit active cell 20 (in the plan view, a linear gate structure) is substantially symmetric, and the N-type semiconductor substrate region 1 s (N-type drain region) of the semiconductor chip 2. A back metal electrode 4 (for example, a drain electrode) is provided on the back surface 1b side, and an N − drift region 3 is provided on the front surface 1a side of the N-type semiconductor substrate region 1s. A pair of P-type body regions 9 (second conductivity type first and second body regions) are provided on the surface 1a side of the N-drift region 3 at a predetermined interval. A source region 11 (first and second source regions) and a P-type body contact region 14 are provided in the body region 9 and in the semiconductor surface region on the surface 1a side of the N− drift region 3. . Further, trench 5 shallower than P-type body region 9 (for example, a depth of about 0.65 μm) from the surface 1 a (first main surface) side of semiconductor substrate 2 toward the inside of N − drift region 3. (For example, a depth of about 0.45 μm and a width of about 0.3 μm) is provided, and the trench 5 is filled with a field plate poly via a gate insulating film 6 (for example, a thickness of about 30 nm). A silicon electrode 7c is provided. The field plate polysilicon electrode 7c is gate-insulated not only inside the trench 5 (trench portion 7ct of the field plate electrode) but also on the surface 1a (first main surface) of the semiconductor substrate 2 outside the upper portion of the trench 5. It extends through the membrane 6. On the surface 1a (first main surface) of the semiconductor substrate 2 on both sides of the field plate polysilicon electrode 7c, a pair of gate poly having a gate length of about 0.4 micrometers, for example, is interposed via a gate insulating film 6. A silicon electrode 7a (first and second gate electrodes) is provided. In this example, the gate polysilicon electrode 7a and the field plate polysilicon electrode 7c are patterned from an integral gate polysilicon film 7 (polysilicon member). On the surface 1a side of the N-drift region 3 between the pair of P-type body regions 9, an N-type low resistance region 40 (N-type well region) having a depth of, for example, about 0.55 micrometers is provided. The impurity concentration is higher than that of the N − drift region 3 and lower than that of the source region 11. Further, the depth D of the N-type low resistance region 40 is shallower than any depth of the pair of P-type body regions 9 and deeper than the trench 5 in this example.

  Further, an interlayer insulating film 8 is provided on the surface 1a side of the semiconductor substrate 2 so as to cover the gate polysilicon electrode 7a and the field plate polysilicon electrode 7c, and the entire active region 12 is formed thereon. A metal source electrode 15 (patterned from the aluminum-based metal electrode film 30 or the like) is formed so as to cover it. The metal source electrode 15 is electrically connected to the source region 11 and the P-type body contact region 14 via a source contact portion 29a (contact hole).

  FIG. 7 shows a detailed plan structure of the gate electrode lead-out region R1 in FIG. As shown in FIG. 7, the gate polysilicon film 7 constituting the trench gate electrode 7a constitutes a gate lead-out polysilicon wiring portion 7b outside the trench 5, and a metal is formed in the gate contact portion 29b. It is electrically connected to the gate wiring portion 24 (a part of the aluminum-based metal electrode film 30). On the other hand, in this example, each field plate polysilicon electrode 7c is connected to the metal source electrode 15 via the field plate contact portion 29c.

  According to such a structure, when viewed in the unit cell region 20, the equipotential surface in the N-drift region 3 is pushed down and becomes relatively flat by the effect of the field plate. As a result of alleviating the electric field concentration on the part, the punch-through breakdown voltage is improved. On the other hand, in such a structure, the point at which the electric field becomes maximum moves from the end of the P-type body region 9 to the trench portion 7ct of the field plate 7c, that is, the lower end of the trench field plate. Since the depth of 7 ct is shallower than the depth of the P-type body region 9, the possibility of excessive electric field concentration is relatively low.

  As described above, since the punch-through breakdown voltage is improved, it becomes easy to introduce the N-type low resistance region 40, thereby reducing the on-resistance. Here, the reason why the depth of the N-type low resistance region 40 is made shallower than the depth of the P-type body region 9 is to avoid undesired electric field concentration at the end of the P-type body region 9.

3. Description of an example of a manufacturing method for the semiconductor device according to the embodiment of the present application (mainly FIGS. 8 to 16)
In this section, an example of the manufacturing process of the device described in FIGS. 2 to 7 will be described.

  FIG. 8 shows a semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 in the middle of the manufacturing process (N-type low resistance region introducing process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of an active cell area. FIG. 9 shows an active cell region of the semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 in the middle of the manufacturing process (trench forming process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view. FIG. 10 corresponds to the BB ′ cross section of FIG. 2 in the middle of the manufacturing process (gate oxidation and polysilicon film deposition process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of an active cell field of a semiconductor wafer. FIG. 11 is an active cell of a semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 in the middle of the manufacturing process (patterning process such as gate electrode) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of a field. FIG. 12 shows an active semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (P-type body region introducing process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of a cell area. FIG. 13 shows an active semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (interlayer insulating film forming process) for explaining an example of the manufacturing method for the semiconductor device according to the embodiment of the present application. It is a fragmentary sectional view of a cell area. FIG. 14 is an active cell of a semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (source contact hole forming process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of a field. 15 shows a semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 in the middle of the manufacturing process (P-type body contact region introduction process) for explaining an example of the manufacturing method for the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of an active cell area. FIG. 16 shows an active semiconductor wafer corresponding to the BB ′ cross section of FIG. 2 during the manufacturing process (metal electrode film forming process) for explaining an example of the manufacturing method for the semiconductor device according to the embodiment of the present application. It is a fragmentary sectional view of a cell area. Based on these, an example of a manufacturing method for the semiconductor device according to the embodiment of the present application will be described.

  First, as shown in FIG. 8, for example, a 200φ N-type silicon single crystal wafer 1s with a plane orientation of (100) (a 300 phi, 450 phi, or other diameter wafer may be used as necessary. For example, the resistivity is about 1 to 2 mΩ · cm, the thickness is about 500 micrometers, for example, and the required breakdown voltage (here, the source / drain breakdown voltage is set to about 30 volts as an example) For example, an N-type (for example, phosphorus-doped, with a resistivity of, for example, about 0.1 to 0.3 mΩ · cm) silicon epitaxial layer of about 2 micrometers (within a range of, for example, about 1.3 to 3.3 micrometers) By depositing 1e (which is the portion that becomes the N-drift region 3), the wafer 1 with an epitaxial layer is obtained.

Next, for example, by ion implantation (including ion implantation and subsequent activation annealing), the surface 1a of the wafer 1 (opposite the first main surface or device surface, that is, the back surface 1b or the second main surface). The N-type low resistance region 40 (N-type well region) is formed by introducing N-type impurities almost over the entire surface. The ion implantation conditions at this time include, for example, ion species: phosphorus, implantation energy: about 200 keV, dose amount: about 1 × 10 ¹³ / cm ² , implantation method: vertical implantation (even if vertical, it is a minute within about 10 degrees The same applies to the following including the inclination). Note that the N-type low-resistance region 40 can also be formed by epitaxial growth. The impurity concentration in that case can be exemplified as a suitable value of about 2 × 10 ¹⁷ / cm ^3, for example.

  Next, a silicon oxide film having a thickness of, for example, about 450 nm is formed on substantially the entire device surface 1a of the wafer 1 by, for example, low pressure CVD (Chemical Vapor Deposition). The silicon oxide film is patterned by, for example, ordinary lithography to obtain a trench processing hard mask film.

  Next, as shown in FIG. 9, using a trench processing hard mask film, anisotropic dry etching (the etching atmosphere is, for example, a halogen-based gas atmosphere such as HBr) has a depth of 0.45 μm, for example. A trench 5 of about a meter (width of about 0.3 micrometer) is formed. Thereafter, the hard mask film for trench processing that has become unnecessary is entirely removed using, for example, a hydrofluoric acid-based etching solution.

Next, as shown in FIG. 10, a gate oxide film 6 (gate insulating film) of about 30 nm, for example, is formed on almost the entire device surface 1a of the wafer 1 and the inner surface of the trench 5 by thermal oxidation or the like. Subsequently, the gate polysilicon film 7 (for example, thickness) is formed by CVD (Chemical Vapor Deposition) or the like so as to cover the entire surface 1a side of the semiconductor wafer 1 on the gate oxide film 6 and fill the trench 5. A film of about 500 nm, for example, a phosphorus-doped polysilicon film and a phosphorus concentration of about 4 × 10 ²⁰ / cm ³ , for example, is formed. Further, a cap insulating film 35 (for example, a silicon oxide insulating film having a thickness of about 200 nm) is formed on almost the entire surface 1a side of the semiconductor wafer 1 on the gate polysilicon film 7 by, for example, CVD.

  Next, as shown in FIG. 11, by patterning the gate polysilicon film 7 (including the cap insulating film 35) by normal lithography, a gate polysilicon electrode 7a and a field plate polysilicon electrode 7c are formed.

Next, as shown in FIG. 12, the P-type body region introduction resist film 36 is patterned by normal lithography, and this is used as an ion implantation mask to ion implantation or the like to the surface 1a side of the semiconductor wafer 1. Is performed to introduce the P-type body region 9. As ion implantation conditions at this time, for example, ion species: boron, implantation energy: about 150 keV, dose amount: about 1 × 10 ¹³ / cm ² , implantation method: inclined implantation (injection is performed in four steps from four inclined directions) ) Can be illustrated as suitable.

Next, as shown in FIG. 13, the P-type body region introducing resist film 36 is patterned, and using this as an ion implantation mask, ion implantation or the like is performed on the surface 1a side of the semiconductor wafer 1. An N-type source region 11 is introduced. As ion implantation conditions at this time, for example, ion species: arsenic, implantation energy: about 70 keV, dose amount: about 3 × 10 ¹⁵ / cm ² , implantation method: vertical implantation can be exemplified as preferable examples. Thereafter, the P-type body region introducing resist film 36 is entirely removed by ashing or the like. Subsequently, an interlayer insulating film 8 is formed on almost the entire device surface 1a of the wafer 1 by, for example, CVD. As the interlayer insulating film 8, an insulating film made of a PSG (Phospho-Silicate Glass) film (for example, about 500 nm thick) can be exemplified as a suitable example.

  Next, as shown in FIG. 14, the contact opening resist film 37 is patterned by normal lithography, and anisotropic dry etching is performed using the resist film 37 as a mask to thereby form the source contact portion 29a (contact hole or contact). Open the groove. Subsequently, the contact groove 29a is extended deeper than the source region 11 by anisotropic dry etching (the etching amount is about 200 nm, for example). Thereafter, the contact opening resist film 37 is entirely removed by ashing or the like.

Next, as shown in FIG. 15, a P-type body is formed in the surface region of the semiconductor substrate in a self-aligned manner by, for example, ion implantation of P-type impurities from the surface 1a side of the semiconductor wafer 1 to almost the entire surface. Contact region 14 (P-type high-concentration contact impurity region) is introduced. As the ion implantation conditions, for example, ion species: BF ₂ , implantation energy: about 30 keV, and dose amount: about 1 × 10 ¹⁵ / cm ² can be exemplified as preferable ones.

  Next, as shown in FIG. 16, a TiW film having a thickness of, for example, about 300 nm (a large part of titanium in the TiW film is formed by sputtering film formation, for example, on almost the entire surface on the surface 1 a side of the semiconductor wafer 1. Subsequent heat treatment moves to the silicon interface to form silicide and contributes to improving contact characteristics, but these processes are complicated and are not shown in the drawing). In the same manner as described above, an aluminum-based metal film having a thickness of, for example, about 3 μm to 5 μm (several percent silicon) is formed on almost the entire surface of the semiconductor wafer 1 on the TiW film on the surface 1a side by, for example, sputtering. Etc. to which aluminum is added). The TiW film and the aluminum metal film constitute an aluminum metal electrode film 30. Thereafter, by patterning the aluminum-based metal electrode film 30 by normal lithography, as shown in FIG. 2, the metal source electrode 15, the gate wiring portion 24, the guard ring 27, and the like are formed. If necessary, subsequently, as a final passivation film, for example, an organic film containing polyimide as a main component (for example, about 2.5 micrometers in thickness) or the like is applied to almost the entire device surface 1a of the wafer 1. . Further, the final passivation film in portions such as the source pad opening 26 and the gate pad opening 25 in FIG. 2 is removed by ordinary lithography. Next, by performing a back grinding process on the back surface 1b of the wafer 1, for example, a wafer thickness of about 500 micrometers is required, for example, about 100 micrometers (the normal range is 30 to 300 micrometers). About). Thereafter, the back electrode 4 (for example, titanium film / nickel film / gold film from the side closer to the wafer) is formed by, for example, sputtering film formation. Further, the wafer 1 is divided into individual chips 2 (FIG. 2) by dicing or the like.

4). Structural description of a modified example (modified example 1: field plate gate connection) of the gate lead portion of the semiconductor device according to the embodiment of the present application (mainly FIG. 17)
In this section, a modification regarding the connection destination of the field plate electrode 7c will be described. Needless to say, the gate (dummy gate) lead-out structure of this section is applicable not only to the structure of FIG. 6, but also to the structure of FIG. 18, FIG. 19, FIG. 21, FIG. .

  17 is an enlarged top view of the gate electrode lead-out region cutout region R1 in FIG. 2 for explaining the structure of a modification (Modification 1: field plate gate connection) of the gate lead-out portion of the semiconductor device according to the embodiment of the present application. FIG. Based on this, the structure of a modified example (modified example 1: field plate gate connection) of the gate lead portion of the semiconductor device according to the embodiment of the present application will be described.

  This example is different from FIG. 7 in that the connection destination of the field plate electrode 7 c is the metal gate wiring portion 24. Specifically, as shown in FIG. 17, in this cell, the gate polysilicon electrode 7a and the field plate polysilicon electrode 7c are joined to the gate lead-out polysilicon wiring portion 7b. Therefore, the structure is simpler than that of FIG. However, in terms of characteristics, the effect as a field plate is weak compared to that of the source connection (FIG. 7), and there are demerits such as an increase in gate parasitic capacitance.

5. Structural description of a modification of the cross-sectional structure of the semiconductor device according to the embodiment of the present application (modification 2: a cell structure without an N-type low resistance region) (mainly FIG. 18)
The example in this section is a variation on the cell structure described in FIG. 6 (and FIG. 5).

  18 is a cross-sectional view taken along the line AA ′ of FIG. 5 for explaining the structure of a modification of the cross-sectional structure of the semiconductor device according to the embodiment of the present application (modification 2: a cell structure without an N-type low resistance region). It is a fragmentary sectional view (unit active cell area) of a corresponding semiconductor chip. Based on this, the structure of a modification (Modification 2: cell structure without an N-type low resistance region) of the cross-sectional structure of the semiconductor device of the one embodiment of the present application will be described.

  As shown in FIG. 18, the structure has no N-type low resistance region 40 as compared with that described in FIG. 6. Originally, by introducing the trench field plate 7ct, a disadvantageous element was introduced from the viewpoint of punch-through like the N-type low resistance region 40, and the on-resistance, which is another parameter, was reduced. Therefore, the N-type low-resistance region 40 can be omitted when it is not necessary to further reduce the on-resistance. This not only simplifies the process, but also has the advantage of eliminating the possibility of deterioration of the punch-through breakdown voltage due to the introduction of the N-type low resistance region 40.

  Regarding the manufacturing process, since the step of introducing the N-type low resistance region 40 is skipped in section 3, the above description is not repeated individually.

6). Structural description of a modification (modification 3: polycide structure) to the cross-sectional structure of the semiconductor device according to the embodiment of the present application (mainly FIG. 19)
The example of this section is a modification of the cell structure of the example of FIG. In this section, only the structure corresponding to FIG. 6 will be described, but it goes without saying that the present invention can also be applied to the structure of FIG. 18, FIG. 19, FIG. 21, FIG.

  FIG. 19 is a partial cross-sectional view of a semiconductor chip corresponding to the AA ′ cross-section of FIG. 5 for explaining the structure of a modification (Modification 3: polycide structure) of the cross-sectional structure of the semiconductor device according to the embodiment of the present application. It is a figure (unit active cell area | region). Based on this, the structure of a modified example (modified example 3: polycide structure) of the cross-sectional structure of the semiconductor device according to the embodiment of the present application will be described.

  As shown in FIG. 19, in this example, a silicide film 38 such as a tungsten silicide film is provided on the gate polysilicon electrode 7a, the gate lead-out polysilicon wiring portion 7b, and the field plate polysilicon electrode 7c. That is, since the electrode structure layers such as the gate polysilicon electrode 7a, the gate lead-out polysilicon wiring portion 7b, and the field plate polysilicon electrode 7c are formed of the polycide film 39, the access resistance reaching the electrode can be reduced. .

7). Description of an example of a manufacturing method for the semiconductor device of Modification 3 (mainly FIG. 20)
In this section, a method for manufacturing the device described in FIG. 19 will be described. However, most of the manufacturing process is the same as that described in Section 3 (FIGS. 8, 9, and 11 to 16), and only different parts (parts corresponding to FIG. 10) will be described below.

  FIG. 20 shows a manufacturing process (gate oxidation, polysilicon film, etc.) for explaining an example of a manufacturing method corresponding to a modified example (modified example 3: polycide structure) of the cross-sectional structure of the semiconductor device according to the embodiment of the present application. It is a fragmentary sectional view of the active cell area | region of the semiconductor wafer corresponding to the BB 'cross section of FIG. 2 in a film-forming process. Based on this, an example of a manufacturing method for the semiconductor device of Modification 3 will be described.

Following FIG. 9, as shown in FIG. 20, a gate oxide film 6 (gate insulating film) of, eg, about 30 nm is formed on almost the entire device surface 1a of the wafer 1 and the inner surface of the trench 5 by thermal oxidation or the like. . Subsequently, the gate polysilicon film 7 (for example, thickness) is formed by CVD (Chemical Vapor Deposition) or the like so as to cover the entire surface 1a side of the semiconductor wafer 1 on the gate oxide film 6 and fill the trench 5. About 300 nm, for example, a phosphorus-doped polysilicon film, and the phosphorus concentration is about 4 × 10 ²⁰ / cm ³ , for example. A silicide film 38 (eg, a thickness of about 200 nm) such as a WSi film is formed on substantially the entire surface 1a side of the semiconductor wafer 1 on the gate polysilicon film 7. Further, a cap insulating film 35 (for example, a silicon oxide insulating film having a thickness of about 200 nm) is formed on the entire surface 1a of the semiconductor wafer 1 on the silicide film 38 by, for example, CVD.

  Next, the process proceeds to the patterning process of the gate polysilicon film 7 (including the silicide film 38 and the cap insulating film 35) in FIG.

8). Structural Description of Modification Example (Modification Example 4: Deep Trench) to the Cross-Sectional Structure of the Semiconductor Device of the One Embodiment of the Present Application (Mainly FIG. 21)
In this section, a modification to the cell structure described in FIG. 6 will be described.

  FIG. 21 is a partial cross-sectional view of a semiconductor chip corresponding to the AA ′ cross-section of FIG. 5 for explaining the structure of a modification (Modification 4: deep trench) to the cross-sectional structure of the semiconductor device of the embodiment of the present application. It is a figure (unit active cell area | region). Based on this, the structure of a modified example (modified example 4: deep trench) of the cross-sectional structure of the semiconductor device according to the embodiment of the present application will be described.

  As shown in FIG. 21, the depth D (for example, about 0.55 μm) of the N-type low resistance region 40 is the same as that of FIG. However, it is characterized in that the depth of the trench 5 (for example, about 0.7 micrometers) is deeper than the depth of the P-type body region 9 (for example, about 0.65 micrometers). Furthermore, the thickness of the insulating film 43 at the bottom of the trench is thicker than the gate insulating film 6 (about 30 nm) at the channel portion. A preferable range of the thickness of the insulating film 43 at the bottom of the trench is, for example, about 60 nm to 120 nm.

  Here, the reason why the depth of the trench 5 is made deeper than the depth of the P-type body region 9 is to completely move the electric field concentration location to the lower end of the trench 5. For this reason, in order to withstand a high electric field, the thickness of the insulating film 43 at the bottom of the trench is increased.

9. Description of an example of a manufacturing method for the semiconductor device of Modification 4 (mainly FIGS. 22 to 25)
In this section, the manufacturing process of the device described in FIG. 21 will be described. However, most of the manufacturing process is the same as described in Section 3 (FIGS. 8 and 10 and a part of FIGS. 11 to 16). Only the corresponding part) will be described.

  FIG. 22 is a diagram in the middle of a manufacturing process (trench forming process) for explaining an example of a manufacturing method corresponding to a modified example (modified example 4: deep trench) with respect to the cross-sectional structure of the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of the active cell area | region of the semiconductor wafer corresponding to a BB 'cross section. FIG. 23 is an illustration of a manufacturing method (sacrificial oxidation and sacrificial polysilicon film) for explaining an example of a manufacturing method corresponding to a modified example (modified example 4: deep trench) of the cross-sectional structure of the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of the active cell area | region of the semiconductor wafer corresponding to the BB 'cross section of FIG. 2 in a film-forming process. FIG. 24 is a diagram illustrating a manufacturing method (sacrificial oxidation and sacrificial polysilicon film) for explaining an example of a manufacturing method corresponding to a modified example (modified example 4: deep trench) of the cross-sectional structure of the semiconductor device according to the embodiment of the present application. It is a fragmentary sectional view of the active cell area | region of the semiconductor wafer corresponding to the BB 'cross section of FIG. 2 in an etch back process. FIG. 25 is a diagram in the middle of a manufacturing process (gate oxidation process) for explaining an example of a manufacturing method corresponding to a modified example (modified example 4: deep trench) with respect to the cross-sectional structure of the semiconductor device of the one embodiment of the present application. It is a fragmentary sectional view of the active cell area | region of the semiconductor wafer corresponding to a BB 'cross section. Based on these, an example of a manufacturing method for the semiconductor device of Modification 4 will be described.

  Continuing to FIG. 8, as shown in FIG. 22, N-type low resistance is obtained by anisotropic dry etching (etching atmosphere is, for example, a halogen-based gas atmosphere such as HBr) using a trench processing hard mask film. For example, trench 5 having a depth of about 0.7 μm (width of about 0.3 μm) is formed so as to penetrate region 40. Thereafter, the hard mask film for trench processing that has become unnecessary is entirely removed using, for example, a hydrofluoric acid-based etching solution.

  Next, as shown in FIG. 23, a sacrificial silicon oxide film 41 of, eg, about 30 nm is formed on almost the entire device surface 1a of the wafer 1 and the inner surface of the trench 5 by thermal oxidation or the like. Subsequently, a sacrificial polysilicon film 42 (for example, a thickness of about 500 nm, for example, is formed by CVD or the like so as to cover almost the entire surface 1a side of the semiconductor wafer 1 on the sacrificial silicon oxide film 41 and fill the trench 5. A non-doped polysilicon film) is formed.

  Next, as shown in FIG. 24, the sacrificial silicon film 41 is used as an etching stop film, and the sacrificial polysilicon film 42 is, for example, wet-etched so that the remaining portion 42r of the sacrificial polysilicon film has a thickness of about 100 nm, for example. Etch back. Subsequently, the sacrificial silicon oxide film 41 is etched back using, for example, a hydrofluoric acid etching solution so that the sacrificial polysilicon film 41 remains only around the remaining portion 42r of the sacrificial polysilicon film (residual portion 41r of the sacrificial silicon oxide film).

  Next, as shown in FIG. 25, the remaining surface 42r of the sacrificial polysilicon film is completely oxidized by performing a thermal oxidation process on the device surface 1a side of the wafer 1, and the device surface 1a of the wafer 1 is also oxidized. A gate oxide film 6 (gate insulating film) of about 30 nm, for example, is formed on almost the entire surface and the inner surface of the trench 5 by thermal oxidation or the like. At this time, the insulating film 43 at the bottom of the trench is thicker.

  Thereafter, the process proceeds to the film forming process of the gate polysilicon film 7 of FIG.

10. Structural description of a modification example (modification example 5: high resistance field plate) to the planar structure of the semiconductor device of the one embodiment of the present application (mainly FIGS. 26 and 27)
In this section, a modification regarding the field plate electrode 7c of the device described in section 2 will be described. Needless to say, the examples described in this section can be applied to the structure of FIG. 6 as well as the structure of FIG. 18, FIG. 19, FIG. 21, or FIG.

  FIG. 26 is a schematic circuit diagram for explaining the structure of a modified example (modified example 5: high resistance field plate) with respect to the planar structure and the like of the semiconductor device according to the embodiment of the present application. FIG. 27 is an enlarged top view of the gate electrode lead-out region cutout region R1 in FIG. 2 for explaining the structure of a modification example (modification example 5: high resistance field plate) to the planar structure and the like of the semiconductor device according to the embodiment of the present application. FIG. Based on these, the structure of a modified example (modified example 5: high resistance field plate) of the planar structure of the semiconductor device of the one embodiment of the present application will be described.

  As shown in FIG. 26, in this example, only the field plate polysilicon electrode 7c (field plate electrode) in the gate polysilicon film 7 has a high resistance, and this portion substantially constitutes a snubber circuit. It acts as an additional resistance portion 34 (snubber resistance) and a field plate-drain capacitance CFD (snubber capacitance). With this configuration, when the high-side switch (high-side SW power MOSFET) is turned off, the surge voltage applied to the low-side SW power MOSFET (Qhl) can be reduced.

  As shown in FIG. 27, for example, the additional resistance portion 34 compares the field plate polysilicon electrode 7c with other gate polysilicon film 7 portions, that is, the gate polysilicon electrode 7a and the gate lead-out polysilicon wiring portion 7b. Thus, it can be realized by increasing the resistance.

As an example, for example, in the process of FIG. 10, a portion 44 (field plate) covered with an ion implantation mask film using non-doped polysilicon instead of a doped polysilicon film as shown in FIG. By making a difference in the dose amount of the ion implantation between the polysilicon electrode 7c) and the other part, the phosphorus concentration of the field plate polysilicon electrode 7c is, for example, about 4 × 10 ¹⁸ / cm ^3, and the phosphorus concentration in the other part May be about 4 × 10 ²⁰ / cm ^3, for example.

  Various methods for realizing the additional resistance portion 34 are conceivable. For example, in FIG. 27, only the field plate polysilicon electrode 7c in the vicinity of the field plate contact portion 29c has a high resistance. it can.

  Further, in the examples of sections 6 and 7 (polycide structure), it can be realized by not forming the silicide film 38 only on all or a part of the field plate polysilicon electrode 7c.

11. Description of application of various embodiments of the present application to IGBT (mainly FIG. 28 and FIG. 29)
The examples described so far have been specifically described mainly using power MOSFETs as an example, but it is needless to say that the concept of each embodiment can be applied to all insulated gate power system active elements. In addition to the power MOSFET, the insulated gate power system active element includes, for example, an IGBT (Insulated gate Bipolar Transistor), an insulated gate power system active element, a CMOS (Complementary Metal Oxide Semiconductor), or a CMIS (Complementary Semiconductor Metal). There is an integrated circuit or the like and an integrated power system device (next section or next section) integrated on a single chip. These will be briefly described below.

  FIG. 28 is a terminal layout diagram of an IGBT (Insulated gate Bipolar Transistor) which is an example of another active device to which the embodiments and the like described in the present application are applied. FIG. 29 is a unit cell cross-sectional view of an IGBT which is an example of another active device to which the embodiments and the like described in the present application corresponding to FIG. 18 are applied. Based on these, application of the various embodiments of the present application to the IGBT will be described.

  As shown in FIG. 28, each terminal of the IGBT is normally referred to as a circuit name in a pin-corresponding relationship with the bipolar transistor. The terminal corresponding to the base is the gate terminal G, the terminal corresponding to the emitter is the emitter terminal E, and the collector. The terminal corresponding to is the collector terminal C. From the structural and operational viewpoint, it is natural that the emitter terminal E is called the source terminal as a structural name.

  That is, as shown in FIG. 29, the IGBT is an N-type semiconductor having the same part R2 as the power MOSFET described in FIG. 18 (the cell structure may be FIG. 6, FIG. 19, or FIG. 21). A P-type collector region 18 is inserted between the back surface 1b side of the substrate region 1s and the back surface metal electrode 4 (collector electrode). Therefore, in the structural name, the source system portion, that is, the source region 11, the N-type substrate source region 11a, the poly-Si source region 11b, the metal source electrode 15, the source pad portion 26, the source contact portion 29a, etc. Can be used. Since the gate system part corresponds as it is, it can be used as it is.

  Needless to say, the example described in this section can be applied to the structure of FIG. 6 as well as the structure of FIG. 18, FIG. 19, FIG. 21, or FIG.

12 Description of examples of integration of various embodiments of the present application on one chip (mainly FIGS. 30 to 32)
In power system switching circuits, it is important to reduce parasitic inductance as the switching frequency increases. Integration of switch devices and their drivers on one chip (or integration into one package, that is, modularization) ) Or integration on a single chip by adding a control circuit to this is important. These will be described below.

  FIG. 30 is a schematic circuit diagram showing a circuit configuration of a DC-DC converter for a computer corresponding to FIG. 1 for explaining an example of integration in one chip of various embodiments of the present application and showing details of the circuit. There is (the circuit configuration is basically the same as that of FIG. 1). FIG. 31 is a chip top surface layout diagram of an integrated power supply element in which main parts of the circuit elements in FIG. 1 are integrated on a single chip. 32 is a schematic cross-sectional view of a chip portion corresponding to the Y-Y ′ cross section of FIG. 31. Based on these, application of various embodiments of the present application to an example of integration on one chip will be described.

  FIG. 31 shows an example of the top surface layout of the chip 2 of a one-chip DC-DC converter for personal computers (corresponding to FIG. 1), which is an example of an integrated power device. As shown in FIG. 31, on the device surface 1a of the chip 2, a high-side driver 51 (output) that drives a high-side SW power MOSFET (Qhh), a low-side SW power MOSFET (Qhl), and a high-side SW power MOSFET (Qhh). Voltage Vout as a reference voltage and driven by a high-voltage power supply Vh), a low-side driver 52 that drives a low-side SW power MOSFET (Qhl) (ground voltage Vss as a reference voltage and driven by a low-voltage power supply Vl), and high A control circuit unit 53 (for example, the circuit has a CMOS circuit configuration) for controlling the side driver 51 and the low side driver 52 is laid out. Here, specifically, the low-side SW power MOSFET (Qhl) is any of the power system active elements (insulated gate type power system active elements) described in FIG. 6, FIG. 18, FIG. 19, FIG. It is. Note that the high-side SW power MOSFET (Qhh) can also be composed of any of these.

  Next, a partial cross section (Y-Y 'cross section) of the active region 12 of the low side SW power MOSFET (Qhl) and the CMOS control circuit section 53 will be described with reference to FIG.

  As shown in FIG. 32, the one-chip type DC-DC converter is made, for example, on a P-type semiconductor substrate 1p. That is, for example, an N-epitaxial region 1e is provided on the surface 1a (first main surface or device surface) side of the P-type semiconductor substrate 1p (P-type semiconductor substrate region) by epitaxial growth or the like. An N + buried region 19 is provided near the boundary between the epitaxial region 1e and the P-type semiconductor substrate region 1p. A P + element isolation region 22 is provided in the N− epitaxial region 1e such as between the CMOS region Rc and the power MOS region Rh, and a field insulating film 23 (LOCOS type or STI type insulating film) is provided.

  Next, each device area will be described. In the region where the power MOS region Rh, that is, the power MOSFET (Qh) is formed, an N + drain extraction region 21 for extracting a drain or the like to the upper surface 1a of the chip 2 is provided, and a semiconductor on the upper surface 1a of the chip 2 is provided. In the surface region, a trench 5, a gate insulating film 6, a gate polysilicon electrode 7a, a field plate polysilicon electrode 7c, a P-type body region 9, a source region 11, a P-type body contact region 14 and the like are provided.

  On the other hand, in the CMOS region Rc, a P-well region 31p and an N-well region 31n are provided below the surface of the N-epitaxial region 1e on the upper surface 1a side of the chip 2, and N-type and N-well regions 31n are provided on these surface regions, respectively. A P-type source / drain region 32 is provided. Further, on the upper surface 1a of the chip 2, together with the N-type and P-type source / drain regions 32, a gate electrode 33 constituting an N-channel MOSFET (Qn) and a P-channel MOSFET (Qp) is provided. ing.

  As shown in FIG. 30, in this example (switch-driver-controller integrated circuit 57), a high-side SW power MOSFET (Qhh), a low-side SW power MOSFET (Qhl), a high-side driver 51, a low-side driver 52, and a control circuit Since the part 53 is integrated on one chip, there is a merit that the parasitic inductance accompanying the connection between the parts is greatly reduced. As an integration range, for example, as shown in FIG. 30 (switch-driver integrated circuit 56), a high-side SW power MOSFET (Qhh), a low-side SW power MOSFET (Qhl), a high-side driver 51, and a low-side driver. 52 may be sufficient.

  Needless to say, the example described in this section can be applied to the structure of FIG. 6 as well as the structure of FIG. 18, FIG. 19, FIG. 21, FIG.

13. Description of examples of integration in multi-chip modules and the like according to various embodiments of the present application (mainly FIG. 33)
In section 12, an example of integration on a single chip is shown, but the same effect can be obtained compared to mounting on a wiring board of individual packages, although there is a difference in degree even if integration is performed on a single module. be able to. Thus, this section describes an example of integration into a single module.

  FIG. 33 is a schematic top view of a package for explaining an example of integration in a multi-chip module or the like according to various embodiments of the present application (the sealing resin on the top surface is removed for easy viewing). Based on this, an example of integration in a multichip module or the like according to various embodiments of the present application will be described.

  As shown in FIG. 33, a high-side SW power MOSFET semiconductor chip (Qhh), a low side is placed on the metal wiring or leads (external terminals) 59 of a module (multi-chip package) corresponding to the switch-driver integrated circuit 56. A driver chip 58 in which an SW power MOSFET semiconductor chip (Qhl), a high-side driver 51 and a low-side driver 52 are integrated is mounted, and a bonding pad BP (or each source of the control circuit unit) is bonded by a bonding wire BW such as a gold wire. Electrical connection is made between the pad 26, the gate pad 25) and the metal wiring or lead 59 or the like. As external terminals of this module, for example, a switching signal input terminal PWM, a DC power supply terminal Vin, a high voltage power supply terminal Vh, a low voltage power supply Vl, a power supply output terminal Vout, a ground terminal Vss, and the like are provided.

  Note that, as an integration range, for example, as shown in FIG. 30 (switch-driver-controller integrated circuit 57), a high-side SW power MOSFET semiconductor chip (Qhh), a low-side SW power MOSFET semiconductor chip (Qhl), A driver chip 58 and a control circuit unit semiconductor chip 53 in which the high side driver 51, the low side driver 52, and the control circuit unit 53 are integrated may be used.

  Needless to say, the example described in this section can be applied to the structure of FIG. 6 as well as the structure of FIG. 18, FIG. 19, FIG. 21, FIG.

14 General consideration of the present application and supplementary explanation regarding each embodiment (mainly FIGS. 34 to 35)
FIG. 34 is a partial cross-sectional view of a semiconductor chip (unit active cell region) corresponding to the AA ′ cross-section of FIG. 5 relating to a comparative example (split-gate vertical power MOSFET having an N-type low-resistance region and a planar-type field plate). It is. FIG. 35 is a data plot diagram showing the relationship between the breakdown voltage and the depth D of the N-type low resistance region in the comparative example corresponding to FIG. 34 and the embodiment (FIGS. 6 and 18) of the present application. Based on these, a general consideration of the present application and a supplementary explanation regarding each embodiment will be given.

  FIG. 34 shows an active cell structure of a comparative example (split gate-planar-vertical power MOSFET having an N-type low resistance region and a planar field plate) for comparing device characteristics. As shown in FIG. 34, the structure is similar to the structure of FIG. 6 (split gate-planar-vertical power MOSFET having an N-type low-resistance region and a trench-type field plate), but the field plate is a planar type. Only the point is different. 6 shows the transition of the punch-through breakdown voltage when the depth D of the N-type low-resistance region 40 (corresponding to FIG. 18 when this is 0) is changed for this comparative example and the structure (embodiment) of FIG. 35. As shown in FIG. 35, in the comparative example, when the depth D of the N-type low resistance region 40 is increased in order to reduce the on-resistance, the breakdown voltage rapidly deteriorates. Below 6 micrometers, there is almost no degradation of pressure resistance. That is, in the range where the depth D of the N-type low-resistance region 40 is shallower than the depth of the P-type body region 9 (here, about 0.65 micrometers), there is almost no deterioration in breakdown voltage.

15. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the N channel device is mainly formed on the upper surface of the N epitaxial layer on the N + silicon single crystal substrate. However, the present invention is not limited thereto, and P + silicon A P channel device may be formed on the upper surface of the N epitaxial layer on the single crystal substrate.

  In the above-described embodiment, the power MOSFET has been specifically described as an example. However, the present invention is not limited thereto, and it is needless to say that the present invention can be applied to a bipolar transistor (including IGBT). Needless to say, the present invention can also be applied to a semiconductor integrated circuit device incorporating such power MOSFETs, bipolar transistors, and the like.

  In the above-described embodiments, devices mainly made on a silicon-based semiconductor substrate have been specifically described. However, the present invention is not limited thereto, and a GaAs-based semiconductor substrate, a silicon carbide-based semiconductor substrate, and a silicon nitride. Needless to say, the present invention can be applied almost as it is to a device made on a ride-type semiconductor substrate.

  In the above-described embodiment, the gate electrode or the like that uses a polysilicon film has been specifically described. However, the present invention is not limited thereto, and may be a polycide film, a silicide film, or the like. Needless to say.

  Further, in the above-described embodiment, the metal electrode and the aluminum-based metal film as the main constituent film have been specifically described. However, the present invention is not limited thereto, and titanium, tungsten, and the like are used. Needless to say, the present invention can also be applied to a film using a refractory metal film or a gold film as a main component film of a metal electrode.

  Further, in the above-described embodiment, the drift region constituted by a single conductivity type region has been specifically described. However, the present invention is not limited to this, and a superconducting region in which the opposite conductivity type regions are alternately replaced is described. Needless to say, the present invention can also be applied to one having a super-junction type drift region.

1 Wafer 1a Wafer or semiconductor chip surface (first main surface or device surface)
1b Back surface of wafer or semiconductor chip (second main surface)
1e N-epitaxial region 1p P-type semiconductor substrate region 1s N-type semiconductor substrate region (semiconductor substrate region of first conductivity type)
2 Semiconductor chip 3 N-drift region 4 Back metal electrode 5 Trench 6 Gate insulating film 7 Gate polysilicon film (gate electrode)
7a Gate polysilicon electrode (first and second gate electrodes)
7b Gate lead polysilicon wiring portion 7c Field plate polysilicon electrode (field plate electrode or dummy gate)
7ct trench portion of field plate electrode (or trench field plate)
8 Interlayer insulating film 9 P-type body region (second conductivity type first and second body regions)
11 N-type source region (first and second source regions)
DESCRIPTION OF SYMBOLS 12 Active area | region 14 P-type body contact area | region 15 Metal source electrode 18 P-type collector area | region 19 N + buried area | region 20 Unit cell area | region 21 N + drain extraction area | region 22 P + element isolation area | region 23 Field insulating film 24 Metal gate wiring part 25 Gate pad part 26 Source pad 27 Guard ring 28 Edge termination region 29a Source contact (contact hole)
29b Gate contact portion 29c Field plate contact portion 30 Aluminum-based metal electrode film 31p CMOS region P well region 31n CMOS region N well region 32 CMOS region source / drain region 33 CMOS region gate electrode, etc. 34 Additional resistor portion 35 Cap Insulating film 36 P-type body region introducing resist film 37 Contact opening resist film 38 Silicide film 39 Polycide film 40 N-type low resistance region (N-type well region)
41 Sacrificial silicon oxide film 41r Residual portion of sacrificial silicon oxide film 42 Sacrificial polysilicon film 42r Residual portion of sacrificial polysilicon film 43 Insulating film at bottom of trench 44 Part covered with ion implantation mask film 50 DC-DC converter 51 High side driver 52 Low-side driver 53 Control circuit section 54 Output smoothing inductor 55 Output smoothing capacitor 56 Switch-driver integrated circuit 57 Switch-driver-controller integrated circuit 58 Driver chip 59 Metal wiring or lead on package BP Bonding pad of control circuit section BW Bonding wire C Collector terminal CFD Field plate-drain capacitance D Depth of N-type low resistance region E Emitter terminal G Gate terminal PWM Switching signal input terminal Qh Power MO SFET
Qhh High-side SW power MOSFET
Qhl Low-side SW power MOSFET
N-channel MOSFET in Qn CMOS region
P-channel MOSFET in Qp CMOS region
R1 Gate electrode lead-out part R2 Structurally the same part as the power MOSFET R3 Unit active cell area part cut-out part Rc CMOS region Rh Power MOS region S Source terminal Vdd Power supply output terminal Vh Power supply of high side driver (or high voltage power supply)
Vin DC power supply (or input voltage)
Vl Low-side power supply (or low-voltage power supply)
Vout Power supply output terminal (or output voltage)
Vss ground terminal (or ground voltage)

Claims (10)

Semiconductor devices including:
(A) a semiconductor substrate having a first main surface and a second main surface;
(B) a drift region provided in the semiconductor substrate and having a first conductivity type;
(C) an active region provided on the first main surface;
(D) a plurality of unit cell regions provided in the active region in plan view;
Here, each unit cell region penetrates the drift region from above the first main surface and has the following:
(D1) A first body having a second conductivity type opposite to the first conductivity type provided in the semiconductor substrate on the first main surface side of the drift region at a planar interval. A region and a second body region;
(D2) a first gate electrode and a second gate electrode provided on the first main surface of the semiconductor substrate with a space therebetween in a plane via a gate insulating film;
(D3) a trench provided in the drift region between the first body region and the second body region from the side of the first main surface of the semiconductor substrate;
(D4) a field plate electrode provided in the trench via a field plate peripheral insulating film;
(D5) an interlayer insulating film provided on the gate electrode and the field plate electrode;
(D6) a first source region having the first conductivity type provided on the first main surface side surface of the semiconductor substrate and in each of the first body region and the second body region; A second source region;
(D7) A metal source electrode provided on the first main surface of the semiconductor substrate so as to cover the interlayer insulating film. In the semiconductor device according to the item 1, each unit cell region further includes:
(D8) Impurity concentration is higher than that of the drift region provided in the drift region between the first body region and the second body region in the first main surface side surface of the semiconductor substrate. A low resistance region having a high first conductivity type.     3. In the semiconductor device according to the item 2, the depth of the low resistance region is shallower than either the first body region or the second body region, and the depth of the trench is shallower than the low resistance region. .     In the semiconductor device according to the item 2, the depth of the low resistance region is shallower than both the first body region and the second body region, and the depth of the trench is equal to the first body region and the second body region. Deeper than any of the second body regions.     5. In the semiconductor device according to the item 4, the thickness of the bottom portion of the trench in the field plate peripheral insulating film is thicker than the gate insulating film.     In the semiconductor device of the item 1, the field plate electrode, the first gate electrode, and the second gate electrode are made of a polysilicon member.     In the semiconductor device of the item 1, the field plate electrode, the first gate electrode, and the second gate electrode have a polycide structure.     In the semiconductor device according to the item 1, the field plate electrode is electrically connected to the metal source electrode. The semiconductor device according to the item 1, further comprising:
(E) a metal gate electrode provided on the interlayer insulating film and electrically connected to the first gate electrode and the second gate electrode in each unit cell region;
(F) a polysilicon gate wiring that electrically connects the metal gate electrode and the first gate electrode and the second gate electrode of each unit cell region;
(G) polysilicon field plate wiring for electrically connecting the field plate electrode and the metal source electrode;
Here, the polysilicon field plate wiring has a higher electric resistance than the polysilicon gate wiring.     10. The semiconductor device according to item 9, wherein the semiconductor device is a power MOSFET.

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