CN111081705B - Monolithic integrated half-bridge power device module - Google Patents
Monolithic integrated half-bridge power device module Download PDFInfo
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- CN111081705B CN111081705B CN201911168608.4A CN201911168608A CN111081705B CN 111081705 B CN111081705 B CN 111081705B CN 201911168608 A CN201911168608 A CN 201911168608A CN 111081705 B CN111081705 B CN 111081705B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0814—Diodes only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Abstract
The invention relates to a monolithic integrated half-bridge power device module, and belongs to the technical field of semiconductors. The module comprises an isolation ring, a low-side power device surrounded by the isolation ring and a high-side power device positioned outside the isolation ring; the periphery of the low-side power device is in direct contact with one side of the isolation ring, and the periphery side of the high-side power device is in direct contact with one side of the isolation ring. The isolation ring is composed of a plurality of semiconductor drift regions which are alternately arranged and have different conductive types, the back of the isolation ring is etched and covered with an insulating medium protection region to form a groove, and the semiconductor regions on two sides of the isolation ring are electrically isolated. The isolation ring can effectively isolate high-side and low-side power devices integrated on the same chip so that their electrodes can be biased separately. Compared with a board-level integrated power device module and a single-package integrated power device module, the single-chip integration of the power device enables the occupied area of the module to be small, and meanwhile, parasitic inductance is small due to the short lead wires.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and relates to a monolithic integrated half-bridge power device module.
Background
The power device module is a functional module formed by combining power devices according to certain functions, is a core component in the fields of medium power and high power electronics, is widely applied to various occasions such as frequency conversion speed regulation, motor control and the like, and has the main functions of rectification and inversion. Typical power device modules include half-bridge circuit modules, single-phase full-bridge circuit modules, three-phase full-bridge circuit modules, multi-phase circuit modules, and the like. A half-bridge circuit module is one of the most common power device modules, also called half-bridge arm, or totem pole, and is generally composed of two sets of power devices, a high-side and a low-side. The single-phase full-bridge circuit module, the three-phase full-bridge circuit module and the multi-phase circuit module can be composed of a plurality of half bridge arms. Conventional power device modules have undergone the evolution from board-level integration to single-package integration, with the module size being continuously reduced and parasitic parameters such as lead inductance being continuously reduced.
The board-level integrated power device module is characterized in that packaged power devices are respectively welded on a printed circuit board, corresponding electrodes are connected through copper wires on the printed circuit board, and meanwhile, components such as a driving control circuit and the like are connected together through the copper wires to form a power electronic system. The disadvantage is that the module occupies a large area and volume, and the longer copper lines introduce larger parasitic inductance. The single-package integrated power device module packages different chips in one package, and sometimes includes a driving control chip. Because the distance between the chips is smaller, the size occupied by the module is greatly reduced. On the other hand, the device electrodes are connected by the lead wires, and the length of the lead wires is reduced, so that the parasitic inductance is reduced. However, due to factors such as electrical isolation and process, the chip-to-chip spacing cannot be reduced at will, and a certain safety distance must be maintained, so that the chip still occupies a large area. In order to further reduce the area, it is imperative to develop a monolithically integrated power device module. However, to realize monolithic integration of power devices, the isolation problem of power devices must be solved.
Disclosure of Invention
In view of the above, the present invention provides a monolithic half-bridge power device module, which provides a new isolation technique to effectively isolate the high-side and low-side power devices integrated on the same chip, so that their electrodes can be biased separately. The monolithic integration of the power device enables the occupied area of the module to be small, and meanwhile, the parasitic inductance is small due to the short lead. The power device module of the present invention is therefore particularly suitable for compact power electronic circuits and systems.
In order to achieve the purpose, the invention provides the following technical scheme:
the monolithic integrated half-bridge power device module comprises an isolating ring, a low-side power device surrounded by the isolating ring and a high-side power device positioned outside the isolating ring;
the periphery of the low-side power device is in direct contact with one side of the isolation ring, and the periphery side of the high-side power device is in direct contact with one side of the isolation ring.
Optionally, the isolation ring is formed by alternately arranging a plurality of semiconductor drift regions of the first conductivity type and a plurality of semiconductor drift regions of the second conductivity type, the outermost side is a drift region of the first conductivity type, and the drift regions of the two conductivity types are in direct contact with each other;
The bottom of the drift region of the first conduction type positioned at the outermost side is connected with a heavily doped semiconductor substrate region of the first conduction type, and the substrate region is covered with a metal region serving as a drain electrode;
etching the back of the isolation ring and covering the back with an insulating medium protection area to form a groove; the protective region is directly connected with all the drift regions, the substrate region and the drain electrode; the surface of each drift region of the first conductivity type is provided with a heavily doped semiconductor ohmic region of the first conductivity type, and the surface of each drift region of the second conductivity type is provided with a heavily doped semiconductor ohmic region of the second conductivity type; the surface of the isolation ring is covered with an insulating medium isolation insulating region and a metal region serving as an isolation electrode, part of the isolation electrode is embedded into the isolation insulating region, the isolation electrode is in direct contact with the ohmic region, and the isolation insulating region is in direct contact with the ohmic region and the drift region; from the side close to the low-side device, the ohmic region of the first conductivity type is connected to the ohmic region of the second conductivity type via the isolating electrode.
Optionally, the low-side power device and the high-side power device are both super junction metal oxide semiconductor field effect transistors MOSFETs;
The low-side super-junction MOSFET consists of a drift region, a drain structure, an MOS gate structure and a terminal region; the drift region consists of a semiconductor drift region of a first conduction type and a plurality of semiconductor drift regions of a second conduction type, and each drift region of the second conduction type is surrounded by the drift region of the first conduction type; the bottom of the drift region of the first conduction type is provided with a heavily doped semiconductor substrate region of the first conduction type, the substrate region is covered with a metal region serving as a drain electrode, and the substrate region and the drain electrode form a drain electrode structure; the MOS grid structure consists of a plurality of MOS unit cells, wherein each MOS unit cell comprises a semiconductor source region positioned on the surface of the drift region of the second conduction type, a semiconductor source region positioned in the source region, an insulating medium grid medium region, a metal source electrode and a semiconductor polycrystalline silicon grid region embedded in the grid medium region; the source body region is in direct contact with the drift region of the first conductivity type and a portion of the drift region of the second conductivity type; the gate dielectric region is in direct contact with the drift region, the source body region and the source region of the first conduction type; the source electrode is directly contacted with the gate dielectric region, the source body region and the source region; the surface of a drift region of the second conductivity type which is not contacted with a source body region and a drift region of the first conductivity type nearby the drift region is covered with an insulating medium passivation region, the surface of the part, close to an isolation ring, of the drift region of the first conductivity type of the low-side super-junction MOSFET is provided with a heavily doped semiconductor field termination region of the first conductivity type, the surface of the semiconductor field termination region is covered with a metal layer to form a field termination electrode, and the drift region of the second conductivity type which is not contacted with the source body region and the drift region of the first conductivity type nearby the drift region of the second conductivity type, the passivation region, the termination region and the termination electrode form a termination region;
The drain electrode of the low-side super-junction MOSFET is directly connected with the drain electrode on one side of the isolating ring close to the low-side super-junction MOSFET and belongs to the same metal electrode; the substrate region of the low-side super-junction MOSFET is directly connected with the substrate region of the isolating ring close to one side of the low-side super-junction MOSFET and belongs to the same semiconductor region; the drift region of the first conductivity type of the low-side super-junction MOSFET is directly connected with the drift region of the first conductivity type on one side, close to the low-side super-junction MOSFET, in the isolating ring and belongs to the same semiconductor region; the field termination region of the low-side super-junction MOSFET is directly connected with the ohmic region of the first conductivity type in the isolating ring close to one side of the low-side super-junction MOSFET and belongs to the same semiconductor region; the field termination electrode of the low-side super-junction MOSFET is directly connected with the isolation electrode on one side of the isolation ring close to the low-side super-junction MOSFET and belongs to the same metal electrode;
the structure of the high-side super-junction MOSFET is the same as that of the low-side super-junction MOSFET;
the drain electrode of the high-side super-junction MOSFET is directly connected with the drain electrode on the side, close to the high-side super-junction MOSFET, in the isolating ring and belongs to the same metal electrode; the substrate area of the high-side super-junction MOSFET is directly connected with the substrate area on one side, close to the high-side super-junction MOSFET, in the isolation ring and belongs to the same semiconductor area; the drift region of the first conductivity type of the high-side super-junction MOSFET is directly connected with the drift region of the first conductivity type on one side, close to the high-side super-junction MOSFET, of the isolation ring and belongs to the same semiconductor region; the field termination region of the high-side super-junction MOSFET is directly connected with the ohmic region of the first conductivity type on one side of the isolation ring close to the high-side super-junction MOSFET, and belongs to the same semiconductor region; the field termination electrode of the high-side super-junction MOSFET is directly connected with the isolation electrode on one side of the isolation ring close to the high-side super-junction MOSFET and belongs to the same metal electrode;
When the first conduction type is N type, the second conduction type is P type; when the first conductivity type is P-type, the second conductivity type is N-type.
Optionally, the semiconductor region is a silicon, gallium arsenide, gallium nitride or silicon carbide material.
Optionally, the low-side power device and the high-side power device are super junction insulated gate bipolar transistors IGBTs, that is, semiconductor emitter regions of the second conductivity type are inserted into substrate regions thereof, and the substrate region concentration is reduced.
Optionally, the low-side power device and the high-side power device are vertical double-diffused metal oxide semiconductor VDMOS, that is, drift regions thereof are only composed of drift regions of the first conductivity type, and do not include drift regions of the second conductivity type.
Optionally, the low-side power device and the high-side power device are diode structures, that is, drift regions thereof are only composed of drift regions of the first conductivity type, and do not include drift regions of the second conductivity type, and do not include MOS gate structures.
The invention has the beneficial effects that: compared with a board-level integrated power device module and a single-package integrated power device module, the single-chip integration of the power device enables the occupied area of the module to be small, and meanwhile, parasitic inductance is small due to the short lead wires.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic top view of a monolithically integrated half-bridge power device module;
FIG. 2 is a cross-sectional view of a monolithically integrated half-bridge power device module with the power device being a super junction MOSEFT;
fig. 3 is a cross-sectional view of a monolithically integrated half-bridge power device module with the power device being a super junction IGBT;
FIG. 4 is a cross-sectional view of a monolithically integrated half-bridge power device module with the power device being a VDMOS;
fig. 5 is a cross-sectional view of a monolithically integrated half-bridge power device module in which the power device is a diode.
Reference numerals: 000-low side super junction MOSFET source electrode, 000 a-low side super junction IGBT emitter, 000 b-low side VDMOS source electrode, 000 c-low side diode anode, 001-spacer electrode 1, 002-spacer electrode 2, 003-spacer electrode 3, 004-high side super junction MOSFET field stop electrode, 010-high side super junction MOSFET source electrode, 010 a-high side super junction IGBT emitter, 010 b-high side VDMOS source electrode, 010 c-high side diode anode, 020 low side super junction MOSFET drain electrode, 020 a-low side super junction IGBT collector, 020 b-low side VDMOS drain electrode, 020 c-low side diode cathode, 021-high side super junction MOSFET drain electrode, 021 a-high side super junction IGBT drain electrode, 021 b-high side mos drain electrode, 021 c-high side diode cathode, 100-low side superjunction MOSFET gate dielectric region, 100 a-low side superjunction IGBT gate dielectric region, 100 b-low side VDMOS gate dielectric region, 101-low side power device passivation region, 102-spacer ring isolation insulation region 1, 103-spacer ring isolation insulation region 2, 104-spacer ring isolation insulation region 3, 105-spacer ring isolation insulation region 4, 106-spacer ring isolation insulation region 5, 107-spacer ring isolation insulation region 6, 108-spacer ring isolation insulation region 7, 110-high side superjunction MOSFET gate dielectric region, 110 a-high side superjunction IGBT gate dielectric region, 110 b-high side VDMOS gate dielectric region, 111-high side power device passivation region, 200-low side superjunction MOSFET gate region, 200 a-low side superjunction IGBT gate region, 200 b-low side VDMOS gate region, 210-high side superjunction MOSFET gate region, 210 a-high side superjunction IGBT gate region, 210 b-high side VDMOS gate region, 300-low side superjunction MOSFET source region, 300 a-low side superjunction IGBT emitter region, 300 b-low side VDMOS source region, 301-low side power device field termination region, 302-isolating ring ohmic region of first conductivity type 1, 303-isolating ring ohmic region of first conductivity type 2, 310-high side superjunction MOSFET source region, 310 a-high side superjunction IGBT emitter region, 310 b-high side VDMOS source region, 311-high side power device field termination region, 400-isolating ring ohmic region of second conductivity type 1, 401-isolating ring ohmic region of second conductivity type 2, 402-isolating ring ohmic region of second conductivity type 3, 500-low side superjunction MOSFET source region, 500 a-low side superjunction IGBT body region, 500 b-low side VDMOS source region, 500 c-low side diode anode diffusion region, 510-high side super junction MOSFET source body region, 510 a-high side super junction IGBT body region, 510 b-high side VDMOS source body region, 510 c-high side diode anode diffusion region, 600-power device second conductivity type drift region, 601-spacer ring second conductivity type drift region 1, 602-spacer ring second conductivity type drift region 2, 603-spacer ring second conductivity type drift region 3, 609-low side IGBT collector region, 610-high side power device second conductivity type drift region, 619-high side IGBT collector region, 700-low side power device first conductivity type drift region, 710-high side power device first conductivity type drift region, 800-low side MOSFET substrate region, 800 a-super junction IGBT buffer region, 800 b-low side VDMOS substrate region, 800 c-low side diode substrate region, 810-high side super junction MOSFET substrate region, 810 a-high side super junction IGBT buffer region, 810 b-high side VDMOS substrate region, 810 c-high side diode substrate region, 900-isolation ring protection region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
Referring to fig. 1, a top view of a monolithic half-bridge power device module is schematically shown, which includes: the isolation ring, the low side power device that is surrounded by the isolation ring, the high side power device that lies outside the isolation ring, the periphery of low side power device and one side direct contact of isolation ring, the peripheral one side of high side power device and one side direct contact of isolation ring.
The low-side power device and the high-side power device may be a super-junction MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a super-junction IGBT (Insulated Gate Bipolar Transistor), a VDMOS (vertical Double Diffused Metal Oxide Semiconductor), and a diode.
In the structure of fig. 2, both the low-side power device and the high-side power device are super junction MOSFETs.
The isolating ring in the structure is composed of a plurality of semiconductor drift regions of a first conduction type and a plurality of semiconductor drift regions of a second conduction type which are alternately arranged, the outermost side is the drift region of the first conduction type, and the drift regions of the two conduction types are in direct contact; the bottom of the drift region of the first conduction type positioned at the outermost side is connected with a heavily doped semiconductor substrate region of the first conduction type, and the substrate region is covered with a metal region serving as a drain electrode; etching the back of the isolation ring and covering the back with an insulating medium protection area to form a groove; the protection region is directly connected with all the drift region, the substrate region and the drain electrode; the surface of each drift region of the first conductivity type is provided with a heavily doped semiconductor ohmic region of the first conductivity type, and the surface of each drift region of the second conductivity type is provided with a heavily doped semiconductor ohmic region of the second conductivity type; the surface of the isolation ring is covered with an insulating medium isolation insulating region and a metal region serving as an isolation electrode, part of the isolation electrode is embedded into the isolation insulating region, the isolation electrode is in direct contact with the ohmic region, and the isolation insulating region is in direct contact with the ohmic region and the drift region; from the side close to the low-side device, the ohmic region of the first conductivity type is connected to the ohmic region of the second conductivity type via the isolating electrode.
The low-side super-junction MOSFET consists of a drift region, a drain structure, an MOS gate structure and a terminal region; the drift region consists of a semiconductor drift region of a first conductivity type and a plurality of semiconductor drift regions of a second conductivity type, and each drift region of the second conductivity type is surrounded by the drift region of the first conductivity type; a heavily doped semiconductor substrate region of the first conductivity type is arranged at the bottom of the drift region of the first conductivity type, the substrate region is covered with a metal region as a drain electrode, and the substrate region and the drain electrode form a drain electrode structure; the MOS grid structure consists of a plurality of MOS unit cells, wherein each MOS unit cell comprises a semiconductor source region positioned on the surface of the drift region of the second conduction type, a semiconductor source region positioned in the source region, an insulating medium grid medium region, a metal source electrode and a semiconductor polycrystalline silicon grid region embedded in the grid medium region; the source body region is in direct contact with the drift region of the first conductivity type and a portion of the drift region of the second conductivity type; the gate dielectric region is in direct contact with the drift region, the source body region and the source region of the first conduction type; the source electrode is directly contacted with the gate dielectric region, the source body region and the source region; the surface of a drift region of the second conductivity type which is not in contact with a source body region and the first conductivity type in the vicinity of the drift region is covered with an insulating medium passivation region, the surface of the first conductivity type drift region of the low-side super-junction MOSFET, which is close to the part of an isolation ring, is provided with a heavily doped semiconductor field termination region of the first conductivity type, the surface of the semiconductor field termination region is covered with a metal layer to form a field termination electrode, and the drift region of the second conductivity type which is not in contact with the source body region and the first conductivity type drift region, the passivation region, the field termination region and the termination electrode in the vicinity of the drift region form a termination region.
The drain electrode of the low-side super-junction MOSFET is directly connected with the drain electrode on one side of the isolating ring close to the low-side super-junction MOSFET and belongs to the same metal electrode; the substrate area of the low-side super-junction MOSFET is directly connected with the substrate area of one side, close to the low-side super-junction MOSFET, in the isolation ring and belongs to the same semiconductor area; the drift region of the first conductivity type of the low-side super-junction MOSFET is directly connected with the drift region of the first conductivity type on one side, close to the low-side super-junction MOSFET, in the isolating ring and belongs to the same semiconductor region; the field termination region of the low-side super-junction MOSFET is directly connected with the ohmic region of the first conductivity type in the isolating ring close to one side of the low-side super-junction MOSFET and belongs to the same semiconductor region; the field termination electrode of the low-side super-junction MOSFET is directly connected with the isolation electrode on one side of the isolation ring close to the low-side super-junction MOSFET and belongs to the same metal electrode.
The structure of the high-side super-junction MOSFET is the same as the structure of the low-side super-junction MOSFET.
The drain electrode of the high-side super-junction MOSFET is directly connected with the drain electrode on the side, close to the high-side super-junction MOSFET, in the isolating ring and belongs to the same metal electrode; the substrate area of the high-side super-junction MOSFET is directly connected with the substrate area on one side, close to the high-side super-junction MOSFET, in the isolation ring and belongs to the same semiconductor area; the drift region of the first conductivity type of the high-side super-junction MOSFET is directly connected with the drift region of the first conductivity type on one side, close to the high-side super-junction MOSFET, of the isolation ring and belongs to the same semiconductor region; the field termination region of the high-side super-junction MOSFET is directly connected with the ohmic region of the first conductivity type on one side of the isolation ring close to the high-side super-junction MOSFET, and belongs to the same semiconductor region; the field termination electrode of the high-side super-junction MOSFET is directly connected with the isolation electrode on one side of the isolation ring close to the high-side super-junction MOSFET, and belongs to the same metal electrode.
In the structure of fig. 3, both the low-side power device and the high-side power device are super junction IGBTs.
The isolating ring in the structure is formed by alternately arranging a plurality of semiconductor drift regions of a first conduction type and a plurality of semiconductor drift regions of a second conduction type, the outermost side of the isolating ring is provided with the drift region of the first conduction type, and the drift regions of the two conduction types are in direct contact; the bottom of a first conductive type drift region positioned at the outermost side is connected with a first conductive type semiconductor buffer region, the bottom of the buffer region is provided with a second conductive type semiconductor collector region, and the collector region is covered with a metal region to serve as a collector; etching the back of the isolation ring and covering the back with an insulating medium protection area to form a groove; the protection region is directly connected with all the drift region, the buffer region, the collector region and the drain electrode; the surface of each drift region of the first conduction type is provided with a heavily doped semiconductor ohmic region of the first conduction type, and the surface of each drift region of the second conduction type is provided with a heavily doped semiconductor ohmic region of the second conduction type; the surface of the isolation ring is covered with an insulating medium isolation insulating region and a metal region serving as an isolation electrode, part of the isolation electrode is embedded into the isolation insulating region, the isolation electrode is in direct contact with the ohmic region, and the isolation insulating region is in direct contact with the ohmic region and the drift region; starting from the side close to the low-side device, the ohmic region of the first conductivity type is connected to the ohmic region of the second conductivity type via the isolating electrode.
The low-side super-junction IGBT consists of a drift region, a collector structure, an MOS gate structure and a terminal region; the drift region consists of a semiconductor drift region of a first conductivity type and a plurality of semiconductor drift regions of a second conductivity type, and each drift region of the second conductivity type is surrounded by the drift region of the first conductivity type; a semiconductor buffer area of the first conductivity type is arranged at the bottom of the drift area of the first conductivity type, a semiconductor collector area of the second conductivity type is arranged at the bottom of the buffer area, a metal area is covered on the collector area to serve as a collector, and the buffer area, the collector area and the collector form a collector structure; the MOS grid structure consists of a plurality of MOS unit cells, wherein each MOS unit cell comprises a semiconductor body region positioned on the surface of the drift region of the second conduction type, a semiconductor emitter region positioned in the body region, an insulating dielectric grid dielectric region, a metal emitter and a semiconductor polycrystalline silicon grid region embedded in the grid dielectric region; the body region is in direct contact with the drift region of the first conductivity type and a portion of the drift region of the second conductivity type; the gate dielectric region is in direct contact with the drift region, the body region and the emitter region of the first conductivity type; the emitter is directly contacted with the gate dielectric region, the body region and the emitter region; the surface of the drift region of the second conductivity type which is not contacted with the body region and the drift region of the first conductivity type nearby the drift region of the second conductivity type are covered with an insulating medium passivation region, the surface of the drift region of the first conductivity type of the low-side super-junction IGBT, which is close to the part of the isolation ring, is provided with a heavily doped semiconductor field termination region of the first conductivity type, the surface of the semiconductor field termination region is covered with a metal layer to form a field termination electrode, and the drift region of the second conductivity type which is not contacted with the source body region and the drift region of the first conductivity type nearby the drift region of the second conductivity type, the passivation region, the field termination region and the termination electrode form a termination region.
The collector of the low-side super-junction IGBT is directly connected with the collector of one side, close to the low-side super-junction IGBT, of the isolation ring and belongs to the same metal electrode; the collector region of the low-side super-junction IGBT is directly connected with the collector region on one side, close to the low-side super-junction IGBT, of the isolating ring and belongs to the same semiconductor region; the buffer area of the low-side super-junction IGBT is directly connected with the buffer area close to one side of the low-side super-junction IGBT in the isolating ring and belongs to the same semiconductor area; the drift region of the first conductivity type of the low-side super-junction IGBT is directly connected with the drift region of the first conductivity type close to one side of the low-side super-junction IGBT in the isolating ring and belongs to the same semiconductor region; the field termination region of the low-side super-junction IGBT is directly connected with the ohmic region of the first conductivity type close to one side of the low-side super-junction IGBT in the isolating ring and belongs to the same semiconductor region; the field termination electrode of the low-side super-junction IGBT is directly connected with the isolation electrode on one side, close to the low-side super-junction IGBT, in the isolation ring and belongs to the same metal electrode.
The structure of the high-side super-junction IGBT is the same as that of the low-side super-junction IGBT.
The drain electrode of the high-side super-junction IGBT is directly connected with the drain electrode on the side, close to the high-side super-junction IGBT, in the isolating ring and belongs to the same metal electrode; the collector region of the low-side super-junction IGBT is directly connected with the collector region on one side, close to the low-side super-junction IGBT, of the isolating ring and belongs to the same semiconductor region; the buffer area of the high-side super-junction IGBT is directly connected with the buffer area on one side, close to the high-side super-junction IGBT, of the isolation ring and belongs to the same semiconductor area; the drift region of the first conductivity type of the high-side super-junction IGBT is directly connected with the drift region of the first conductivity type, close to one side of the high-side super-junction IGBT, in the isolating ring and belongs to the same semiconductor region; the field termination region of the high-side super-junction IGBT is directly connected with the ohmic region of the first conductivity type in the isolating ring, close to one side of the high-side super-junction IGBT, and belongs to the same semiconductor region; the field termination electrode of the high-side super-junction IGBT is directly connected with the isolation electrode on one side of the isolation ring close to the high-side super-junction IGBT and belongs to the same metal electrode.
In the structure of fig. 4, both the low-side power device and the high-side power device are VDMOS. The isolation ring in this structure is the same as the isolation ring in FIG. 2, and is not described again.
The low-side super-junction VDMOS consists of a drift region, a drain structure, an MOS gate structure and a terminal region; the drift region is a semiconductor drift region of a first conductivity type; a heavily doped semiconductor substrate region of the first conductivity type is arranged at the bottom of the drift region, the substrate region is covered with a metal region as a drain electrode, and the substrate region and the drain electrode form a drain electrode structure; the MOS grid structure consists of a plurality of MOS unit cells, wherein each MOS unit cell comprises a semiconductor source region positioned on the surface of the drift region, a semiconductor source region positioned in the source region, an insulating medium grid medium region, a metal source electrode and a semiconductor polycrystalline silicon grid region embedded in the grid medium region; the gate dielectric region is directly contacted with the drift region, part of the source body region and the source region; the source electrode is directly contacted with the gate dielectric region, the source body region and the source region; the surface of a source body region which is not contacted with the gate dielectric region and a drift region of the first conduction type nearby the source body region is covered with an insulating dielectric passivation region, the surface of the part, close to an isolation ring, of the drift region of the low-side VDMOS is provided with a semiconductor field termination region of the first conduction type, the surface of the semiconductor field termination region is covered with a metal layer to form a field termination electrode, and the source body region which is not contacted with the gate dielectric region and the drift region nearby the source body region, the passivation region, the field termination region and the field termination electrode form a terminal region.
The drain electrode of the low-side VDMOS is directly connected with the drain electrode on one side of the isolating ring close to the low-side VDMOS, and belongs to the same metal electrode; the substrate region of the low-side VDMOS is directly connected with the substrate region of the isolating ring close to one side of the low-side VDMOS and belongs to the same semiconductor region; the drift region of the first conductivity type of the low-side VDMOS is directly connected with the drift region of the first conductivity type on one side, close to the low-side VDMOS, in the isolation ring and belongs to the same semiconductor region; the field termination region of the low-side VDMOS is directly connected with the first-conductivity-type ohmic region close to one side of the low-side VDMOS in the isolating ring and belongs to the same semiconductor region; the field termination electrode of the low-side VDMOS is directly connected with the isolation electrode on one side of the isolation ring close to the low-side VDMOS and belongs to the same metal electrode.
The structure of the high-side VDMOS is the same as the structure of the low-side VDMOS.
The drain electrode of the high-side VDMOS is directly connected with the drain electrode on the side, close to the high-side VDMOS, in the isolating ring and belongs to the same metal electrode; the substrate region of the high-side VDMOS is directly connected with the substrate region on one side, close to the high-side VDMOS, of the isolation ring and belongs to the same semiconductor region; the drift region of the first conductivity type of the high-side VDMOS is directly connected with the drift region of the first conductivity type on one side, close to the high-side VDMOS, in the isolation ring and belongs to the same semiconductor region; the field termination region of the high-side VDMOS is directly connected with the ohmic region of the first conductivity type, close to one side of the high-side VDMOS, in the isolation ring, and belongs to the same semiconductor region; the field termination electrode of the high-side VDMOS is directly connected with the isolation electrode on one side of the isolation ring close to the high-side VDMOS, and belongs to the same metal electrode.
In the structure of fig. 5, both the low-side power device and the high-side power device are diode structures.
The isolating ring in the structure is composed of a plurality of semiconductor drift regions of a first conduction type and a plurality of semiconductor drift regions of a second conduction type which are alternately arranged, the outermost side is the drift region of the first conduction type, and the drift regions of the two conduction types are in direct contact; the bottom of the drift region of the first conduction type positioned at the outermost side is connected with a heavily doped semiconductor substrate region of the first conduction type, and the substrate region is covered with a metal region as a cathode; etching the back of the isolation ring and covering the back with an insulating medium protection area to form a groove; the protection region is directly connected with all the drift regions, the substrate region and the cathode; the surface of each drift region of the first conductivity type is provided with a heavily doped semiconductor ohmic region of the first conductivity type, and the surface of each drift region of the second conductivity type is provided with a heavily doped semiconductor ohmic region of the second conductivity type; the surface of the isolation ring is covered with an insulating medium isolation insulating region and a metal region serving as an isolation electrode, part of the isolation electrode is embedded into the isolation insulating region, the isolation electrode is in direct contact with the ohmic region, and the isolation insulating region is in direct contact with the ohmic region and the drift region; from the side close to the low-side device, the ohmic region of the first conductivity type is connected to the ohmic region of the second conductivity type via the isolating electrode.
The low-side diode structure consists of a drift region of the first conductivity type, a cathode structure, an anode structure and a terminal region; a heavily doped semiconductor substrate region of the first conductivity type is arranged at the bottom of the drift region, the substrate region is covered with a metal region as a cathode, and the substrate region and the cathode form a cathode structure; a plurality of semiconductor anode diffusion regions of the second conductivity type are arranged on the surface of the drift region, a metal region is covered on the surface of part of the anode diffusion regions to serve as an anode, and the anode diffusion regions and the anode form an anode structure; the surface of the anode diffusion region which is not in contact with the anode and the surface of the drift region nearby the anode are covered with an insulating medium passivation region, the surface of the drift region of the low-side diode structure, which is close to the part of the isolation ring, is provided with a heavily doped semiconductor field termination region of the first conductivity type, the surface of the semiconductor field termination region is covered with a metal layer to form a field termination electrode, and the anode diffusion region which is not in contact with the anode and the drift region, the passivation region, the field termination region and the field termination electrode nearby the anode diffusion region of the first conductivity type form a terminal region.
The cathode of the low-side diode structure is directly connected with the cathode of one side, close to the low-side diode structure, of the isolating ring and belongs to the same metal electrode; the cathode region of the low-side diode structure is directly connected with the cathode region of one side, close to the low-side diode structure, of the isolation ring and belongs to the same semiconductor region; the drift region of the low-side diode structure is directly connected with the drift region of the first conductivity type on one side, close to the low-side diode structure, in the isolation ring and belongs to the same semiconductor region; the field termination region of the low-side diode structure is directly connected with the ohmic region of the first conductivity type on one side, close to the low-side diode structure, in the isolating ring and belongs to the same semiconductor region; the field stop electrode of the low-side diode structure is directly connected with the isolating electrode on one side of the isolating ring close to the low-side diode structure and belongs to the same metal electrode.
The structure of the high-side diode structure is the same as that of the low-side diode structure.
The cathode of the high-side diode structure is directly connected with the cathode of one side, close to the high-side diode structure, of the isolating ring and belongs to the same metal electrode; the cathode region of the high-side diode structure is directly connected with the substrate region on one side, close to the high-side diode structure, of the isolation ring and belongs to the same semiconductor region; the drift region of the high-side diode structure is directly connected with the drift region of the first conductivity type, close to one side of the high-side diode structure, in the isolation ring and belongs to the same semiconductor region; the field termination region of the high-side diode structure is directly connected with the ohmic region of the first conductivity type, close to one side of the high-side diode structure, in the isolating ring, and belongs to the same semiconductor region; the field stop electrode of the high-side diode structure is directly connected with the isolating electrode on one side of the isolating ring close to the high-side diode structure and belongs to the same metal electrode.
The most important point of the invention is that the back of the isolation ring is embedded with a groove, so that the drift region of the first conduction type of the low-side power device and the high-side power device, the substrate region and the drain electrode are electrically isolated. When the low-side power device is turned off and the high-side power device is turned on, the potentials of the drain electrode of the low-side power device and the source electrode of the high-side power device are basically the same, and the potentials of the drain electrode of the low-side power device and the source electrode of the high-side power device are the same as the potentials of all the isolation electrodes of the isolation ring, are high voltages and are equivalent to the withstand voltage of the low-side power device; when the low-side device power device is turned on and the high-side device is turned off, the potentials of the drain electrode of the low-side device and the source electrode of the high-side device power device are basically the same and are equal to the turn-on voltage of the low-side device power device, the high voltage of the drain electrode of the high-side device is uniformly borne by the isolation electrode of the isolation ring, the number of drift regions in the isolation ring is reasonably set, and the required breakdown voltage can be obtained, so that the low-side device and the high-side device are ensured to work safely.
When the first conduction type is N type, the second conduction type is P type; when the first conductivity type is P-type, the second conductivity type is N-type.
The semiconductor region may be a silicon material, or may be a material such as gallium arsenide, gallium nitride, or silicon carbide.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.
Claims (3)
1. Monolithic integrated half-bridge power device module characterized in that: the device comprises an isolation ring, a low-side power device surrounded by the isolation ring and a high-side power device positioned outside the isolation ring;
the periphery of the low-side power device is directly contacted with one side of the isolating ring, and one side of the periphery of the high-side power device is directly contacted with one side of the isolating ring;
the isolating ring is formed by alternately arranging a plurality of semiconductor drift regions of a first conduction type and a plurality of semiconductor drift regions of a second conduction type, the outermost side of the isolating ring is provided with the drift regions of the first conduction type, and the drift regions of the two conduction types are in direct contact;
The bottom of the drift region of the first conduction type positioned at the outermost side is connected with a heavily doped semiconductor substrate region of the first conduction type, and the substrate region is covered with a metal region serving as a drain electrode;
etching the back of the isolation ring and covering the back with an insulating medium protection area to form a groove; the protection region is directly connected with all the drift region, the substrate region and the drain electrode; the surface of each drift region of the first conductivity type is provided with a heavily doped semiconductor ohmic region of the first conductivity type, and the surface of each drift region of the second conductivity type is provided with a heavily doped semiconductor ohmic region of the second conductivity type; the surface of the isolation ring is covered with an insulating medium isolation insulating region and a metal region serving as an isolation electrode, part of the isolation electrode is embedded into the isolation insulating region, the isolation electrode is in direct contact with the ohmic region, and the isolation insulating region is in direct contact with the ohmic region and the drift region; starting from the side close to the low-side component, the ohmic region of the first conductivity type is connected to the adjacent ohmic region of the second conductivity type via the isolating electrode;
the low-side power device and the high-side power device are both super-junction Metal Oxide Semiconductor Field Effect Transistors (MOSFETs);
The low-side super-junction MOSFET consists of a drift region, a drain structure, an MOS gate structure and a terminal region; the drift region consists of a semiconductor drift region of a first conductivity type and a plurality of semiconductor drift regions of a second conductivity type, and each drift region of the second conductivity type is surrounded by the drift region of the first conductivity type; a heavily doped semiconductor substrate region of the first conductivity type is arranged at the bottom of the drift region of the first conductivity type, the substrate region is covered with a metal region as a drain electrode, and the substrate region and the drain electrode form a drain electrode structure; the MOS grid structure consists of a plurality of MOS unit cells, wherein each MOS unit cell comprises a semiconductor source region positioned on the surface of the drift region of the second conduction type, a semiconductor source region positioned in the source region, an insulating medium grid medium region, a metal source electrode and a semiconductor polycrystalline silicon grid region embedded in the grid medium region; the source body region is in direct contact with the drift region of the first conductivity type and a portion of the drift region of the second conductivity type; the gate dielectric region is in direct contact with the drift region, the source body region and the source region of the first conduction type; the source electrode is directly contacted with the gate dielectric region, the source body region and the source region; the surface of a drift region of the second conductivity type which is not contacted with a source body region and a drift region of the first conductivity type nearby the drift region is covered with an insulating medium passivation region, the surface of the part, close to an isolation ring, of the drift region of the first conductivity type of the low-side super-junction MOSFET is provided with a semiconductor field termination region of the first conductivity type, the surface of the semiconductor field termination region is covered with a metal layer to form a field termination electrode, and the drift region of the second conductivity type which is not contacted with the source body region and the drift region of the first conductivity type nearby the drift region, the passivation region, the termination region and the field termination electrode form a termination region;
The drain electrode of the low-side super-junction MOSFET is directly connected with the drain electrode on one side of the isolating ring close to the low-side super-junction MOSFET and belongs to the same metal electrode; the substrate region of the low-side super-junction MOSFET is directly connected with the substrate region of the isolating ring close to one side of the low-side super-junction MOSFET and belongs to the same semiconductor region; the drift region of the first conductivity type of the low-side super-junction MOSFET is directly connected with the drift region of the first conductivity type on one side, close to the low-side super-junction MOSFET, in the isolating ring and belongs to the same semiconductor region; the field termination region of the low-side super-junction MOSFET is directly connected with the ohmic region of the first conductivity type in the isolating ring close to one side of the low-side super-junction MOSFET and belongs to the same semiconductor region; the field termination electrode of the low-side super-junction MOSFET is directly connected with the isolation electrode on one side of the isolation ring close to the low-side super-junction MOSFET and belongs to the same metal electrode;
the structure of the high-side super-junction MOSFET is the same as that of the low-side super-junction MOSFET;
the drain electrode of the high-side super-junction MOSFET is directly connected with the drain electrode on the side, close to the high-side super-junction MOSFET, in the isolating ring and belongs to the same metal electrode; the substrate area of the high-side super-junction MOSFET is directly connected with the substrate area on one side, close to the high-side super-junction MOSFET, in the isolation ring and belongs to the same semiconductor area; the drift region of the first conductivity type of the high-side super-junction MOSFET is directly connected with the drift region of the first conductivity type on one side, close to the high-side super-junction MOSFET, of the isolation ring and belongs to the same semiconductor region; the field termination region of the high-side super-junction MOSFET is directly connected with the ohmic region of the first conductivity type on one side of the isolation ring close to the high-side super-junction MOSFET, and belongs to the same semiconductor region; the field termination electrode of the high-side super-junction MOSFET is directly connected with the isolation electrode on one side of the isolation ring close to the high-side super-junction MOSFET and belongs to the same metal electrode;
When the first conductive type is N type, the second conductive type is P type; when the first conduction type is a P type, the second conduction type is an N type;
the low-side power device and the high-side power device are vertical double-diffused metal oxide semiconductor (VDMOS), namely drift regions of the VDMOS consist of drift regions of the first conduction type only and do not contain drift regions of the second conduction type;
the low-side power device and the high-side power device are diode structures, i.e. the drift regions thereof consist of drift regions of the first conductivity type only, and do not comprise drift regions of the second conductivity type, and do not comprise MOS gate structures.
2. The monolithically integrated half-bridge power device module of claim 1, wherein: the semiconductor region is made of silicon, gallium arsenide, gallium nitride or silicon carbide materials.
3. The monolithically integrated half-bridge power device module of claim 1, wherein: the low-side power device and the high-side power device are super-junction Insulated Gate Bipolar Transistors (IGBTs), namely, semiconductor emitting regions of the second conduction type are inserted into substrate regions of the IGBTs, and meanwhile, the concentration of the substrate regions is reduced.
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Effective date of registration: 20221228 Address after: Room 401, Building A, No. 169 Shengxia Road, Pudong New Area, Shanghai, 200,120 Patentee after: Jiefang Semiconductor (Shanghai) Co.,Ltd. Address before: 400044 No. 174 Shapingba street, Shapingba District, Chongqing Patentee before: Chongqing University |