JP2005322949A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2005322949A
JP2005322949A JP2005227973A JP2005227973A JP2005322949A JP 2005322949 A JP2005322949 A JP 2005322949A JP 2005227973 A JP2005227973 A JP 2005227973A JP 2005227973 A JP2005227973 A JP 2005227973A JP 2005322949 A JP2005322949 A JP 2005322949A
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Prior art keywords
gate
trench
electric field
semiconductor device
field relaxation
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Inventor
Hiroisa Suzuki
啓功 鈴木
Eiji Yanokura
栄二 矢ノ倉
Tetsuo Iijima
哲郎 飯島
Satoshi Kudo
聡 工藤
Yasuo Imai
保雄 今井
Masayoshi Kobayashi
正義 小林
Sumuto Numazawa
澄人 沼沢
Taku Shigematsu
卓 重松
Takamitsu Kanazawa
孝光 金澤
Masamitsu Haruyama
正光 春山
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Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
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Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
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Priority to JP2005227973A priority Critical patent/JP2005322949A/en
Publication of JP2005322949A publication Critical patent/JP2005322949A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Abstract

<P>PROBLEM TO BE SOLVED: To make thinner a gate insulator without reducing the breakdown voltage of the gate or to increase the breakdown voltage of the gate without thickening the gate insulator in a FET having a trench gate structure. <P>SOLUTION: In a semiconductor device including the FET having the trench gate structure, an electric field relaxation section is provided at the end of the trench gate. Thereby the electric field relaxation section which is provided at the end of the gate can prevent the generation of a local high electric field, so that the gate insulator can be made thinner without reducing the breakdown voltage of the gate or the breakdown voltage of the gate can be increased without thickening the gate insulator. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置に関し、特に、トレンチゲート構造の半導体装置に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a trench gate structure.

電力増幅回路、電源回路、コンバータ或は電源保護回路等にはパワートランジスタが用いられているが、これらのパワートランジスタには大電力を扱うために高耐圧化及び大電流化が要求される。   Power transistors are used in power amplifier circuits, power supply circuits, converters, power supply protection circuits, and the like, but these power transistors are required to have a high breakdown voltage and a large current in order to handle a large amount of power.

ＭＩＳＦＥＴの場合には、大電流化を達成する方法として、チャネル幅を増大させることによって容易に達成できる。そして、このようなチャネル幅の増大を行なうことによってチップ面積が増大するのを回避するために、例えばメッシュゲート構造が用いられている。   In the case of MISFET, it can be easily achieved by increasing the channel width as a method for achieving a large current. In order to avoid an increase in the chip area due to such an increase in channel width, for example, a mesh gate structure is used.

メッシュゲート構造では、ゲートが平面的に格子状に配置されており、このため単位チップ面積当りのチャネル幅を大きくすることができる。   In the mesh gate structure, the gates are arranged in a grid pattern in a plane, and therefore the channel width per unit chip area can be increased.

従来、このようなパワーＦＥＴには、工程が簡単でありゲート絶縁膜となる酸化膜の形成が容易なことからプレーナ構造のものが用いられてきた。   Conventionally, power FETs having a planar structure have been used because the process is simple and it is easy to form an oxide film to be a gate insulating film.

しかしながら、ＦＥＴではゲート長によってチャネル長が決まるために、プレーナ構造のＦＥＴでは、ゲートを細くした場合にはチャネル長が短くなり短チャネル効果が生じる、或はゲートが同時に配線の機能をもっているために、ゲートを細くした場合には許容電流が減少してしまう等の問題があり、微細化には限界がある。   However, in FETs, the channel length is determined by the gate length, so in planar FETs, when the gate is thinned, the channel length is shortened and the short channel effect occurs, or the gate has a wiring function at the same time. When the gate is thinned, there is a problem that the allowable current is reduced, and there is a limit to miniaturization.

このため、更にセルの集積度を向上させることが可能であり、加えてオン抵抗を低減させることができる等の理由からトレンチゲート構造のＦＥＴが注目されている。   For this reason, FETs having a trench gate structure have been attracting attention for the reason that the degree of cell integration can be further improved and the on-resistance can be reduced.

トレンチゲート構造とは、半導体基板主面に延設した溝部に絶縁膜を介してゲートとなる導体層を設け、前記主面の深層部をドレイン領域とし、前記主面の表層部をソース領域とし、前記ドレイン領域及びソース領域間の半導体層をチャネル領域とするものであり、このようなトレンチゲート構造のパワーＭＯＳＦＥＴとしては三菱電機社のＦＳ７０ＴＭ‐０６、シリコニクス社のＳＵＰ７５Ｎ０６‐０８等がある。
メッシュゲート構造のＦＥＴについては、下記非特許文献に記載されている。 In the trench gate structure, a conductor layer serving as a gate is provided in a groove extending to the main surface of the semiconductor substrate via an insulating film, a deep layer portion of the main surface is used as a drain region, and a surface layer portion of the main surface is used as a source region. A semiconductor layer between the drain region and the source region is used as a channel region. Examples of such a power MOSFET having a trench gate structure include FS70TM-06 manufactured by Mitsubishi Electric Corporation and SUP75N06-08 manufactured by Siliconix.
The mesh gate structure FET is described in the following non-patent literature.

オーム社刊「半導体ハンドブック」第４２９頁乃至第４３０頁Ohm Publishing "Semiconductor Handbook" pages 429 to 430

しかしながら、本発明者は、トレンチゲート構造のパワーＦＥＴについて、低電圧駆動のためにゲート絶縁膜の膜厚を薄くした場合に、プレーナ構造のＦＥＴと比較して、ゲート耐圧の低下が予想以上に大きいことを見出した。本発明者は、この点について検討を加え、次の結論を得た。   However, the inventor has found that the trench gate structure power FET has a lower gate breakdown voltage than expected when the gate insulating film thickness is reduced for low voltage driving compared to the planar structure FET. I found it big. The present inventor examined this point and obtained the following conclusion.

プレーナ構造のＭＩＳＦＥＴでは半導体基板主面上にゲート絶縁膜を介してゲート電極が形成されているために、平面に形成されるので均一性に優れたゲート絶縁膜上にゲートが形成されるのに対して、トレンチゲート構造のＦＥＴでは、ゲートが半導体基板内に設けられているために、ゲート絶縁膜の均一性が充分に保証されず、加えて、ゲートが立体的に形成されることから、ゲートの端部が形状誤差によって鋭角的に形成された場合には、この部分に局部的に電界集中が起こり、この電界集中によって生じた高電界によってゲート絶縁膜が破壊され、ゲート耐圧の低下となる。   In the planar structure MISFET, the gate electrode is formed on the main surface of the semiconductor substrate via the gate insulating film, so that the gate electrode is formed on a flat surface, so that the gate is formed on the gate insulating film having excellent uniformity. On the other hand, in the FET of the trench gate structure, since the gate is provided in the semiconductor substrate, the uniformity of the gate insulating film is not sufficiently ensured, and in addition, the gate is formed in three dimensions. When the edge of the gate is formed with an acute angle due to a shape error, an electric field concentration occurs locally in this portion, and the gate insulating film is destroyed by the high electric field generated by this electric field concentration, resulting in a decrease in gate breakdown voltage. Become.

このようなゲート耐圧の低下を防止するため、ゲート絶縁膜を厚くしたのでは相互コンダクタンスｇｍが低下し、低電圧作動が困難となる。   If the gate insulating film is made thick in order to prevent such a reduction in gate breakdown voltage, the mutual conductance gm is lowered, and low voltage operation becomes difficult.

本発明の課題は、このような問題を解決し、ゲート耐圧を低下させることなくゲート絶縁膜を薄くする、或はゲート絶縁膜を厚くせずにゲート耐圧を向上させることが可能な技術を提供することにある。
本発明の前記ならびにその他の課題と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。 An object of the present invention is to provide a technique capable of solving such problems and reducing the gate breakdown voltage without reducing the gate breakdown voltage, or improving the gate breakdown voltage without increasing the gate insulation film. There is to do.
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。
半導体基板主面に延設した溝部にゲートとなる導体層を設けるトレンチゲート構造のＦＥＴを有する半導体装置において、前記トレンチゲートの終端部に電界緩和部を設ける。 Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
In a semiconductor device having a FET having a trench gate structure in which a conductor layer serving as a gate is provided in a groove extending on a main surface of a semiconductor substrate, an electric field relaxation portion is provided at a terminal portion of the trench gate.

電界緩和部の具体的な構成としては、半導体チップ外周部に沿って電界緩和部を延在させ、この電界緩和部にトレンチゲートの終端部を接続する。   As a specific configuration of the electric field relaxation portion, the electric field relaxation portion is extended along the outer peripheral portion of the semiconductor chip, and the terminal portion of the trench gate is connected to the electric field relaxation portion.

或は、半導体チップ外周部の各トレンチゲート終端部に、各内角が鈍角となる多角形或は円形の平面形状をした電界緩和部を設け、この電界緩和部にトレンチゲートの終端部を接続する。   Alternatively, an electric field relaxation portion having a polygonal or circular planar shape with each inner angle being an obtuse angle is provided at each trench gate termination portion on the outer periphery of the semiconductor chip, and the termination portion of the trench gate is connected to this electric field relaxation portion. .

或は、半導体チップ外周部にトレンチゲートから連続し、その断面積を減少させ電界緩和部を設け、この電界緩和部にトレンチゲートの終端部を接続する。   Alternatively, it is continuous from the trench gate on the outer periphery of the semiconductor chip, and the electric field relaxation portion is provided by reducing the cross-sectional area, and the termination portion of the trench gate is connected to the electric field relaxation portion.

更に、半導体チップ外周部に沿って延在し、トレンチゲートの終端部を接続した電界緩和部の周囲に、ドレインとは反対導電型で且つドレインよりも低濃度の不純物を注入した低濃度領域を設ける。   Further, a low-concentration region extending along the outer periphery of the semiconductor chip and having a conductivity type opposite to that of the drain and having an impurity doped lower than that of the drain is formed around the electric field relaxation portion connected to the terminal portion of the trench gate. Provide.

前記トレンチゲートが、内方に前記ソースの形成される領域を、各内角が鈍角となる多角形或は円形の平面形状に残す形で、矩形形状に略全面に形成される。   The trench gate is formed on a substantially entire surface in a rectangular shape so as to leave a region in which the source is formed inward in a polygonal or circular plane shape in which each inner angle is an obtuse angle.

［作用］
上述した手段によれば、ゲートの終端部に設けた電界緩和部にて、局部的な高電界の発生を防止することができるので、ゲート耐圧を低下させることなくゲート絶縁膜を薄くする、或はゲート絶縁膜を厚くせずにゲート耐圧を向上させることが可能となる。 [Action]
According to the above-mentioned means, since the generation of a local high electric field can be prevented by the electric field relaxation portion provided at the terminal end portion of the gate, the gate insulating film is made thin without reducing the gate breakdown voltage, or The gate breakdown voltage can be improved without increasing the thickness of the gate insulating film.

本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
（１）本発明によれば、ゲートの終端部に設けた電界緩和部にて、局部的な高電界が発生するのを防止することができるという効果がある。
（２）本発明によれば、上記効果（１）により、ゲート耐圧を低下させることなくゲート絶縁膜を薄くすることが可能となるという効果がある。
（３）本発明によれば、上記効果（１）により、ゲート絶縁膜を厚くせずにゲート耐圧を向上させることが可能となるという効果がある。 The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.
(1) According to the present invention, there is an effect that a local high electric field can be prevented from being generated in the electric field relaxation portion provided at the terminal end portion of the gate.
(2) According to the present invention, the effect (1) has an effect that the gate insulating film can be thinned without reducing the gate breakdown voltage.
(3) According to the present invention, the effect (1) has an effect that the gate breakdown voltage can be improved without increasing the thickness of the gate insulating film.

以下、本発明の実施の形態を説明する。
なお、実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。 Embodiments of the present invention will be described below.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

（実施の形態１）
図１に示すのは、本発明の一実施の形態である半導体装置のトレンチゲート構造のパワーＭＩＳＦＥＴの要部を表す平面図であり、図２に示すのは、図１中ａ‐ａ線に沿った縦断面図であり、図３に示すのは同じくｂ‐ｂ線に沿った縦断面図である。なお、図１にては説明のために、ソース取り出し配線及びＰＳＧ膜を図示せず、ゲート取り出し配線を透過して示し、これに斜線を付す。 (Embodiment 1)
FIG. 1 is a plan view showing the main part of a power MISFET having a trench gate structure of a semiconductor device according to an embodiment of the present invention. FIG. 2 shows a line aa in FIG. 3 is a longitudinal sectional view taken along the line bb. In FIG. 1, for the sake of explanation, the source extraction wiring and the PSG film are not shown, but are shown through the gate extraction wiring and are hatched.

本実施の形態のＭＩＳＦＥＴは、ＮＰＮ型であり、半導体基板主面の深層部であるＮ＋型層１上のＮ型層２をドレインとし、Ｎ型層２上に形成されたＰ−型層３をチャネルとしている。トレンチゲート４は、半導体基板主面に延設しＮ型層２に達する溝部にゲート絶縁膜となる酸化珪素膜５を介して設けられている。半導体基板主面の表層部のトレンチゲート４周辺に形成されるＮ＋型層６をソースとしている。   The MISFET of the present embodiment is an NPN type, and a P − type layer 3 formed on the N type layer 2 with the N type layer 2 on the N + type layer 1 which is a deep layer portion of the main surface of the semiconductor substrate as a drain. Is the channel. The trench gate 4 is provided in a groove extending to the main surface of the semiconductor substrate and reaching the N-type layer 2 via a silicon oxide film 5 serving as a gate insulating film. The source is an N + type layer 6 formed around the trench gate 4 in the surface layer portion of the main surface of the semiconductor substrate.

トレンチゲート４は、平面的に格子状に配置されるメッシュゲート構造となっているが、図１中横方向に延在する各トレンチゲート４間に位置する縦方向のトレンチゲート４は交互に位置を変えて配置されている。各トレンチゲート４は半導体チップの外周部近傍にて終端しており、この終端部分にて半導体基板主面上のゲート取り出し配線７と接続している。   The trench gates 4 have a mesh gate structure that is arranged in a grid pattern on the plane, but the vertical trench gates 4 positioned between the trench gates 4 extending in the horizontal direction in FIG. It is arranged with changing. Each trench gate 4 terminates in the vicinity of the outer peripheral portion of the semiconductor chip, and is connected to the gate lead-out wiring 7 on the main surface of the semiconductor substrate at this termination portion.

本実施の形態では、半導体チップ外周部に沿って延在する電界緩和部８を半導体基板内に設け、この電界緩和部８にトレンチゲート４の終端部を接続する。電界緩和部８はＭＩＳＦＥＴの形成される領域を囲むようにして矩形環状に設けられ、電界の集中を防止するために、その角部に曲率をもたせて形成する。   In the present embodiment, an electric field relaxation portion 8 extending along the outer periphery of the semiconductor chip is provided in the semiconductor substrate, and the terminal portion of the trench gate 4 is connected to the electric field relaxation portion 8. The electric field relaxation portion 8 is provided in a rectangular ring shape so as to surround a region where the MISFET is formed, and is formed with a curvature at a corner portion thereof in order to prevent concentration of the electric field.

次に、本実施の形態の半導体装置の製造方法を図４乃至図７を用いて説明する。
先ず、厚さ５００μｍ程度のＮ＋型半導体基板１の主面にエピタキシャル成長によって、Ｎ型層２を４μｍ程度形成し、続いてイオン打込みによりＰ−型層３を２μｍ程度形成し、トレンチゲート４の形成される部分及び電界緩和部８の形成される部分の半導体基板主面にホトリソグラフィによってＮ型層２に達する溝部を形成する。この状態を図４に示す。 Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.
First, an N-type layer 2 is formed to about 4 μm by epitaxial growth on the main surface of an N + type semiconductor substrate 1 having a thickness of about 500 μm, and then a P− type layer 3 is formed to about 2 μm by ion implantation to form a trench gate 4. A groove reaching the N-type layer 2 is formed by photolithography on the main surface of the semiconductor substrate at the portion where the electric field relaxation portion 8 is to be formed. This state is shown in FIG.

次に、溝部の表面を含む全面にゲート絶縁膜となる酸化珪素膜を形成し、半導体基板全面にトレンチゲート或は電界緩和部となる多結晶シリコン１１を堆積させる。この状態を図５に示す。   Next, a silicon oxide film to be a gate insulating film is formed on the entire surface including the surface of the trench, and a polycrystalline silicon 11 to be a trench gate or an electric field relaxation portion is deposited on the entire surface of the semiconductor substrate. This state is shown in FIG.

次に、エッチバックによって多結晶シリコン１１を平坦化し、前記溝部を多結晶シリコン１１によって埋め込んで、トレンチゲート４及び電界緩和部８を形成し、この半導体チップ外周部に沿って延在する電界緩和部８と接続する半導体基板主面上にＮ型多結晶シリコンからなるゲート取り出し配線７を形成する。この状態を図６に示す。   Next, the polycrystalline silicon 11 is flattened by etch back, and the trench is filled with the polycrystalline silicon 11 to form the trench gate 4 and the electric field relaxation portion 8, and the electric field relaxation extending along the outer peripheral portion of the semiconductor chip. A gate extraction wiring 7 made of N-type polycrystalline silicon is formed on the main surface of the semiconductor substrate connected to the portion 8. This state is shown in FIG.

この後は従来の方法と同様に、図７に示すように、ソースとなるＮ＋層６をイオン打込みにより１μｍ程度形成し、全面に保護絶縁のためのＰＳＧ膜９を堆積させて、所定位置のＰＳＧ膜９及び酸化珪素膜５をエッチング除去しソース取り出し配線１０の開口を形成し、アルミニュウム等の導体からなる配線１０をソースとなるＮ＋層６に接続し、図２に示す状態となる。なお、ソース取り出し配線１０はベース電位を一定とするためにソースとなるＮ＋層６とチャネルとなるＰ−層３の双方に接続されている。   Thereafter, as in the conventional method, as shown in FIG. 7, an N + layer 6 serving as a source is formed by ion implantation to a thickness of about 1 μm, and a PSG film 9 for protective insulation is deposited on the entire surface. The PSG film 9 and the silicon oxide film 5 are removed by etching to form an opening of the source extraction wiring 10, and the wiring 10 made of a conductor such as aluminum is connected to the N + layer 6 serving as the source, resulting in the state shown in FIG. The source lead-out wiring 10 is connected to both the N + layer 6 serving as the source and the P− layer 3 serving as the channel in order to keep the base potential constant.

なお、本実施の形態では電界緩和部８として矩形環状に設けたが、電界緩和部８としては半導体チップ外周部の各辺に沿って延在するものを各辺に設けてもよく、この場合には各電界緩和部８の終端の電界を緩和する構成としておくことが望ましい。   In the present embodiment, the electric field relaxation portion 8 is provided in a rectangular ring shape, but the electric field relaxation portion 8 may be provided on each side so as to extend along each side of the outer periphery of the semiconductor chip. It is desirable that the electric field at the end of each electric field relaxation unit 8 be relaxed.

ここで、図８に示すのは、従来のトレンチゲート構造のパワーＭＩＳＦＥＴの要部を表す平面図であり、図９に示すのは、図８中ａ‐ａ線に沿った縦断面図である。   Here, FIG. 8 is a plan view showing a main part of a conventional power MISFET having a trench gate structure, and FIG. 9 is a longitudinal sectional view taken along line aa in FIG. .

このような従来のＦＥＴでは、トレンチゲート４が半導体チップ外周部にて終端しており、トレンチゲート４の端部が形状誤差によって部分的に鋭角的に形成された場合には、この部分に局部的に電界集中が起こり、この電界集中によって生じた高電界によってゲート絶縁膜となる酸化珪素膜５が破壊され、ゲート耐圧の低下となる。メッシュゲート構造の場合にはこうした終端部が多数存在することになるため、このような危険性が高くなる。   In such a conventional FET, when the trench gate 4 is terminated at the outer periphery of the semiconductor chip and the end of the trench gate 4 is partially formed by a shape error, the trench gate 4 is locally formed at this portion. Electric field concentration occurs, and the high electric field generated by the electric field concentration destroys the silicon oxide film 5 serving as a gate insulating film, resulting in a decrease in gate breakdown voltage. In the case of a mesh gate structure, there are a large number of such terminal portions, and this risk is increased.

これに対して、本実施の形態のＦＥＴでは、トレンチゲート４の終端部に設けた電界緩和部８によって、トレンチゲート４が面状に終端することとなり、局部的な高電界が発生するのを防止することができる。   On the other hand, in the FET of the present embodiment, the trench gate 4 is terminated in a planar shape by the electric field relaxation portion 8 provided at the termination portion of the trench gate 4, and a local high electric field is generated. Can be prevented.

なお、図１０に示すのは、従来構造のＦＥＴ（ａ）と本実施の形態のＦＥＴ（ｂ）とについて、ゲート耐圧を試験した結果をグラフに表したものである。この図から、本実施の形態のＦＥＴは従来構造のＦＥＴと比較して、ゲート耐圧が高く、製品誤差が小さいことが明らかである。   FIG. 10 is a graph showing the results of testing the gate breakdown voltage of the FET (a) having the conventional structure and the FET (b) of the present embodiment. From this figure, it is clear that the FET according to the present embodiment has a higher gate breakdown voltage and a smaller product error than the conventional FET.

（実施の形態２）
図１１に示すのは、本発明の他の実施の形態である半導体装置のトレンチゲート構造のパワーＭＩＳＦＥＴの要部を表す平面図であり、図１２に示すのは、図１中ｃ‐ｃ線に沿った縦断面図である。なお、図１１にては説明のために、ソース取り出し配線及びＰＳＧ膜を図示せず、ゲート取り出し配線を透過して示し、これに斜線を付す。 (Embodiment 2)
FIG. 11 is a plan view showing a main part of a power MISFET having a trench gate structure of a semiconductor device according to another embodiment of the present invention. FIG. 12 shows a line cc in FIG. It is a longitudinal cross-sectional view along line. In FIG. 11, for the sake of explanation, the source extraction wiring and the PSG film are not shown, but are shown through the gate extraction wiring, and are hatched.

本実施の形態のＭＩＳＦＥＴは、ＮＰＮ型であり、半導体基板主面の深層部であるＮ＋型層１上のＮ型層２をドレインとし、Ｎ型層２上に形成されたＰ−型層３をチャネルとしている。トレンチゲート４は、半導体基板主面に延設しＮ型層２に達する溝部にゲート絶縁膜となる酸化珪素膜５を介して設けられている。半導体基板主面の表層部のトレンチゲート４周辺に形成されるＮ＋型層６をソースとしている。   The MISFET of the present embodiment is an NPN type, and a P − type layer 3 formed on the N type layer 2 with the N type layer 2 on the N + type layer 1 which is a deep layer portion of the main surface of the semiconductor substrate as a drain. Is the channel. The trench gate 4 is provided in a groove portion extending to the main surface of the semiconductor substrate and reaching the N-type layer 2 via a silicon oxide film 5 serving as a gate insulating film. The source is an N + type layer 6 formed around the trench gate 4 in the surface layer portion of the main surface of the semiconductor substrate.

トレンチゲート４は、平面的に格子状に配置されるメッシュゲート構造となっているが、図１１中横方向に延在する各トレンチゲート４間に位置する縦方向のトレンチゲート４は交互に位置を変えて配置されている。各トレンチゲート４は半導体チップの外周部近傍にて終端しており、この終端部分にて半導体基板主面上のゲート取り出し配線７と接続している。   The trench gates 4 have a mesh gate structure that is arranged in a grid pattern on a plane, but the vertical trench gates 4 positioned between the trench gates 4 extending in the horizontal direction in FIG. It is arranged with changing. Each trench gate 4 terminates in the vicinity of the outer peripheral portion of the semiconductor chip, and is connected to the gate lead-out wiring 7 on the main surface of the semiconductor substrate at this termination portion.

本実施の形態では、半導体チップ外周部にトレンチゲート４から連続し、その断面積を段階的に減少させた電界緩和部８を設け、この電界緩和部８にトレンチゲート４の終端部を接続する。このような構成は、トレンチゲート４形成のための前記溝部を形成する際に、マスクパターンを変えることによって容易に形成することができる。   In the present embodiment, an electric field relaxation portion 8 that is continuous from the trench gate 4 and whose cross-sectional area is reduced stepwise is provided on the outer periphery of the semiconductor chip, and the terminal portion of the trench gate 4 is connected to the electric field relaxation portion 8. . Such a configuration can be easily formed by changing the mask pattern when forming the groove for forming the trench gate 4.

本実施の形態のＦＥＴでは、トレンチゲート４の終端部に設けた電界緩和部８の断面積が減少することによって、ゲート絶縁膜となる酸化珪素膜５が実効的に厚くなることとなり、ゲート耐圧の低下を防止することができる。また本実施の形態では、前述した実施の形態と比較して、電界緩和部８に要する面積が小さいために、電界緩和部８形成に伴う容量の増加を抑制することができる。
なお、本実施の形態の電界緩和部８としては、その幅を漸減させる構成としてもよい。 In the FET according to the present embodiment, the silicon oxide film 5 serving as a gate insulating film is effectively thickened by reducing the cross-sectional area of the electric field relaxation portion 8 provided at the terminal portion of the trench gate 4. Can be prevented. Further, in the present embodiment, since the area required for the electric field relaxation portion 8 is smaller than that in the above-described embodiment, an increase in capacitance due to formation of the electric field relaxation portion 8 can be suppressed.
In addition, as the electric field relaxation part 8 of this Embodiment, it is good also as a structure which reduces the width | variety gradually.

（実施の形態３）
図１３に示すのは、本発明の他の実施の形態である半導体装置のトレンチゲート構造のパワーＭＩＳＦＥＴの要部を表す平面図である。なお、図１３にては説明のために、ソー
ス取り出し配線及びＰＳＧ膜を図示せず、ゲート取り出し配線を透過して示し、これに斜線を付す。 (Embodiment 3)
FIG. 13 is a plan view showing a main part of a power MISFET having a trench gate structure of a semiconductor device according to another embodiment of the present invention. In FIG. 13, for the sake of explanation, the source extraction wiring and the PSG film are not shown, but are shown through the gate extraction wiring, and are hatched.

図１２に示す前述した実施の形態と同様に、本実施の形態のＭＩＳＦＥＴは、ＮＰＮ型であり、半導体基板主面の深層部であるＮ＋型層１上のＮ型層２をドレインとし、Ｎ型層２上に形成されたＰ−型層３をチャネルとしている。トレンチゲート４は、半導体基板主面に延設しＮ型層２に達する溝部にゲート絶縁膜となる酸化珪素膜５を介して設けられ、その終端部が電界緩和部８と接続している。半導体基板主面の表層部のトレンチゲート４周辺に形成されるＮ＋型層６をソースとしている。   Similar to the above-described embodiment shown in FIG. 12, the MISFET of this embodiment is of the NPN type, and the N-type layer 2 on the N + -type layer 1 which is a deep layer portion of the main surface of the semiconductor substrate is used as the drain, A P-type layer 3 formed on the mold layer 2 is used as a channel. The trench gate 4 is provided in a groove portion extending to the main surface of the semiconductor substrate and reaching the N-type layer 2 via a silicon oxide film 5 serving as a gate insulating film, and a terminal portion thereof is connected to the electric field relaxation portion 8. The source is an N + type layer 6 formed around the trench gate 4 in the surface layer portion of the main surface of the semiconductor substrate.

トレンチゲート４は、平面的に格子状に配置されるメッシュゲート構造となっているが、図１１中横方向に延在する各トレンチゲート４間に位置する縦方向のトレンチゲート４は交互に位置を変えて配置されている。各トレンチゲート４は半導体チップの外周部近傍にて終端しており、この終端部分にて半導体基板主面上のゲート取り出し配線７と接続している。   The trench gates 4 have a mesh gate structure that is arranged in a grid pattern on the plane, but the vertical trench gates 4 positioned between the trench gates 4 extending in the horizontal direction in FIG. It is arranged with changing. Each trench gate 4 terminates in the vicinity of the outer peripheral portion of the semiconductor chip, and is connected to the gate lead-out wiring 7 on the main surface of the semiconductor substrate at this termination portion.

本実施の形態では、半導体チップ外周部の各トレンチゲート４終端部に、平面形状が円形でその径がトレンチゲート４の幅よりも大きな電界緩和部８を設け、この電界緩和部８にトレンチゲート４の終端部を接続する。このような構成は、トレンチゲート４形成のための前記溝部を形成する際に、マスクパターンを変えることによって容易に形成することができる。   In the present embodiment, an electric field relaxation portion 8 having a circular planar shape and a diameter larger than the width of the trench gate 4 is provided at the end of each trench gate 4 on the outer periphery of the semiconductor chip. 4 end portions are connected. Such a configuration can be easily formed by changing the mask pattern when forming the groove for forming the trench gate 4.

本実施の形態のＦＥＴでは、トレンチゲート４の終端部に設けた電界緩和部８の平面形状を円形とすることにより、各角部に曲率をもたせて局部的な電界集中の発生が防止され、ゲート耐圧の低下を防止することができる。また本実施の形態では、前述した実施の形態と比較して、電界緩和部８に要する面積が小さいために、電界緩和部８形成に伴う容量の増加を抑制することができる。
なお、本実施の形態の電界緩和部８としては、各内角が鈍角となる多角形例えば八角形の平面形状等の構成としてもよい。 In the FET of the present embodiment, by making the planar shape of the electric field relaxation part 8 provided at the terminal part of the trench gate 4 circular, the occurrence of local electric field concentration can be prevented by giving each corner a curvature, A reduction in gate breakdown voltage can be prevented. Further, in the present embodiment, since the area required for the electric field relaxation portion 8 is smaller than that in the above-described embodiment, an increase in capacitance due to formation of the electric field relaxation portion 8 can be suppressed.
In addition, as the electric field relaxation part 8 of this Embodiment, it is good also as a structure of the polygon which each interior angle becomes an obtuse angle, for example, an octagonal planar shape.

（実施の形態４）
図１４に示すのは、本発明の他の実施の形態である半導体装置のトレンチゲート構造のパワーＭＩＳＦＥＴの要部を表す平面図であり、図１５に示すのは、図１４中ａ‐ａ線に沿った縦断面図である。なお、図１４にては説明のために、ソース取り出し配線及びＰＳＧ膜を図示せず、ゲート取り出し配線を透過して示し、これに斜線を付す。 (Embodiment 4)
FIG. 14 is a plan view showing a main part of a power MISFET having a trench gate structure of a semiconductor device according to another embodiment of the present invention. FIG. 15 shows a line aa in FIG. It is a longitudinal cross-sectional view along line. In FIG. 14, for the sake of explanation, the source lead-out wiring and the PSG film are not shown, but are shown through the gate lead-out wiring, and are hatched.

本実施の形態のＭＩＳＦＥＴは、ＮＰＮ型であり、半導体基板主面の深層部であるＮ＋型層１上のＮ型層２をドレインとし、Ｎ型層２上に形成されたＰ−型層３をチャネルとしている。トレンチゲート４は、半導体基板主面に延設しＮ型層２に達する溝部にゲート絶縁膜となる酸化珪素膜５を介して設けられている。半導体基板主面の表層部のトレンチゲート４周辺に形成されるＮ＋型層６をソースとしている。   The MISFET of the present embodiment is an NPN type, and a P − type layer 3 formed on the N type layer 2 with the N type layer 2 on the N + type layer 1 which is a deep layer portion of the main surface of the semiconductor substrate as a drain. Is the channel. The trench gate 4 is provided in a groove extending to the main surface of the semiconductor substrate and reaching the N-type layer 2 via a silicon oxide film 5 serving as a gate insulating film. The source is an N + type layer 6 formed around the trench gate 4 in the surface layer portion of the main surface of the semiconductor substrate.

トレンチゲート４は、平面的に格子状に配置されるメッシュゲート構造となっているが、図１１中横方向に延在する各トレンチゲート４間に位置する縦方向のトレンチゲート４は交互に位置を変えて配置されている。各トレンチゲート４は半導体チップの外周部近傍にて終端しており、この終端部分にて半導体基板主面上のゲート取り出し配線７と接続している。   The trench gates 4 have a mesh gate structure that is arranged in a grid pattern on the plane, but the vertical trench gates 4 positioned between the trench gates 4 extending in the horizontal direction in FIG. It is arranged with changing. Each trench gate 4 terminates in the vicinity of the outer peripheral portion of the semiconductor chip, and is connected to the gate lead-out wiring 7 on the main surface of the semiconductor substrate at this termination portion.

半導体チップ外周部に沿って延在する電界緩和部８を半導体基板内に設け、この電界緩和部８にトレンチゲート４の終端部を接続する。電界緩和部８はＭＩＳＦＥＴの形成される領域を囲むようにして矩形環状に設けられ、電界の集中を防止するために、その角部に曲率をもたせて形成する。   An electric field relaxation portion 8 extending along the outer periphery of the semiconductor chip is provided in the semiconductor substrate, and the terminal portion of the trench gate 4 is connected to the electric field relaxation portion 8. The electric field relaxation portion 8 is provided in a rectangular ring shape so as to surround a region where the MISFET is formed, and is formed with a curvature at a corner portion thereof in order to prevent concentration of the electric field.

また、本実施の形態では、半導体チップ外周部に沿って延在し、トレンチゲート４の終端部を接続した電界緩和部８の周囲に、ドレインとは反対導電型で且つドレインよりも低濃度の不純物を注入した低濃度領域１２を設ける。
この低濃度領域１２の平面形状は、電界緩和部８と同様に、ＦＥＴの形成される領域を囲む矩形環状とする。 Further, in the present embodiment, around the electric field relaxation portion 8 extending along the outer peripheral portion of the semiconductor chip and connected to the terminal portion of the trench gate 4, the conductivity type is opposite to that of the drain and the concentration is lower than that of the drain. A low concentration region 12 into which impurities are implanted is provided.
The planar shape of the low concentration region 12 is a rectangular ring surrounding the region where the FET is formed, like the electric field relaxation portion 8.

本実施の形態では、前述した実施の形態と比較して、電界緩和部８をＦＥＴの形成される領域を囲む環状としても、この低濃度領域によって電界緩和部８形成に伴う容量の増加を抑制することができる。   In the present embodiment, compared to the above-described embodiment, even if the electric field relaxation portion 8 is formed in an annular shape surrounding the region where the FET is formed, this low concentration region suppresses an increase in capacitance due to the formation of the electric field relaxation portion 8. can do.

（実施の形態５）
図１６に示すのは、本発明の他の実施の形態である半導体装置のトレンチゲート構造のパワーＭＩＳＦＥＴの要部を表す平面図であり、図１７に示すのは、図１６中ａ‐ａ線に沿った縦断面図である。なお、図１６にては説明のために、ソース取り出し配線及びＰＳＧ膜を図示せず、ゲート取り出し配線を透過して示し、これに斜線を付す。 (Embodiment 5)
FIG. 16 is a plan view showing a main part of a power MISFET having a trench gate structure of a semiconductor device according to another embodiment of the present invention. FIG. 17 shows a line aa in FIG. It is a longitudinal cross-sectional view along line. In FIG. 16, for the sake of explanation, the source extraction wiring and the PSG film are not shown, but are shown through the gate extraction wiring, and are hatched.

本実施の形態のＭＩＳＦＥＴは、ＮＰＮ型であり、半導体基板主面の深層部であるＮ＋型層１上のＮ型層２をドレインとし、Ｎ型層２上に形成されたＰ−型層３をチャネルとしている。トレンチゲート４は、半導体基板主面に延設しＮ型層２に達する溝部にゲート絶縁膜となる酸化珪素膜５を介して設けられている。半導体基板主面の表層部のトレンチゲート４周辺に形成されるＮ＋型層６をソースとしている。   The MISFET of the present embodiment is an NPN type, and a P− type layer 3 formed on the N type layer 2 with the N type layer 2 on the N + type layer 1 which is a deep layer portion of the main surface of the semiconductor substrate as a drain. Is the channel. The trench gate 4 is provided in a groove portion extending to the main surface of the semiconductor substrate and reaching the N-type layer 2 via a silicon oxide film 5 serving as a gate insulating film. The source is an N + type layer 6 formed around the trench gate 4 in the surface layer portion of the main surface of the semiconductor substrate.

本実施の形態では、トレンチゲート４は、内方にチャネルとなるＰ−型層３およびソースとなるＮ型層６を平面形状円形に残す形で、矩形形状に略全面に形成されており、その周縁部分にて半導体基板主面上のゲート取り出し配線７と接続する。   In the present embodiment, the trench gate 4 is formed on the substantially entire surface in a rectangular shape in such a manner that the P-type layer 3 serving as a channel and the N-type layer 6 serving as a source are left in a planar shape circle inward. The peripheral edge portion is connected to the gate extraction wiring 7 on the main surface of the semiconductor substrate.

本実施の形態では、半導体チップ外周部に沿って延在する電界緩和部８を半導体基板内に設け、この電界緩和部８にトレンチゲート４の終端部を接続する。電界緩和部８はＭＩＳＦＥＴの形成される領域を囲むようにして矩形環状に設けられ、電界の集中を防止するために、その角部に曲率をもたせて形成する。   In the present embodiment, an electric field relaxation portion 8 extending along the outer periphery of the semiconductor chip is provided in the semiconductor substrate, and the terminal portion of the trench gate 4 is connected to the electric field relaxation portion 8. The electric field relaxation portion 8 is provided in a rectangular ring shape so as to surround a region where the MISFET is formed, and is formed with a curvature at a corner portion thereof in order to prevent concentration of the electric field.

本実施の形態のＦＥＴでは、トレンチゲート４が面状に終端し、形状誤差によって部分的に鋭角的に形成されることがないので、局部的に電界集中の起こることがないので、電界集中による高電界によってゲート絶縁膜となる酸化珪素膜５が破壊されることがない。   In the FET according to the present embodiment, the trench gate 4 terminates in a planar shape and is not partially formed at an acute angle due to a shape error. Therefore, the electric field concentration does not occur locally. The silicon oxide film 5 serving as a gate insulating film is not broken by a high electric field.

なお、本実施の形態のトレンチゲート４の内方に形成される、チャネルとなるＰ−型層３およびソースとなるＮ型層６を、円形の他に六角形或は八角形等の各内角が鈍角となる多角形等の平面形状としてもよい。   The P-type layer 3 serving as a channel and the N-type layer 6 serving as a source, which are formed inside the trench gate 4 of the present embodiment, can be formed into inner angles such as hexagons or octagons in addition to a circle. It is good also as planar shapes, such as a polygon used as an obtuse angle.

以上、本発明者によってなされた発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。
例えば本発明は、パワーＭＩＳＦＥＴ以外にも、ＩＧＢＴ（Integrated Gate Bipolar Transistor）等にも適用が可能である。 Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
For example, the present invention can be applied not only to a power MISFET but also to an IGBT (Integrated Gate Bipolar Transistor) or the like.

本発明の一実施の形態である半導体装置の要部を示す平面図である。It is a top view which shows the principal part of the semiconductor device which is one embodiment of this invention. 図１中のａ‐ａ線に沿った部分縦断面図である。FIG. 2 is a partial longitudinal sectional view taken along line aa in FIG. 1. 図１中のｂ‐ｂ線に沿った部分縦断面図である。It is the fragmentary longitudinal cross-section along the bb line in FIG. 本発明の一実施の形態である半導体装置の要部を製造工程毎に示す縦断面図である。It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. 本発明の一実施の形態である半導体装置の要部を製造工程毎に示す縦断面図である。It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. 本発明の一実施の形態である半導体装置の要部を製造工程毎に示す縦断面図である。It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. 本発明の一実施の形態である半導体装置の要部を製造工程毎に示す縦断面図である。It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. 従来の半導体装置の要部を示す平面図である。It is a top view which shows the principal part of the conventional semiconductor device. 図８中のａ‐ａ線に沿った部分縦断面図である。It is a fragmentary longitudinal cross-sectional view along the aa line in FIG. 本発明の一実施の形態である半導体装置と従来の半導体装置とのゲート耐圧の試験結果を示す図である。It is a figure which shows the test result of the gate pressure | voltage resistance of the semiconductor device which is one embodiment of this invention, and the conventional semiconductor device. 本発明の他の実施の形態である半導体装置の要部を示す平面図である。It is a top view which shows the principal part of the semiconductor device which is other embodiment of this invention. 図１１中のｃ‐ｃ線に沿った部分縦断面図である。It is a fragmentary longitudinal cross-sectional view along the cc line in FIG. 本発明の他の実施の形態である半導体装置の要部を示す平面図である。It is a top view which shows the principal part of the semiconductor device which is other embodiment of this invention. 本発明の他の実施の形態である半導体装置の要部を示す平面図である。It is a top view which shows the principal part of the semiconductor device which is other embodiment of this invention. 図１４中のａ‐ａ線に沿った部分縦断面図である。It is the fragmentary longitudinal cross-sectional view along the aa line | wire in FIG. 本発明の他の実施の形態である半導体装置の要部を示す平面図である。It is a top view which shows the principal part of the semiconductor device which is other embodiment of this invention. 図１６中のａ‐ａ線に沿った部分縦断面図である。It is a fragmentary longitudinal cross-sectional view along the aa line in FIG.

符号の説明Explanation of symbols

１…Ｎ＋層、２…Ｎ層（ドレイン）、３…Ｐ−層（チャネル）、４…トレンチゲート、５…酸化珪素膜、６…Ｎ＋層（ソース）、７…ゲート取りだし配線、８…電界緩和部、９…ＰＳＧ膜、１０…ソース取り出し配線、１１…多結晶シリコン、１２…低濃度領域。   DESCRIPTION OF SYMBOLS 1 ... N + layer, 2 ... N layer (drain), 3 ... P- layer (channel), 4 ... Trench gate, 5 ... Silicon oxide film, 6 ... N + layer (source), 7 ... Gate extraction wiring, 8 ... Electric field Relaxation part, 9 ... PSG film, 10 ... source extraction wiring, 11 ... polycrystalline silicon, 12 ... low concentration region.

Claims (5)

トレンチゲート構造の電界効果型トランジスタを含む半導体装置であって、
半導体基板と、
前記半導体基板の主面上に形成された、前記電界効果型トランジスタのゲート電極形成用の複数の第１トレンチ部と、
前記第１トレンチ部内に形成された、前記電界効果型トランジスタのゲート絶縁膜と、
前記第１トレンチ内の前記ゲート絶縁膜上に形成された、前記電界効果型トランジスタのゲート電極と、
前記半導体基板の主面上に形成され、前記複数の第１トレンチ部を接続するように前記第１トレンチ部の周辺に形成された第２トレンチ部と、
前記第２トレンチ部内に形成され、前記ゲート電極と電気的に接続された導電膜を有することを特徴とする半導体装置。 A semiconductor device including a field effect transistor having a trench gate structure,
A semiconductor substrate;
A plurality of first trench portions for forming a gate electrode of the field effect transistor formed on the main surface of the semiconductor substrate;
A gate insulating film of the field effect transistor formed in the first trench portion;
A gate electrode of the field effect transistor formed on the gate insulating film in the first trench;
A second trench portion formed on a main surface of the semiconductor substrate and formed around the first trench portion so as to connect the plurality of first trench portions;
A semiconductor device comprising: a conductive film formed in the second trench portion and electrically connected to the gate electrode. 前記第２トレンチ部および導電膜は電界緩和部として機能することを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the second trench part and the conductive film function as an electric field relaxation part. 前記第１および第２トレンチ部は同一工程によって形成されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first and second trench portions are formed by the same process. 前記ゲート電極および第２トレンチ部内の導電膜は同一工程によって形成されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the gate electrode and the conductive film in the second trench portion are formed in the same process. 前記第２トレンチ内の導電膜上にゲート取り出し配線が形成され、前記第２トレンチ内の導電膜と前記ゲート取り出し配線が電気的に接続されていることを特徴とする請求項１記載の半導体装置。
2. The semiconductor device according to claim 1, wherein a gate extraction wiring is formed on the conductive film in the second trench, and the conductive film in the second trench and the gate extraction wiring are electrically connected. .
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8076720B2 (en) 2007-09-28 2011-12-13 Semiconductor Components Industries, Llc Trench gate type transistor
US8242557B2 (en) 2007-09-28 2012-08-14 Semiconductor Components Industries, Llc Trench gate type transistor
WO2013047085A1 (en) 2011-09-26 2013-04-04 住友電気工業株式会社 Semiconductor device and method for producing semiconductor device
US8530966B2 (en) 2010-12-17 2013-09-10 Mitsubishi Electric Corporation Semiconductor device
CN104051503A (en) * 2013-03-15 2014-09-17 飞兆半导体公司 Methods and apparatus related to termination regions of a semiconductor device
JP2017037921A (en) * 2015-08-07 2017-02-16 トヨタ自動車株式会社 Igbt
CN106463539A (en) * 2014-05-01 2017-02-22 三菱电机株式会社 Semiconductor device
US10229969B2 (en) 2015-06-09 2019-03-12 Mitsubishi Electric Corporation Power semiconductor device
JPWO2020145109A1 (en) * 2019-01-08 2021-09-30 三菱電機株式会社 Semiconductor equipment and power conversion equipment

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01192175A (en) * 1988-01-27 1989-08-02 Hitachi Ltd Semiconductor device
JPH06204483A (en) * 1992-07-23 1994-07-22 Siliconix Inc Structure of high-voltage transistor and its formation
JPH08264787A (en) * 1995-01-10 1996-10-11 Siliconix Inc Edge termination method of power mosfet and its structure
JPH08298322A (en) * 1995-04-27 1996-11-12 Nippondenso Co Ltd Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01192175A (en) * 1988-01-27 1989-08-02 Hitachi Ltd Semiconductor device
JPH06204483A (en) * 1992-07-23 1994-07-22 Siliconix Inc Structure of high-voltage transistor and its formation
JPH08264787A (en) * 1995-01-10 1996-10-11 Siliconix Inc Edge termination method of power mosfet and its structure
JPH08298322A (en) * 1995-04-27 1996-11-12 Nippondenso Co Ltd Manufacture of semiconductor device

Cited By (25)

* Cited by examiner, † Cited by third party
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US8530966B2 (en) 2010-12-17 2013-09-10 Mitsubishi Electric Corporation Semiconductor device
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WO2013047085A1 (en) 2011-09-26 2013-04-04 住友電気工業株式会社 Semiconductor device and method for producing semiconductor device
US8610132B2 (en) 2011-09-26 2013-12-17 Sumitomo Electric Industries, Ltd. Semiconductor device and method for manufacturing semiconductor device
CN103748688A (en) * 2011-09-26 2014-04-23 住友电气工业株式会社 Semiconductor device and method for producing semiconductor device
US9184056B2 (en) 2011-09-26 2015-11-10 Sumitomo Electric Industries, Ltd. Semiconductor device and method for manufacturing semiconductor device
CN111106011A (en) * 2013-03-15 2020-05-05 飞兆半导体公司 Arrangement in connection with termination area of semiconductor device
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US9496391B2 (en) 2013-03-15 2016-11-15 Fairchild Semiconductor Corporation Termination region of a semiconductor device
EP2779248A3 (en) * 2013-03-15 2015-01-14 Fairchild Semiconductor Corporation Apparatus related to termination regions of a semiconductor device
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