JP2001284585A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vertical type power MOSFET having a high withstand voltage. SOLUTION: In the power MOSFET 1, a p-type active layer 13 is formed on an n-type drain layer 12. In the active layer 13, vertical holes 17 are formed from the surface and a p-type impurity is diffused around the vertical holes 17 to form current channel diffusion layers 19. In the active layer 13, there are depletion layers extended in the transverse direction from the current channel diffusion layers 19 into the active layer 13, and depletion layers extended in the vertical direction from the drain layer 12 into the active layer 13, with the depletion layers extended in the transverse direction and the depletion layers extended in the vertical direction being connected to each other. Due to the depletion layers extended into the active layer 13 from two directions, an electric field is distributed nearly evenly in the depletion layers, resulting in a higher withstand voltage than by the conventional method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly, to a power MOS transistor frequently used in a power supply circuit and the like.
Related to FET.

[0002]

2. Description of the Related Art Conventionally, a MOS in which a large number of cells are arranged is used.
Transistors are used as power control elements.

Referring to FIG. 45, reference numeral 105 denotes a conventional M
This is an example of an OS transistor, and is a silicon single crystal substrate 1
11 and a drain layer 112 epitaxially grown on the single crystal substrate 111.

The silicon single crystal 111 is heavily doped with N-type impurities, and the drain layer 112 is lightly doped with N-type impurities. In the drain layer 112, a P-type impurity is diffused from the surface,
A base region 154 is formed.

In the base region 154, N-type impurities are further diffused from the surface thereof to form a ring-shaped source region 1.
61 are formed. A region indicated by reference numeral 110 is a surface portion of the base region 154 located between an end portion of the base region 154 and an outer peripheral portion of the source region 161, and is called a channel region. The channel region 110;
One cell 101 is formed by the base region 154 and the source region 161. MOS transistor 105
In the first embodiment, a large number of cells 101 are regularly arranged in a grid on the surface of the drain layer 112.

FIG. 46 shows an arrangement state of the cell 101 of the MOS transistor 105. The surface of the base region 154 is exposed at the center of the ring of the source region 161 in each cell 101. Source region 161 surface and base region 1
A source electrode film 144 is formed on the surface of the source electrode film, and the source region 161 and the base region 154 are both connected to the source electrode film 144.

The channel region 11 in each cell 101
0 and on the surface of the drain layer 112 between the cells 101,
A gate insulating film 126 made of a silicon oxide film is provided. On this gate insulating film 126, a gate electrode film 127 made of polysilicon is arranged.

The interlayer insulating film 14 is formed on the gate electrode film 127.
1, the source electrode film 144 and the gate electrode film 127 formed on each cell 101 are insulated by the interlayer insulating film 141, and the source electrode film 144 Is the interlayer insulating film 141
They are connected to each other by a source electrode film 144 disposed thereon.

Reference numeral 150 denotes a protective film.
The source electrode 144 is partially exposed on the MOS transistor 105, and the metal film connected to the gate electrode film 127 is also partially exposed on the MOS transistor 105.

A drain electrode 148 is formed on the front surface of the single crystal substrate 111 (the back surface of the MOS transistor 105), and the drain electrode 148 and the source electrode 1
The exposed portion 44 and the exposed portion of the metal film connected to the gate electrode film 127 are connected to external terminals, respectively, and the MOS transistor is operated by connecting the external terminal to an electric circuit. ing.

When the MOS transistor 105 is used, the source electrode 144 is set at the ground potential, and the gate electrode film 127 is kept in a state where a positive voltage is applied to the drain electrode 148.
When a gate voltage (positive voltage) equal to or higher than the threshold is applied, an N-type inversion layer is formed on the surface of the P-type channel region 110, and the source region 161 and the conductive region 111 are connected by the inversion layer. A current flows through the source electrode 144.

When a voltage lower than the threshold voltage (eg, ground potential) is applied to the gate electrode film 127 in this state, the inversion layer disappears, and the base region 154 and the conductive region 11
1 and the drain electrode 148
No current flows between the gate electrode and the source electrode 144.

The MOS transistor 105 as described above
By controlling the voltage applied to the gate electrode film 127, the connection between the drain electrode 148 and the source electrode 144 can be turned on or off, so that the power of a power supply circuit, a motor control circuit, or the like can be used as a high-speed switch. Widely used for handling electrical circuits.

In the MOS transistor 105 having the above-described structure, a strong electric field is intensively applied to the pn junction formed between the channel region 110 and the drain layer 112. Layer 112
The drain layer 112 must be formed thick in order to lower the concentration of GaN and secure a region where the depletion layer spreads. However, such a configuration causes a problem that the conduction resistance of MOS transistor 105 is increased.

[0015]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned disadvantages of the prior art, and has as its object to reduce the conduction resistance of a field-effect transistor and reduce the withstand voltage. It is an object of the present invention to provide a technology that can increase the size of the image.

[0016]

According to a first aspect of the present invention, there is provided a field effect transistor, comprising: a first conductivity type drain layer; and a first conductivity type drain layer disposed on the drain layer. An active layer of a second conductivity type having a conductivity type opposite to the first conductivity type, and a source diffusion layer disposed on a surface side in the active layer and formed of the diffusion layer of the first conductivity type And a vertical hole formed at a position separated from the source diffusion layer, and the first conductivity type impurity is diffused into the active layer from at least a surface of the wall surface of the vertical hole facing the source diffusion layer. The formed current path diffusion layer, a filling material filling the inside of the vertical hole, and a surface near the surface in the active layer, located between the source diffusion layer and the current path diffusion layer, The second layer disposed in contact with the layer;
A conductive type channel region, a gate insulating film disposed on the channel region, a gate electrode disposed on the gate insulating film, a source electrode connected to the source diffusion layer, and a And a back electrode connected thereto. The invention according to claim 2 is the field-effect transistor according to claim 1, wherein the filler is made of a semiconductor material, and an insulating film is arranged between the semiconductor material and the current path diffusion layer. Insulated from each other. The invention according to claim 3 is the field-effect transistor according to claim 2, wherein the semiconductor material is placed at a floating potential. The invention according to claim 4 is the field-effect transistor according to claim 1, wherein the filler is made of an insulator. According to a fifth aspect of the present invention, there is provided any one of the first to fourth aspects.
3. The field effect transistor according to claim 1, wherein the bottom of the vertical hole is located in the active layer, and the current path diffusion layer is in contact with the drain layer. According to a sixth aspect of the present invention, in the field effect transistor according to any one of the first to fifth aspects, the bottom portion of the vertical hole is located in the drain layer, and the current path diffusion layer is located between the vertical hole and the vertical hole. And the current path diffusion layer is in contact with the drain layer. The invention according to claim 7 is the invention according to claims 1 to 6.
The field effect transistor according to any one of the above,
When forming the current path diffusion layer, the impurity of the first conductivity type is diffused from the bottom of the vertical hole into the active layer,
Part of the current path diffusion layer is located at the bottom of the vertical hole. The invention according to claim 8 is the field-effect transistor according to any one of claims 1 to 7, wherein the vertical hole is formed in an elongated groove, and the source diffusion layer is formed on both sides of the vertical hole. The channel region, the gate insulating film, and the gate electrode are arranged. According to a ninth aspect of the present invention, in the field effect transistor according to any one of the first to eighth aspects, the surface in the channel region has a second conductive layer having a higher surface concentration than the active layer. The main diffusion layer of the mold is arranged. According to a tenth aspect of the present invention, in the field effect transistor according to any one of the first to ninth aspects, a sub-diffusion layer of a second conductivity type is provided in the main diffusion layer. The sub-diffusion layer is diffused from the front side, and the surface concentration of the sub-diffusion layer is higher than that of the main diffusion layer, and the sub-diffusion layer is connected to the source electrode. An eleventh aspect of the present invention is the field-effect transistor according to any one of the first to tenth aspects, wherein the drain layer comprises:
The semiconductor device is formed on a semiconductor layer of the same conductivity type as the drain layer, and the back surface electrode is connected to the semiconductor layer. Claim 12
The field-effect transistor according to any one of claims 1 to 10, wherein the drain layer is formed on a semiconductor layer having a conductivity type opposite to that of the drain layer. Is connected to the back electrode.

According to the field effect transistor of the present invention,
In the active layer in which the impurity of the second conductivity type is diffused,
A depletion layer extending laterally from the current path diffusion layer into which the impurity of the first conductivity type is diffused into the active layer; and a depletion layer extending vertically from the drain layer into which the impurity of the first conductivity type is diffused into the active layer. A depletion layer is generated, and the depletion layer extending in the horizontal direction and the depletion layer expanding in the vertical direction are connected. As described above, since the depletion layer spreads in the active layer from two directions, the electric field in the depletion layer is distributed almost uniformly, so that a higher breakdown voltage can be obtained as compared with the related art.

When such a field-effect transistor is set to the same withstand voltage as the conventional one, the impurity concentration of the drain layer can be increased and the thickness of the drain layer can be reduced. And the conduction resistance of the field effect transistor can be reduced.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. First, a method for manufacturing a vertical power MOSFET according to an embodiment of the present invention will be described with reference to FIGS. In the drawings, the same members are denoted by the same reference numerals.

First, a drain layer 12 made of a 5 μm thick N ⁻ -type epitaxial layer is formed on the surface of an N ⁺ -type silicon substrate 11. Next, on the drain layer 12, P
An active layer 13 of a type epitaxial layer is formed to a thickness of 27 μm, and a silicon oxide film 14 is formed on the surface of the active layer 13 by a CVD method (FIG. 1).

Next, a resist film 15 is formed on the surface so that a plurality of elongated openings 16 are parallel to each other at predetermined intervals (FIG. 2), and a silicon oxide film is formed using the resist film 15 as a mask. 14 and the active layer 1
3 is exposed (FIG. 3). Here, the interval between the openings 16 is 16 μm, and the width of the openings 16 is 2 μm.

Next, the resist film 15 is removed, and the active layer 13 is etched for a predetermined time using the silicon oxide film 14 as a mask. A plurality of deep holes 17 whose bottoms do not reach the drain layer 12 are formed (FIG. 4). Here, the depth of the deep hole 17 is 25 μm.

Next, when polysilicon doped with phosphorus is deposited from the surface of the silicon oxide film 14 to the inside of the deep hole 17, a polysilicon film 18 is formed.
The inside of the deep hole 17 is filled with a polysilicon film 18 (FIG. 5).

Next, when a heat treatment is performed, the phosphorus in the polysilicon thin film 18 filling the inside of the deep hole 17 is diffused into the active layer 13 from the side wall surface and bottom surface of the deep hole 17, and the side wall surface of the deep hole 17 and A current path diffusion layer 19 formed by diffusing an N-type impurity is formed near the bottom surface (FIG. 6).

Next, when the polysilicon film 18 is etched for a predetermined time, the polysilicon film 18 on the surface of the silicon oxide film 14 and inside the deep hole 17 is completely removed.
(FIG. 7). Next, after the silicon oxide film 14 is removed by etching (FIG. 8), a thermal oxide film 20 is formed to a thickness of 50 nm from the surface of the active layer 13 to the inner side surface and the inner bottom surface of the deep hole 17 by thermal oxidation (FIG. 8). (FIG. 9).

Next, when polysilicon is deposited on the entire surface by the CVD method, the polysilicon film 21 becomes the active layer 13.
And is filled in the deep hole 17. Hereinafter, the polysilicon filled in the deep hole 17 is referred to as a filling material, and is indicated by reference numeral 91 (FIG. 10).

Next, when the polysilicon film 21 is etched for a predetermined time, the polysilicon film 21 on the active layer 13 is removed, and the deep hole 17 is filled with only the filling material 91 (FIG. 11).

Next, when the thermal oxide film 20 is etched for a predetermined time, the thermal oxide film 20 on the active layer 13 is removed, and the thermal oxide film 20 remains on the inner side surface and the inner bottom surface of the deep hole 17 (FIG. 12).

Next, a silicon oxide film 2 is formed on the entire surface by CVD.
2 is formed to a thickness of 100 nm, and then a silicon oxide film 22 is formed.
A polysilicon thin film 23 is formed thereon to a thickness of 500 nm.
(FIG. 13).

Next, the patterned resist film 2
4 is formed on the polysilicon thin film 23. The openings 25 of the resist film 24 are elongated on the polysilicon thin film 23 between the fillings 19 adjacent to each other so as to be parallel to each other at predetermined intervals (FIG. 14). Thereafter, when the polysilicon thin film 23 is etched and removed using the resist film 24 as a mask, the polysilicon thin film 23 exposed from the opening 25 is removed. Hereinafter, the polysilicon thin film remaining after the etching is referred to as a gate electrode, and is denoted by reference numeral 27. In this state, the silicon oxide film 22 is exposed from the bottom of the opening 25 (FIG. 15).

Next, the silicon oxide film 22 exposed from the bottom of the opening 25 is removed by etching. In this state,
The surface of the active layer 13 is exposed from the bottom of the opening 25 (FIG. 1).
6). Hereinafter, the silicon oxide film remaining under the gate electrode 27 after the etching is referred to as a gate insulating film, and is indicated by reference numeral 26.

Next, after removing the resist film 24, C
A base oxide film 28 is formed on the surface of the gate electrode 27 and the surface of the active layer 13 by the VD method (FIG. 17). Next, when the entire surface is irradiated with boron ions, the gate electrode 27 serves as a mask, and the active layer 1 in the region between the adjacent gate electrodes 27 is formed.
Boron ions are implanted into the three surfaces to form a P-type implanted layer 29 (FIG. 18).

Next, when heat treatment is performed, the P-type injection layer 29 is formed.
Are diffused in the active layer 13, and a plurality of elongated main diffusion layers 30 are formed in the depth direction from the surface of the active layer 13, each of which is formed of a P-type impurity diffusion layer according to the pattern of the opening 25 (FIG. 1).
9). Here, a main diffusion layer 30 having a depth of 2 μm is formed. The main diffusion layer 30 has an end portion at the gate electrode 27.
And is formed so as to be separated from the current path diffusion layer 19.

Next, a patterned resist film 31 is formed on the underlying oxide film 28. The resist film 31
Are formed to be elongated, and are arranged so as to be located substantially at the center of each main diffusion layer 30 (FIG. 20). In that state,
When the entire surface is irradiated with boron ions, boron ions are implanted into the surface of each main diffusion layer 30 through each opening 32 to form a P-type implanted layer 33 (FIG. 21).

Next, when the resist film 31 is removed and then heat-treated, the P-type implanted layer 33 is diffused in the main diffusion layer 30 and P-type impurities are diffused from the surface of the main diffusion layer 30 in the depth direction. A plurality of elongated sub-diffusion layers 34 are formed.
(FIG. 22).

Next, the underlying oxide film 28 on each sub-diffusion layer 34
After forming a plurality of elongated resist films 35 on the sub-diffusion layer 34 and slightly smaller than the width of the sub-diffusion layer 34,
(FIG. 23), when the entire surface is irradiated with arsenic ions,
Arsenic ions are implanted into the main diffusion layers 30 on both sides of the substrate 4, respectively, to form elongated N-type implanted layers 36 (FIG. 24).

Next, when the resist film 35 is removed and heat-treated, the N-type implanted layer 36 is diffused in the main diffusion layer 30,
From the surface of the main diffusion layer 30, a plurality of elongated source diffusion layers 37 formed by diffusing N-type impurities are formed (FIG. 25). The end of the source diffusion layer 37 is located below the end of the gate electrode 37, and is located inside the end of the main diffusion layer 30. Therefore, the surface of the active layer 13 between the current path diffusion layer 19 and the source diffusion layer 37 is
And a main diffusion layer 30, and the active layer 13 and the main diffusion layer 30 form a channel region indicated by reference numeral 99 in FIG.

Next, an interlayer insulating film 38 made of a PSG film is formed on the entire surface of the underlying oxide film 28 (FIG. 26). After that, a patterned resist film 40 is formed on the interlayer insulating film 38. The opening 53 of the resist film 40 is narrowly arranged over the sub-diffusion layer 34 and the formation region of the source diffusion layer 37 on both sides thereof (FIG. 27).

Next, the interlayer insulating film 38 and the underlying oxide film 28 are etched using the resist film 40 as a mask.
The sub-diffusion layer 34 and the source diffusion layers 37 on both sides thereof are exposed from the bottom surface of the opening 53. When the resist film 40 is removed,
A hole 54 penetrating through the interlayer insulating film 38 and the base oxide film 28 is formed, and the sub-diffusion layer 34 and the source diffusion layers 37 on both sides thereof are exposed from the bottom surface of the hole 54 (FIG. 28).

Thereafter, a source electrode film 41 is formed by forming an Al thin film on the entire surface by sputtering, and the source electrode film 41 is formed by the sub-diffusion layer 34 and the source diffusion layers 3 on both sides thereof.
7 is connected. Thereafter, a metal thin film is formed on the back surface of the substrate by an evaporation method, and a drain electrode film 51 is formed. Then
The drain electrode film 51 is connected to the silicon substrate 11. Through the above steps, the power M shown in FIG.
OSFET1 is formed. FIG. 31 shows a power MOSF
FIG. 4 shows a plan view of an element peripheral portion of ET1. FIG. 29 corresponds to a sectional view taken along line BB of FIG.

When this power MOSFET 1 is used, the source electrode 41 is set at the ground potential and the drain electrode 5
When a gate voltage (positive voltage) equal to or higher than a threshold is applied to the gate electrode 27 while a positive voltage is applied to the N.1, an N-type inversion layer is formed on the surface of the P-type main diffusion layer 30, and the source diffusion layer 37 and the current The channel diffusion layer 19 is connected to the channel diffusion layer 19 by an inversion layer, and as shown in FIG.
9, a current I flows to the source electrode 41 via the inversion layer and the source diffusion layer 37 in this order.

The inside of the power MOSFET 1 of this embodiment is
FIG. 32 shows the electric field intensity distribution. The vertical axis of the graph of FIG.
(E) shows the magnitude of the electric field strength, and the horizontal axis (y) shows the figure.
Table of the main diffusion layer 30 of the power MOSFET 1 shown in FIG.
With the surface as the origin, N ⁺Mold silicon substrate 11
The position on the line segment that reaches vertically is shown.

The line AA in FIG. 30 reaches the N ⁺ type silicon substrate 11 from one point in the sub-diffusion layer 34 through the active layer 13 and the drain layer 12 without passing through the source diffusion layer 37. 32 shows a line segment, and a broken line (A) in FIG. 32 is a graph showing a relationship between a position on the AA line and an electric field intensity.

In the power MOSFET 1 of the present embodiment,
In the active layer 13, a depletion layer extending in the lateral direction from the current path diffusion layer 19 into which the N-type impurity is diffused into the active layer 13, and a drain layer 12 from which the N-type impurity is diffused to the active layer 13 are formed. A depletion layer extending in the vertical direction is generated inside, and the depletion layer expanding in the horizontal direction and the depletion layer expanding in the vertical direction are connected.

Therefore, the electric field strength in the active layer 13 is
As shown by the polygonal line (A), a constant value is taken, and the maximum electric field strength S is taken at the pn junction (x _{2 of the} horizontal axis y) between the active layer 13 and the drain layer 12.

In FIG. 32, the polygonal line (B) indicates the electric field intensity distribution of the device in which the current path diffusion layer 19 is not formed in the power MOSFET 1 of the present embodiment. The broken line (B) shows the relationship between the position on the line AA in FIG. 30 and the electric field strength when the same maximum electric field strength S as that of the broken line (A) is applied.

In this case, there is no depletion layer extending in the horizontal direction from current path diffusion layer 19 to active layer 13, and only a depletion layer extending in the vertical direction from drain layer 12 to active layer 13 is present. Will do. Therefore, a broken line
As shown in (B), the electric field strength takes the maximum value at the pn junction (x _{2 of the} horizontal axis y) between the active layer 13 and the drain layer 12, but differs from the electric field strength shown by the polygonal line (A). , Main diffusion layer 3
It always takes 0 in 0, and in the active layer 13 (x ₁ to x _{2 on the} horizontal axis)
In the active layer 13, the electric field intensity E monotonically increases.
Cannot take a constant value.

When the integrated values obtained by integrating the electric field strengths shown in the broken line (A) and the broken line (B) in the depth direction are compared, the broken line
The integral value of the electric field strength shown in FIG. 3A is larger than the integral value of the broken line B. Since this integrated value corresponds to the withstand voltage, the withstand voltage of the power MOSFET 1 of the present embodiment is smaller than that of an element in which the depletion layer extends only in one direction, such as an element without the current path diffusion layer 19. Get higher. Also in the conventional device, the depletion layer extends in only one direction, so that the power MOSFET 1 of the present embodiment has a higher breakdown voltage than the conventional device.

The power MOSFET 1 according to the present embodiment
Is set to the same withstand voltage as before, the drain layer 1
2 can be increased and the thickness of the drain layer 12 can be reduced, so that the resistance component of the drain layer 12 can be reduced as compared with the related art, and the conduction resistance can be reduced.

FIG. 33 is a cross-sectional view of the peripheral portion of the power MOSFET 1 described above. FIG. 33 is a cross-sectional view of CC of FIG.
It is a line sectional view. As shown in FIG. 33, a thermal oxide film 80 formed simultaneously with the thermal oxide film 20 formed inside the deep hole 17 is formed on the inner wall surface of a vertical hole formed so as to surround the element around the element. A filling material 81 formed simultaneously with the filling material 91 and made of polysilicon is formed therein. An N-type diffusion region 79 formed in the same step as the current path diffusion layer 19 is formed around the filler 81 and the thermal oxide film 80.

Although the planar structure of the power MOSFET 1 is shown in FIG. 31, the present invention is not limited to this. As shown in FIG. 34, a filling material 91 made of polysilicon is formed in a lattice shape. The planar structure may be such that the sub-diffusion layer 34, the source diffusion layer 37, the current path diffusion layer 19, and the thermal oxide film 20 are formed in an island shape.

Further, the above-mentioned power MOSFET 1 is configured such that the thermal oxide film 20 is formed on the inner wall surface of the vertical hole 17, the filling material 91 is formed on the surface of the thermal oxide film 20, and the vertical hole 17 is filled. However, the field effect transistor of the present invention is not limited to this. For example, as shown in FIG.
7 may be configured as the power MOSFET 61. FIG. 37 is a cross-sectional view of the element periphery of the power MOSFET 61, and FIG.
Shown in FIGS. 35 and 37 correspond to the sectional view taken along the line DD and the line EE of FIG. 38, respectively.

Although the planar structure of the power MOSFET 61 is shown in FIG. 38, the present invention is not limited to this. As shown in FIG. 39, a filling 91 made of polysilicon is formed in a lattice shape. The planar structure may be such that the sub-diffusion layer 34, the source diffusion layer 37, and the current path diffusion layer 19 are formed in an island shape.

Further, the structure of the field effect transistor of the present invention is the same as that of the power MOSFETs 1 and 61 described above.
However, as shown in FIG. 36, for example, as shown in FIG. 36, the power MOSFET 6 having a structure in which the deep hole 17 is filled with only the filling 63 made of an insulating film such as a silicon oxide film.
It may be 2.

Further, the above-mentioned power MOSFETs 1, 6
1 and 62, an N ⁺ type silicon substrate 1 is used as a semiconductor substrate.
1 was used, but the structure of the field effect transistor of the present invention is not limited thereto, N ⁺ -type silicon substrate 11
An IGBT (Insulated gate bipolar transistor) having a structure whose cross section is shown in FIG.
ansistor) 64.

Further, the power MOSFET 1 described above,
61 and 62 and the IGBT 64, the bottom of the vertical hole 17 is formed so as not to reach the surface of the drain layer 12. However, the field effect transistor of the present invention is not limited to this. Power MOS having a structure in which the bottom of the vertical hole 17 reaches the drain layer 12
The FET 67 may be used. Similarly, in a structure in which the bottom of the vertical hole 17 reaches the drain layer 12, as shown in FIG.
A power MOSFET 65 having a structure in which only the filling 63 made of an insulating film is filled in the vertical hole 17 as shown in FIG.
The SFET 66 may be configured.

[0057] The field effect transistor structure in which the bottom portion of the vertical hole 17 reaches the drain layer 12 is not limited to the power MOSFET65,66,67 described above, P-type silicon in place of the N ⁺ -type silicon substrate 11 IGBT having a structure using a substrate 81 and having a cross section shown in FIG.
It may be 64.

In this embodiment, the N type is the first conductivity type and the P type is the second conductivity type.
5 and the P ⁺ type diffusion region 24 constitute an example of the opposite conductive region of the present invention, but the present invention is not limited to this, and the P type is the first conductive type and the N type is the second conductive type. It may be a type.

Although an Al film is used as the source electrode film 37, the present invention is not limited to this. For example, a copper film may be used. Furthermore, although the drain layer 12 is formed by epitaxial growth, the method of forming the drain layer 12 of the present invention is not limited to this, and may be formed by surface diffusion.

In each of the above embodiments, a silicon substrate is used as a semiconductor substrate. However, the semiconductor substrate of the present invention is not limited to this, and may be applied to a substrate such as SiC.

Although the silicon oxide film is used as the gate insulating film 19, the gate insulating film 19 of the present invention is not limited to this. For example, a silicon nitride film may be used, or a silicon oxide film and a silicon nitride film may be used. May be used.

[0062]

The withstand voltage of the power MOSFET can be increased. When the breakdown voltage is the same as in the conventional case, the conduction resistance is smaller than in the conventional case.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a power MOSFET according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating a subsequent step.

FIG. 3 is a sectional view illustrating a subsequent step.

FIG. 4 is a sectional view illustrating a subsequent step.

FIG. 5 is a sectional view illustrating a subsequent step.

FIG. 6 is a sectional view illustrating a subsequent step.

FIG. 7 is a sectional view illustrating a subsequent step.

FIG. 8 is a sectional view illustrating a subsequent step.

FIG. 9 is a sectional view illustrating a subsequent step.

FIG. 10 is a sectional view illustrating a subsequent step.

FIG. 11 is a sectional view illustrating a subsequent step.

FIG. 12 is a sectional view illustrating a subsequent step.

FIG. 13 is a sectional view illustrating a subsequent step.

FIG. 14 is a sectional view illustrating a subsequent step.

FIG. 15 is a sectional view illustrating a subsequent step.

FIG. 16 is a sectional view illustrating a subsequent step.

FIG. 17 is a sectional view illustrating a subsequent step.

FIG. 18 is a sectional view illustrating a subsequent step.

FIG. 19 is a sectional view illustrating a subsequent step.

FIG. 20 is a sectional view illustrating a subsequent step.

FIG. 21 is a sectional view illustrating a subsequent step.

FIG. 22 is a sectional view illustrating a subsequent step.

FIG. 23 is a sectional view illustrating a subsequent step.

FIG. 24 is a sectional view illustrating a subsequent step.

FIG. 25 is a sectional view illustrating a subsequent step.

FIG. 26 is a sectional view illustrating a subsequent step.

FIG. 27 is a sectional view illustrating a subsequent step.

FIG. 28 is a sectional view illustrating a subsequent step.

FIG. 29 is a sectional view illustrating a subsequent step.

FIG. 30 is a sectional view for explaining the operation of the power MOSFET according to one embodiment of the present invention;

FIG. 31 is a plan view of a power MOSFET according to an embodiment of the present invention.

FIG. 32 is a graph illustrating an electric field intensity distribution inside a power MOSFET according to an embodiment of the present invention.

FIG. 33 is a sectional view of a peripheral portion of the power MOSFET according to the embodiment of the present invention;

FIG. 34 is a plan view illustrating another plan structure of the power MOSFET according to the embodiment of the present invention.

FIG. 35 is a sectional view illustrating an element structure in which only a polysilicon thin film is filled in a vertical hole in a power MOSFET according to an embodiment of the present invention.

FIG. 36 is a cross-sectional view illustrating an element structure in which only an insulating film is filled in a vertical hole in a power MOSFET according to an embodiment of the present invention.

FIG. 37 is a cross-sectional view of a peripheral portion of an element in which only a polysilicon thin film is filled in a vertical hole in a power MOSFET according to an embodiment of the present invention;

FIG. 38 is a plan view including a peripheral portion of an element in which only a polysilicon thin film is filled in a vertical hole in a power MOSFET according to an embodiment of the present invention.

FIG. 39 is a plan view illustrating an example of another planar structure of an element in which only a polysilicon thin film is filled in a vertical hole in a power MOSFET according to an embodiment of the present invention.

FIG. 40 is a cross-sectional view illustrating an IGBT of one embodiment of the present invention.

FIG. 41 is a cross-sectional view illustrating an element structure in which the bottom of the vertical hole reaches the drain layer in the power MOSFET according to the embodiment of the present invention;

FIG. 42 is a cross-sectional view illustrating an IGBT having a structure in which the bottom of a vertical hole reaches a drain layer in the field-effect transistor of the present invention.

FIG. 43 is a cross-sectional view illustrating an element structure in which the bottom of the vertical hole reaches the drain layer and only the polysilicon thin film is filled in the vertical hole in the power MOSFET according to one embodiment of the present invention;

FIG. 44 is a cross-sectional view illustrating an element structure in which the bottom of the vertical hole reaches the drain layer and only the insulating film is filled in the vertical hole in the power MOSFET according to the embodiment of the present invention;

FIG. 45 is a cross-sectional view illustrating the structure of a conventional MOSFET.

FIG. 46 is a plan view illustrating the structure of a conventional MOSFET.

[Explanation of symbols]

1, 61, 62, 65, 66 ... Power MOSFET
(Field effect transistors) 64, 68 IGBT (Field effect transistor) 11 Silicon substrate (semiconductor layer) 12 Drain layer 13 Active layer 19
... Current path diffusion layer 21... Insulating film 26... Gate insulating film 27... Gate electrode 30... Primary diffusion layer 34.
41 ... source electrode 51 ... drain electrode 91
…… filling

Claims (12)

[Claims] A drain layer of a first conductivity type; an active layer of a second conductivity type disposed on the drain layer and having a conductivity type opposite to the first conductivity type; A source diffusion layer formed of the diffusion layer of the first conductivity type, a vertical hole formed at a position separated from the source diffusion layer, and at least the source diffusion of a wall surface of the vertical hole. A current path diffusion layer formed by diffusing the first conductivity type impurity into the active layer from a surface facing the layer; a filler filling the vertical hole; and a surface near the surface in the active layer. A second conductive type channel region located between the source diffusion layer and the current path diffusion layer and in contact with the source diffusion layer; and a gate disposed on the channel region. An insulating film; and a gate disposed on the gate insulating film. Gate electrode and a source electrode connected to the source diffusion layer, a field effect transistor having a back surface electrode connected to the drain layer. 2. The field effect transistor according to claim 1, wherein the filling is made of a semiconductor material, and an insulating film is arranged between the semiconductor material and the current path diffusion layer, and is insulated from each other. 3. The field effect transistor of claim 2, wherein said semiconductor material is at a floating potential. 4. The method according to claim 1, wherein the filling is made of an insulating material.
A field-effect transistor according to claim 1. 5. The field effect transistor according to claim 1, wherein the bottom of the vertical hole is located in the active layer, and the current path diffusion layer is in contact with the drain layer. 6. The vertical hole is located in the drain layer, the current path diffusion layer is extended to a position deeper than the vertical hole, and the current path diffusion layer is in contact with the drain layer. The field-effect transistor according to claim 5. 7. When forming the current path diffusion layer, the impurities of the first conductivity type are diffused from the bottom of the vertical hole into the active layer, and a part of the current path diffusion layer is formed at the bottom of the vertical hole. The field-effect transistor according to claim 1, wherein 8. The vertical hole is formed in an elongated groove, and the source diffusion layer, the channel region, the gate insulating film, and the gate electrode are arranged on both sides of the vertical hole. The field-effect transistor according to claim 1. 9. The electric field according to claim 1, wherein a main diffusion layer of a second conductivity type having a higher surface concentration than the active layer is disposed on a surface in the channel region. Effect transistor. 10. A sub-diffusion layer of a second conductivity type is diffused into the main diffusion layer from the surface side of the active layer, and the surface concentration of the sub-diffusion layer is made higher than that of the main diffusion layer. The field effect transistor according to claim 1, wherein a sub-diffusion layer is connected to the source electrode. 11. The semiconductor device according to claim 1, wherein the drain layer is formed on a semiconductor layer of the same conductivity type as the drain layer, and the back electrode is connected to the semiconductor layer.
Item 3. The field-effect transistor according to Item 1. 12. The semiconductor device according to claim 1, wherein the drain layer is formed on a semiconductor layer having a conductivity type opposite to that of the drain layer, and the back electrode is connected to the semiconductor layer. Field effect transistor.