JP2017188562A - Switching element and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology for suppressing increase in a gate threshold of a switching element.SOLUTION: A trench is formed, a second conductivity type impurity is injected in a direction where a perpendicular rising on a top face of a semiconductor substrate is inclined around an axis extending in a width direction of the trench, to a bottom face of the trench and a side face in a length direction, and a first conductivity type impurity is injected in a direction where the perpendicular is inclined around an axis extending in the length direction of the trench. The second conductivity type impurity injected to a side face in the width direction of the trench in an injection step of the second conductivity type impurity is cancelled by the first conductivity type impurity injected to the side face in the width direction of the trench in the injection step of the first conductivity type impurity, thereby suppressing increase in a gate threshold.SELECTED DRAWING: Figure 8

Description

  The present specification discloses a switching element and a manufacturing method thereof.

  A switching element having a gate electrode disposed in a trench has been developed. This type of switching element uses a semiconductor substrate in which a first conductivity type source region, a second conductivity type body region, and a first conductivity type drift region are stacked, and drifts through the source region and the body region. A trench reaching the region is formed, and a gate electrode is provided in the trench. In the switching element of Patent Document 1, the bottom region of the second conductivity type is formed in a range in the drift region and in contact with the bottom surface of the trench. Further, a connection region of the second conductivity type is provided in a range in contact with the side surface in the longitudinal direction of the trench, and the body region and the bottom region are made conductive. Providing the bottom region can suppress the occurrence of electric field concentration in the semiconductor material located near the bottom surface of the trench when the switching element is turned off. When the connection region is provided, carriers can enter and exit from the bottom region, and an increase in resistance when the switching element is on can be suppressed.

  In the method for manufacturing a switching element disclosed in Patent Document 1, a trench is formed in a semiconductor substrate, and a second conductivity type impurity is implanted into the bottom surface and the side surface in the longitudinal direction of the trench. Patent Document 2 will be described later.

JP 2007-242852 A JP2013-219161A

  When the impurity is implanted into the bottom surface of the trench, the impurity is implanted from the direction perpendicular to the upper surface of the semiconductor substrate. At this time, it is difficult to make the movement direction of the impurity and the side surface of the trench completely parallel, and the impurity is also implanted into the side surface of the trench. Further, when the impurity is implanted into the side surface in the longitudinal direction of the trench, the impurity is implanted from a direction in which the perpendicular is inclined around an axis extending in the short direction of the trench. Also in this case, it is difficult to make the movement direction of the impurity and the side surface in the short direction of the trench completely parallel, and the impurity is also implanted into the side surface in the short direction of the trench. In any of the above cases, the second conductivity type impurity is implanted from the direction in which the vertical line standing on the upper surface of the semiconductor substrate is inclined around the axis extending in the short direction of the trench. At that time, it is difficult to make the lateral side of the trench and the moving direction of the impurity completely parallel, and the lateral side of the trench is orthogonal to the upper surface of the semiconductor substrate due to the tolerance of the implantation direction. However, the second conductivity type impurity is implanted into the lateral side surface of the trench.

  In addition, the side surface of the actual trench formed in the semiconductor substrate is not perpendicular to the upper surface of the semiconductor substrate, and is inclined so that the width of the upper end of the trench is wider than the width of the bottom of the trench. The fact that the side surface in the short direction of the trench is inclined also means that the trench is formed in the above-described implantation step (injecting from the direction in which the vertical line standing on the upper surface of the semiconductor substrate is inclined around the axis extending in the short direction of the trench). This induces the phenomenon that impurities are implanted also in the lateral direction of the.

  The semiconductor region located near the lateral side surface of the trench is a region where a channel is formed when the switching element is turned on. When the second conductivity type impurity is implanted into the lateral side surface of the trench, the gate threshold value increases. The present specification discloses a switching element that can suppress an increase in gate threshold value caused by the implantation of the second conductivity type impurity into the lateral side surface of the trench, and a manufacturing method thereof.

In this specification, the following switching element, that is, a trench provided on the upper surface of a semiconductor substrate, a gate insulating film covering the inner surface of the trench, and a semiconductor substrate disposed in the trench and gate insulating film. A gate electrode insulated from the first conductive type source region in contact with the gate insulating film on the lateral side surface of the trench, and in contact with the gate insulating film below the source region on the lateral side surface of the trench. A second conductivity type body region, a first conductivity type drift region that is in contact with the gate insulating film below the body region on the side surface in the lateral direction and separated from the source region by the body region; The bottom region of the second conductivity type in contact with the gate insulating film at the bottom of the trench, and the gate insulating film at the side surface in the longitudinal direction of the trench. It discloses a method for producing a switching device having a bottom region and the connection region of the second conductivity type connecting the body regions together is.
The manufacturing method includes a step of forming a trench, and a second conductive layer extending from a direction in which a perpendicular standing on an upper surface of a semiconductor substrate is inclined around an axis extending in a short direction of the trench to a bottom surface and a longitudinal side surface of the trench. And a step of injecting a first conductivity type impurity into a lateral side surface of the trench from a direction in which the perpendicular is inclined around an axis extending in the longitudinal direction of the trench.

When a second conductivity type impurity is implanted into the bottom surface of the trench and the side surface in the longitudinal direction from the direction in which the vertical line standing on the upper surface of the semiconductor substrate is inclined around the axis extending in the short direction of the trench, it comes into contact with the bottom surface of the trench. The bottom region of the second conductivity type is formed in the area, and the connection region of the second conductivity type is formed in the area in contact with the side surface in the longitudinal direction of the trench. At this time, the second conductivity type impurity is also implanted into the lateral surface due to the tolerance of the implantation direction and / or the inclination of the lateral surface in the lateral direction.
In the manufacturing method described above, in addition to the implantation step described above, a first vertical line formed on the upper surface of the semiconductor substrate is inclined from an axis extending in the longitudinal direction of the trench to a side surface in the short direction of the trench. A step of implanting a conductive impurity; When the first conductivity type impurity is implanted from the direction in which the vertical line standing on the upper surface of the semiconductor substrate is inclined around the axis extending in the longitudinal direction of the trench, the first conductivity type impurity is implanted into the lateral side surface of the trench. .

  According to the manufacturing method, in the impurity implantation process for forming the bottom region and the connection region, the second conductivity type impurity is also implanted into the lateral surface of the trench and the lateral surface of the trench. Thus, the first conductivity type impurity is implanted. The influence of the second conductivity type impurity due to the former phenomenon can be reduced or eliminated by the first conductivity type impurity due to the latter phenomenon. That is, it is possible to reduce or eliminate the problem that the gate threshold value increases due to the implantation of the second conductivity type impurity into the lateral side surface of the trench.

  It is to be noted that impurities for forming the bottom region and the connection region are introduced by injecting the second conductivity type impurity from the direction in which the vertical line standing on the upper surface of the semiconductor substrate is inclined around the axis extending in the short direction of the trench. The step of injecting may be performed in a plurality of times or may be performed once. The bottom region implantation step and the connection region implantation step may be performed separately, or a necessary impurity concentration may be implanted into the bottom region during the connection region implantation step. In addition, the context of the implantation process of the second conductivity type impurity to the bottom surface and the side surface in the longitudinal direction of the trench and the implantation process of the first conductivity type impurity to the side surface in the short direction of the trench are not limited. When the second conductivity type impurity implantation step is performed in a plurality of times, the first conductivity type impurity implantation step may be performed in the middle of the process.

  As used herein, “longitudinal side surface” refers to a side surface serving as an end surface in the longitudinal direction of the trench, and “short side surface” refers to a side surface serving as an end surface in the short direction of the trench. I mean.

  As described above, the switching element disclosed in the present specification includes a trench provided on the upper surface of the semiconductor substrate, a gate insulating film covering the inner surface of the trench, and a gate insulating film disposed in the trench. A gate electrode insulated from the semiconductor substrate by the gate, a first conductivity type source region in contact with the gate insulating film on the lateral side of the trench, and gate insulation below the source region on the lateral side of the trench A second conductivity type body region in contact with the film, and a first conductivity type drift in contact with the gate insulating film below the body region on the side surface in the short direction and separated from the source region by the body region Region, the bottom region of the second conductivity type in contact with the gate insulating film at the bottom surface of the trench, and the gate insulation at the side surface in the longitudinal direction of the trench And a connection region of the second conductivity type connecting the bottom region and the body region with in contact with. In this switching element, the effective second conductivity type impurity concentration of the body region at a position in contact with the gate insulating film covering the lateral side surface of the trench is such that the effective concentration of the second region in the body region at a position away from the gate insulating film. It is characterized by being thinner than the effective second conductivity type impurity concentration.

When a high-concentration second conductivity type impurity (its concentration is d1) and a low-concentration first conductivity type impurity (its concentration is d2) are mixed, the second conductivity-type impurity having a concentration of d1-d2 is present. The characteristics are almost the same as when existing. The effective second conductivity type impurity concentration referred to in this specification refers to a concentration obtained by subtracting a low concentration first conductivity type impurity concentration from a high concentration second conductivity type impurity concentration.
In the case of a switching element manufactured by the technique of Patent Document 1 (the second conductivity type impurity implantation step for forming the bottom region and the connection region is performed, but the first conductivity type impurity implantation step is not performed) The effective second conductivity type impurity concentration of the body region at the contact position becomes higher than the effective second conductivity type impurity concentration of the body region at a position away from the gate insulating film, and the gate threshold value increases.
Patent Document 2 discloses a technique for performing the first conductivity side impurity implantation step, but implanting an amount of the first conductivity type impurity exceeding the second conductivity type impurity concentration of the second conductivity type body region. As a result, the range in contact with the gate insulating film is inverted to the first conductivity type.
The switching element disclosed in this specification is different from Patent Document 2 in that the range in contact with the gate insulating film remains in the second conductivity type even after the first conductive side impurity is implanted, and the switching element is in a position in contact with the gate insulating film. This is different from Patent Document 1 in that the effective second conductivity type impurity concentration of the body region in the body region is thinner than the effective second conductivity type impurity concentration of the body region located away from the gate insulating film. It is a novel switching element that is different from both.

The MOSFET10 top view of an Example. FIG. 2 is a cross-sectional view of MOSFET 10 taken along the line II-II in FIG. 1. FIG. 3 is a longitudinal sectional view of a MOSFET 10 taken along line III-III in FIG. 1. The cross-sectional view of the semiconductor substrate 12 before processing. The cross-sectional view of the semiconductor substrate 12 after forming the trench 22. FIG. 6 is a cross-sectional view of the semiconductor substrate 12 showing a step of forming a bottom region 36 and a connection region 38. FIG. 6 is a longitudinal sectional view of the semiconductor substrate 12 showing a step of forming a bottom region 36 and a connection region 38. The cross-sectional view of the semiconductor substrate 12 which shows the process of inject | pouring an n-type impurity.

  1 to 3 show a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 10 of the embodiment. As shown in FIGS. 2 and 3, the MOSFET 10 includes a semiconductor substrate 12, an electrode, an insulating layer, and the like. In FIG. 1, illustration of electrodes and insulating layers on the upper surface 12 a of the semiconductor substrate 12 is omitted for easy viewing. Hereinafter, when the upper surface 12a is viewed in plan, the direction in which the trench 22 extends long (the y direction in the drawing) may be referred to as the longitudinal direction, and the direction orthogonal to the longitudinal direction (the x direction in the drawing) may be referred to as the short direction. The thickness direction of the semiconductor substrate 12 is referred to as the z direction. The semiconductor substrate 12 is made of SiC.

  A plurality of trenches 22 are provided on the upper surface 12 a of the semiconductor substrate 12. As shown in FIG. 1, each trench 22 extends linearly in the y direction. The plurality of trenches 22 are arranged at intervals in the x direction. As shown in FIG. 2, the side surface 22 a located at the end in the short direction of each trench is inclined so that the width in the x direction of the trench 22 increases from the bottom toward the upper end. FIG. 3 shows a cross-sectional structure of the end portion of the trench 22 in the longitudinal direction. 3 shows one end portion of the trench 22 in the longitudinal direction, the other end portion also has the same cross-sectional structure as FIG. As shown in FIG. 3, the side surface 22b located at the end portion in the longitudinal direction of each trench 22 is also inclined so that the width in the y direction of the trench 22 increases from the bottom portion toward the upper end portion. As shown in FIGS. 2 and 3, the inner surface of each trench 22 is covered with a gate insulating film 24. The gate insulating film 24 has a bottom insulating layer 24a and a side insulating layer 24b. The bottom insulating layer 24 a covers the bottom surface 22 c of the trench 22. The side surface insulating layer 24 b covers the side surfaces 22 a and 22 b of the trench 22. The bottom insulating layer 24a is thicker than the side insulating layer 24b. A gate electrode 26 is disposed in each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of each gate electrode 26 is covered with an interlayer insulating film 28.

  As shown in FIGS. 2 and 3, the upper electrode 70 is disposed on the upper surface 12 a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12 a of the semiconductor substrate 12 at a portion where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is disposed on the lower surface 12 b of the semiconductor substrate 12. The lower electrode 72 is in contact with the lower surface 12 b of the semiconductor substrate 12.

  As shown in FIGS. 1 to 3, a plurality of source regions 30, a body region 32, a drift region 33, a drain region 34, a plurality of bottom regions 36, and a plurality of connection regions 38 are provided inside the semiconductor substrate 12. Yes.

  Each source region 30 is an n-type region. As shown in FIG. 2, each source region 30 is disposed at a position exposed at the upper surface 12 a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the side insulating layer 24 b at the upper end of the trench 22.

  Body region 32 is a p-type region. As shown in FIG. 2, the body region 32 is in contact with each source region 30. The body region 32 has a first portion 32 a and a second portion 32 b when viewed from the longitudinal direction of the trench 22. The first portion 32 a is in contact with the gate insulating film 24 (side insulating layer 24 b) below the source region 30 and on the side surface 22 a in the short direction of the trench 22. The second portion 32b is formed at a position farther from the gate insulating film 24 than the first portion 32a, and is in contact with the first portion 32a. The second portion 32b extends from a range sandwiched between the two source regions 30 to the lower side of each source region. The second portion 32 b is a portion exposed at the upper surface 12 a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 70. As shown in FIG. 3, the body region 32 (second portion 32 b) is also formed at a position in contact with the side surface 22 b in the longitudinal direction of each trench 22. The lower end of the body region 32 is disposed above the lower end of the gate electrode 26. The effective p-type impurity concentration of the first portion 32a is lower than the effective p-type impurity concentration of the second portion 32b. A detailed description of the effective p-type impurity concentration in the body region 32 will be described later.

  The drift region 33 is an n-type region having a low n-type impurity concentration. The drift region 33 is disposed below the body region 32 and is separated from the source region 30 by the body region 32. As shown in FIG. 2, the drift region 33 is in contact with the side insulating layer 24 b below the body region 32.

  The drain region 34 is an n-type region having an n-type impurity concentration higher than that of the drift region 33. The drain region 34 is disposed below the drift region 33. The drain region 34 is exposed on the lower surface 12 b of the semiconductor substrate 12. The drain region 34 is in ohmic contact with the lower electrode 72.

  Each bottom region 36 is a p-type region. Each bottom region 36 is disposed in a range in contact with the bottom surface 22 c of the corresponding trench 22. Each bottom region 36 is in contact with the bottom insulating layer 24 a at the bottom surface 22 c of the corresponding trench 22. As shown in FIG. 3, each bottom region 36 extends long in the y direction along the bottom surface of the corresponding trench 22. Each bottom region 36 is in contact with the bottom insulating layer 24 a over the entire bottom surface of the corresponding trench 22. As shown in FIG. 2, the periphery of each bottom region 36 is surrounded by a drift region 33. In the cross section shown in FIG. 2, each bottom region 36 is separated from the body region 32 by a drift region 33. Each bottom region 36 is separated from each other by a drift region 33.

  Each connection region 38 is a p-type region. As shown in FIGS. 1 and 3, each connection region 38 is provided along the side surface 22 b in the y direction of the corresponding trench 22. As shown in FIG. 3, the lower end of each connection region 38 is connected to the corresponding bottom region 36. The upper end of each connection region 38 is connected to the body region 32. As described above, the body region 32 is connected to the upper electrode 70. Accordingly, each bottom region 36 is connected to the upper electrode 70 via the connection region 38 and the body region 32.

  When the MOSFET 10 is used, the MOSFET 10, a load (for example, a motor), and a power source are connected in series. A power supply voltage is applied to the series circuit of the MOSFET 10 and the load. The power supply voltage is applied in such a direction that the drain (lower electrode 72) of the MOSFET 10 has a higher potential than the source (upper electrode 70).

  When the gate potential of the MOSFET 10 (potential of the gate electrode 26) is controlled to a potential higher than the gate threshold value, the first portion 32a of the body region 32 adjacent to the side surface insulating layer 24b is inverted to n-type and a channel is formed. Is done. Therefore, electrons flow from the upper electrode 70 to the lower electrode 72 through the source region 30, the channel, the drift region 33, and the drain region 34. That is, the MOSFET 10 is turned on, and a current flows from the lower electrode 72 to the upper electrode 70.

  When the gate potential is lowered to a potential lower than the gate threshold, the channel disappears and the MOSFET 10 is turned off. As a result, the potential of the lower electrode 72 rises, and the potentials of the drain region 34 and the drift region 33 rise. Therefore, a reverse potential is applied to the pn junction at the interface between the body region 32 and the drift region 33, and a depletion layer spreads from the body region 32 toward the drift region 33.

  In addition, when the potential of the drift region 33 increases, the potential of the bottom region 36 tends to increase due to capacitive coupling between the drift region 33 and the bottom region 36. However, when the potential of the bottom region 36 increases, holes flow from the bottom region 36 to the upper electrode 70 through the connection region 38 and the body region 32. For this reason, the potential of the bottom region 36 hardly increases and is maintained at a potential close to the potential of the upper electrode 70. Therefore, a reverse voltage is also applied to the pn junction at the interface between the bottom region 36 and the drift region 33, and a depletion layer spreads from the bottom region 36 to the drift region 33.

  Thus, a depletion layer spreads from both the body region 32 and the bottom region 36 to the drift region 33. Since the drift region 33 is depleted, the voltage is held by the drift region 33. Since the depletion layer spreads not only from the body region 32 but also from the bottom region 36 to the drift region 33, the drift region 33 is depleted in a short time. Further, the lower end of each trench 22 is protected by a depletion layer extending from the bottom region 36. For this reason, it is difficult for the electric field to concentrate on the semiconductor region located near the lower end of each trench 22. In particular, in the MOSFET 10 of this embodiment, the bottom region 36 is formed wide so as to contact the entire bottom surface 22 c of the trench 22. For this reason, the electric field concentration of the semiconductor region in the vicinity of the corner portion at the lower end of the trench 22 (that is, the corner portion at the boundary between the bottom surface 22c and the side surface 22a) can be effectively suppressed. Therefore, this MOSFET 10 has a high breakdown voltage.

  When the gate potential is again raised to a potential higher than the gate threshold, a channel is formed in the body region 32 (second portion 32b), and the MOSFET 10 is turned on. For this reason, the potentials of the lower electrode 72, the drain region 34, and the drift region 33 are lowered. At this time, holes are supplied from the upper electrode 70 to the bottom region 36 through the body region 32 and the connection region 38. For this reason, the potential of the bottom region 36 hardly decreases and is maintained at a potential close to the potential of the upper electrode 70. For this reason, as the potential of the drift region 33 decreases, the reverse voltage applied to the pn junction at the interface between the bottom region 36 and the drift region 33 decreases. As a result, the depletion layer extending from the bottom region 36 to the drift region 33 contracts to the bottom region 36 and disappears. As described above, the holes are supplied to the bottom region 36, so that the depletion layer disappears in a short time. Therefore, in this MOSFET 10, the on-resistance decreases in a short time after being turned on. Therefore, the MOSFET 10 can operate with low loss.

  In addition, as described above, the first portion 32a of the body region 32 has an effective p-type impurity concentration that is lower than that of the second portion 32b. For this reason, the first portion 32a has a lower potential for inversion to the n-type than the second portion 32b. The first portion 32a is a range where a channel is formed. That is, the gate threshold value of the MOSFET 10 can be lowered. Further, when a reverse potential is applied to the pn junction at the interface between the body region 32 and the drift region 33, a depletion layer extends from the drift region 33 to the body region 32. Since the effective p-type impurity concentration in the first portion 32a is lower than that in the second portion 32b, the portion is easily depleted. For this reason, the breakdown voltage of the MOSFET 10 can be improved.

  Next, a method for manufacturing MOSFET 10 will be described. First, the semiconductor substrate 12 before the formation of the MOSFET 10 shown in FIG. 4 is prepared. The semiconductor substrate 12 has a drift region 33, a body region 32, and a source region 30. The body region 32 and the source region 30 may be formed by ion implantation, may be formed by epitaxial growth, or may be formed by combining these.

  Next, as shown in FIG. 5, a resist layer 41 having an opening 41 a is formed on the upper surface 12 a of the semiconductor substrate 12. Next, dry etching (for example, reactive ion etching) is performed on the upper surface 12 a of the semiconductor substrate 12 through the resist layer 41. As a result, a trench 22 is formed in the upper surface 12 a of the semiconductor substrate 12. The trench 22 is formed so as to penetrate the source region 30 and the body region 32 and reach the drift region 33.

  Next, as shown in FIGS. 6 and 7, the vertical line V standing on the upper surface 12 a of the semiconductor substrate 12 is formed around the axis extending in the short direction of the trench 22 (x A p-type impurity is implanted from a direction inclined around the axis. As a result, p-type impurities are implanted into the semiconductor region in contact with the bottom surface 22c, and p-type impurities are implanted into the semiconductor region in contact with the side surface 22b in the longitudinal direction. Here, when the impurity is implanted, a tolerance in the implantation direction may occur. Further, the trench 22 may be inclined in a direction in which the width of the upper end portion in the short direction is wider than the width of the bottom surface 22c. For these reasons, the p-type impurity is injected into the bottom surface 22 c of the trench and the side surface 22 b in the longitudinal direction, and is also slightly injected into the side surface 22 a in the short direction of the trench 22. 7 shows the implantation of p-type impurities into one of the side surface 22b in the longitudinal direction of the trench 22 and a part of the bottom surface 22c, but also to the other of the side surface 22b in the longitudinal direction and the other part of the bottom surface 22c. A p-type impurity is implanted as in FIG.

  Next, as shown in FIG. 8, the vertical line V standing on the upper surface 12 a of the semiconductor substrate 12 is inclined on the side surface 22 a in the short direction of the trench 22 around the axis extending in the longitudinal direction of the trench 22 (around the y axis). An n-type impurity is implanted from the formed direction. In this step, by adjusting the inclination angle θ ′, the n-type impurity is not injected into the bottom surface 22c, but is injected into the side surface 22a in the short direction. In this embodiment, an n-type impurity is implanted into the side surface 22 a in a range shallower than the body region 32 using the resist layer 41. In this embodiment, the n-type impurity concentration implanted in this step is higher than the p-type impurity concentration implanted in the short side surface 22a in the step of injecting the p-type impurity into the bottom surface 22c and the longitudinal side surface 22b. On the other hand, it is lighter than the p-type impurity concentration of the body region 32 at the time of FIG. The effective p-type impurity concentration in the range in which the n-type impurity is implanted in the body region 32 is as follows: This concentration is obtained by subtracting the n-type impurity concentration injected into the side surface 22a in this step from the concentration obtained by adding the p-type impurity concentration injected into the side surface 22a. For this reason, the first portion 32a having an effective p-type impurity concentration lower than that of the body region 32 (second portion 32b) is formed. Thereafter, the resist layer 41 is removed.

  When the step of implanting the p-type impurity and the n-type impurity is completed, the implanted impurity is activated by heat treatment. Thereby, the bottom region 36 and the connection region 38 are formed.

  Next, the gate insulating film 24 shown in FIGS. 2 and 3 is formed in the trench 22, and the gate electrode 26 is formed. Next, the interlayer insulating film 28 and the upper electrode 70 are formed on the upper surface 12 a of the semiconductor substrate 12. Next, an n-type impurity is implanted into the lower surface 12 b of the semiconductor substrate 12 to form the drain region 34. Next, the lower electrode 72 is formed on the lower surface 12 b of the semiconductor substrate 12. Through the above steps, the MOSFET 10 shown in FIGS. 1 to 3 is completed.

  In the process of manufacturing the MOSFET 10, as described above, p-type impurities are implanted into the side surface 22 a in the short direction of the trench 22. When p-type impurities are implanted into the semiconductor region near the side surface 22a of the trench 22, especially the body region 32, problems such as an increase in gate threshold and channel resistance occur. However, the manufacturing method of the present embodiment includes a step of injecting n-type impurities into the side surface 22a of the trench 22. Thereby, the effective p-type impurity concentration of the body region 32 into which the p-type impurity is implanted can be reduced. Therefore, these problems can be suppressed.

  In the above-described embodiments, the MOSFET has been described. However, the technology disclosed in this specification may be applied in the manufacturing process of the IGBT. In the embodiment described above, an IGBT can be obtained by forming a p-type collector region instead of the n-type drain region 34.

  Further, the shape of the trench 22 when the semiconductor substrate 12 is viewed in plan is not limited to the shape in the above-described embodiment. For example, it may be a lattice shape or a polygonal shape.

  The step of implanting p-type impurities into the bottom surface 22c and the side surface 22b of the trench 22 and the step of implanting n-type impurities into the side surface 22a of the trench 22 may be performed in any order. Further, the step of injecting the p-type impurity into the bottom surface 22c and the side surface 22b of the trench 22 may be performed separately. In this way, the p-type impurity concentration in the bottom region 36 and the connection region 38 can be adjusted. In the manufacturing method of the above-described embodiment, the semiconductor substrate 12 having the body region 32 is used in advance. However, the body region 32 may be formed after each of the above-described steps.

  Further, in the embodiment, as shown in FIG. 3, the example in which the body region 32 is formed in the semiconductor region in contact with the upper portion of the longitudinal side surface 22b of the trench 22 is described. However, the connection region 38 is formed in the semiconductor region. It may be formed. That is, the connection region 38 may be formed so as to face the upper surface 12 a of the semiconductor substrate 12. Further, the source region 30 may be formed at the upper end portion of the semiconductor region in contact with the side surface 22b in the longitudinal direction of the trench 22.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: MOSFET
12: Semiconductor substrate 22: Trench 22a: Side 22b: Side 22c: Bottom 24: Gate insulating film 24a: Bottom insulating layer 24b: Side insulating layer 26: Gate electrode 28: Interlayer insulating film 30: Source region 32: Body region 32a: First portion 32b: Second portion 33: Drift region 34: Drain region 36: Bottom region 38: Connection region 41: Resist layer 41a: Opening 70: Upper electrode 72: Lower electrode

Claims (2)

A trench provided on the upper surface of the semiconductor substrate;
A gate insulating film covering the inner surface of the trench;
A gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film;
A source region of a first conductivity type in contact with the gate insulating film on a lateral side surface of the trench;
A body region of a second conductivity type in contact with the gate insulating film below the source region on the side surface in the lateral direction;
A drift region of a first conductivity type that is in contact with the gate insulating film below the body region on the side surface in the lateral direction, and is separated from the source region by the body region;
A bottom region of a second conductivity type in contact with the gate insulating film at the bottom of the trench;
A second conductivity type connection region that is in contact with the gate insulating film on the side surface in the longitudinal direction of the trench and connects the bottom region and the body region;
A method for manufacturing a switching element comprising:
Forming the trench;
A second conductivity type impurity is introduced into the bottom surface of the trench and the side surface in the longitudinal direction from a direction in which a perpendicular standing on the top surface of the semiconductor substrate is inclined around an axis extending in the short direction of the trench. Injecting, and
Injecting a first conductivity type impurity into the side surface of the trench in the lateral direction from a direction in which the perpendicular is inclined around an axis extending in the longitudinal direction of the trench;
A manufacturing method comprising: A trench provided on the upper surface of the semiconductor substrate;
A gate insulating film covering the inner surface of the trench;
A gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film;
A source region of a first conductivity type in contact with the gate insulating film on a lateral side surface of the trench;
A body region of a second conductivity type in contact with the gate insulating film below the source region on the side surface in the lateral direction;
A drift region of a first conductivity type that is in contact with the gate insulating film below the body region on the side surface in the lateral direction, and is separated from the source region by the body region;
A bottom region of a second conductivity type in contact with the gate insulating film at the bottom of the trench;
A second conductivity type connection region that is in contact with the gate insulating film on the side surface in the longitudinal direction of the trench and connects the bottom region and the body region;
With
The effective second conductivity type impurity concentration of the body region at a position in contact with the gate insulating film covering the lateral side surface of the trench in the lateral direction is effective in the body region at a position separated from the gate insulating film. The second conductivity type impurity concentration is lower than the target concentration,
Switching element.

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