JP2020077736A - Method for manufacturing semiconductor device - Google Patents

Abstract

To provide a technology for forming a bottom p-type layer from a bottom face of a trench gate to a deep position.SOLUTION: A method for manufacturing a semiconductor device provided with a bottom p-type layer brought into contact with a bottom face of a trench gate includes a trench formation step for forming a trench on one principal plane of a silicon carbide semiconductor substrate with only by an off angle inclined with respect to a basal plane, and a bottom p-type layer formation step for irradiating p-type impurity toward the inside of the trench to form the bottom p-type layer. In the bottom p-type layer formation step, an implantation angle of the p-type impurity is set to the off angle such that the p-type impurity is implanted to the basal plane from a vertical direction.SELECTED DRAWING: Figure 2

Description

  The technique disclosed in this specification relates to a method for manufacturing a semiconductor device.

  Development of a semiconductor device manufactured using a silicon carbide semiconductor substrate is in progress. In this type of semiconductor device, a plurality of trench gates are formed on one main surface of a semiconductor substrate. The trench gate is formed so as to penetrate the p-type body region and enter the n-type drift region. Patent Document 1 discloses a technique of providing a bottom p-type layer so as to be in contact with the bottom surface of the trench gate in order to relax the electric field at the bottom surface of the trench gate.

JP, 2017-117951, A

  In order to relax the electric field on the bottom surface of the trench gate well, it is desirable that such a bottom p-type layer is formed deep from the bottom surface of the trench gate. The present specification aims to provide a technique of forming a bottom p-type layer from a bottom surface of a trench gate to a deep position.

  The present specification discloses a method for manufacturing a semiconductor device including a bottom p-type layer in contact with a bottom surface of a trench gate. This manufacturing method comprises a trench forming step of forming a trench on one main surface of a silicon carbide semiconductor substrate inclined by an off-angle with respect to a basal plane, and irradiating a p-type impurity into the trench to form the bottom. a bottom p-type layer forming step of forming a p-type layer. In the bottom p-type layer forming step, the implantation angle of the p-type impurities is set to the off-angle so that the p-type impurities are implanted in a direction perpendicular to the base surface. According to this manufacturing method, the p-type impurity can be implanted from the bottom surface of the trench to a deep position due to the channeling effect. According to this manufacturing method, the bottom p-type layer can be formed deep from the bottom surface of the trench gate.

  According to one embodiment of the above-mentioned manufacturing method, in the bottom p-type layer forming step, the p-type impurity is implanted also into one lateral side of the pair of lateral sides facing each other in the lateral direction of the trench. Thus, the bottom p-type layer may be formed so as to be connected to the p-type body region provided on the one main surface side of the semiconductor substrate. According to this manufacturing method, a connection region for connecting the bottom p-type layer to the body region can be simultaneously formed. Therefore, the number of steps required to manufacture the connection region can be reduced, and the manufacturing cost can be suppressed. Further, the bottom p-type layers formed on the lateral side surfaces may be dispersed and arranged along the longitudinal direction of the trench. By arranging the bottom p-type layers formed on the short side surfaces in a dispersed manner, an increase in channel resistance can be suppressed.

  According to another embodiment of the above manufacturing method, in the bottom p-type layer forming step, the p-type impurity is implanted into one of the pair of long side surfaces facing each other in the longitudinal direction of the trench. Accordingly, the bottom p-type layer may be formed so as to be connected to the p-type body region provided on the one main surface side of the semiconductor substrate. According to this manufacturing method, a connection region for connecting the bottom p-type layer to the body region can be simultaneously formed. Therefore, the number of steps required to manufacture the connection region can be reduced, and the manufacturing cost can be suppressed.

FIG. 3 is a plan view of the semiconductor device according to the first embodiment viewed from the upper surface side. FIG. 2 is a sectional view of the semiconductor device taken along line II-II of FIG. 1. Sectional drawing of the semiconductor device in the III-III line of FIG. Sectional drawing in one manufacturing process which forms the bottom p-type layer of the semiconductor device of 1st Embodiment. Sectional drawing in one manufacturing process which forms the bottom p-type layer of the semiconductor device of 1st Embodiment. Sectional drawing in one manufacturing process which forms the bottom p-type layer of the semiconductor device of 1st Embodiment. The top view of the semiconductor device of a 2nd embodiment seen from the upper surface side. Sectional drawing of the semiconductor device in the VIII-VIII line of FIG. The top view seen from the upper surface side of the semiconductor device of a 3rd embodiment. Sectional drawing of the semiconductor device in the XX line of FIG. Sectional drawing of the semiconductor device in the XI-XI line of FIG.

(First Embodiment) A semiconductor device 1 of the first embodiment shown in FIGS. 1 to 3 is a semiconductor device of a type called MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device 1 is manufactured using a semiconductor substrate 12 made of silicon carbide (SiC). Note that, in FIG. 1, the electrodes and the insulating layer on the upper surface 12 a of the semiconductor substrate 12 are not shown for the sake of clarity. The semiconductor substrate 12 is a silicon carbide substrate having a (0001) plane as a basal plane, and is inclined by an off angle in the [11-20] direction with respect to the (0001) plane. In this example, the off angle is about 4 °.

  A plurality of trenches TR are formed on the upper surface 12a of the semiconductor substrate 12, and a trench gate 22 is provided in each trench TR. As shown in FIG. 1, the trench gate 22 extends linearly in the [1-100] direction on the upper surface 12a. The plurality of trench gates 22 are arranged at intervals in the [11-20] direction and have a striped layout. As shown in FIG. 2, the trench TR extends in the direction perpendicular to the upper surface 12 a of the semiconductor substrate 12. The side surface of the trench TR is inclined along the depth direction of the semiconductor substrate 12, and is tapered toward the deep portion of the semiconductor substrate 12. The bottom surface of the trench TR is parallel to the top surface 12a of the semiconductor substrate 12.

  The side surface and the bottom surface of the trench TR are covered with the gate insulating film 24. The gate insulating film 24 may be formed thicker on the bottom surface than the side surface of the trench TR. The gate electrode 26 is arranged in the trench TR. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of the gate electrode 26 is covered with an interlayer insulating film 28.

  The source electrode 70 is arranged on the upper surface 12 a of the semiconductor substrate 12. The source electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 at the portion where the interlayer insulating film 28 is not provided. The source electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A drain electrode 72 is arranged on the lower surface 12b of the semiconductor substrate 12. The drain electrode 72 is in contact with the lower surface 12b of the semiconductor substrate 12.

  Inside the semiconductor substrate 12, a plurality of source regions 30, a body region 32, a drift region 34, a drain region 35 and a plurality of bottom p-type layers 36 are provided.

  The source region 30 is an n-type region. The source region 30 is arranged in a range facing the upper surface 12 a of the semiconductor substrate 12, and is in ohmic contact with the source electrode 70. The source region 30 is in contact with the gate insulating film 24 at a pair of short side surfaces S1 (side surfaces extending along the [1-100] direction) that face each other in the short direction of the trench gate 22. The source region 30 is in contact with the gate insulating film 24 at the upper end of the trench gate 22.

  The body region 32 is a p-type region. The body region 32 is in contact with each source region 30. The body region 32 extends from the area sandwiched between the two source regions 30 to the lower side of each source region 30. The body region 32 has a high concentration body region 32a and a low concentration body region 32b. The high-concentration body region 32a has a higher p-type impurity concentration than the low-concentration body region 32b. The high-concentration body region 32a is arranged in the range sandwiched by the two source regions 30. The high concentration body region 32 a is in ohmic contact with the source electrode 70. The low concentration body region 32b is in contact with the gate insulating film 24 on the lateral side surface of the trench gate 22. The low-concentration body region 32b is in contact with the gate insulating film 24 below the source region 30. Further, as shown in FIG. 1, the low-concentration body region 32b is a pair of long side surfaces S2 facing each other in the longitudinal direction of the trench gate 22 (side surfaces located at end portions in the longitudinal direction of the trench gate 22, [11- 20] is also arranged in a range adjacent to the side surface extending along the direction).

  The drift region 34 is an n-type region. The drift region 34 is arranged below the body region 32, and is separated from the source region 30 by the body region 32. As shown in FIG. 2, the drift region 34 is in contact with the gate insulating film 24 on one short side surface of the pair of short side surfaces of the trench gate 22.

  The drain region 35 is an n-type region. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 is arranged below the drift region 34. The drain region 35 is arranged in a range facing the lower surface 12b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the drain electrode 72.

  The bottom p-type layer 36 is a p-type region. The bottom p-type layer 36 is in contact with the gate insulating film 24 on the bottom surface of the trench gate 22. The bottom p-type layer 36 extends in the [1-100] direction along the bottom surface of the trench gate 22. Further, a part of the bottom p-type layer 36 is in contact with the gate insulating film 24 on one short side surface of the pair of short side surfaces of the trench gate 22. Here, a portion of the bottom p-type layer 36 that contacts the side surface of the trench gate 22 is particularly referred to as a connection region 36a. The connection region 36a of the bottom p-type layer 36 extends in the [1-100] direction along one short side surface S1 of the trench gate 22. The bottom p-type layer 36 is in contact with the body region 32 via the connection region 36a and is electrically connected to the body region 32.

  Next, the operation of the semiconductor device 1 will be described. When using the semiconductor device 1, the semiconductor device 1, a load (for example, a motor), and a power supply are connected in series. A power supply voltage (about 800 V in this embodiment) is applied to the series circuit of the semiconductor device 1 and the load. The power supply voltage is applied so that the drain side (drain electrode 72) of the semiconductor device 1 has a higher potential than the source side (source electrode 70). When a gate-on potential (potential higher than the gate threshold) is applied to the gate electrode 26, a channel (inversion layer) is formed in the body region 32 (low-concentration body region 32b) in a range in contact with the gate insulating film 24, and the semiconductor device 1 Turn on. In the semiconductor device 1, a current flows through the channel formed in the body region 32 on the short side surface S1 of the pair of short side surfaces S1 of the trench gate 22 that is in contact with the drift region 34. When a gate-off potential (potential equal to or lower than the gate threshold) is applied to the gate electrode 26, the channel disappears and the semiconductor device 1 turns off. At this time, a depletion layer extending from the pn junction between the drift region 34 and the bottom p-type layer 36 is formed near the bottom surface of the trench gate 22, and the electric field near the bottom surface of the trench gate 22 is relaxed. As a result, the semiconductor device 1 can have high withstand voltage characteristics. Further, in the semiconductor device 1, since the bottom p-type layer 36 is electrically connected to the body region 32 via the connection region 36a, the bottom p-type layer 36 is turned on from the body region 32 via the connection region 36a. Holes are injected into the mold layer 36. This hole injection suppresses the charging of the bottom p-type layer 36, so that the depletion layer formed at the time of turn-off disappears immediately, and the increase in on-resistance due to the JFET effect is suppressed.

  Next, the step of forming the bottom p-type layer 36 in the method for manufacturing the semiconductor device 1 will be described with reference to FIGS. First, as shown in FIG. 4, a silicon oxide mask 82 is formed on the upper surface 12 a of the semiconductor substrate 12. Next, using dry etching technology, the semiconductor substrate 12 exposed from the opening of the mask 82 is etched to form a trench TR. The bottom surface of the trench TR is parallel to the upper surface 12a of the semiconductor substrate 12, and like the upper surface 12a, is inclined by the off angle in the [11-20] direction with respect to the (0001) plane of the base surface.

  Next, as shown in FIG. 5, a protective film 84 of silicon oxide is formed on the bottom surface and the side surface of the trench TR. The protective film 84 is formed for the purpose of suppressing unintended impurities from being introduced into the low-concentration body region 32b on the side where the channel is formed in the ion implantation process described later. If necessary, only the portion of the protective film 84 that covers the bottom surface of the trench TR may be removed.

  Next, as shown in FIG. 6, the bottom p-type layer 36 is formed by irradiating the trench TR with p-type impurities using the ion implantation technique. At this time, the implantation angle of the p-type impurity is set to the off angle so as to be perpendicular to the (0001) plane of the basal plane. In this example, since the semiconductor substrate 12 is tilted with respect to the (0001) plane in the [11-20] direction by the off angle, the implantation angle of the p-type impurity is the vertical direction of the upper surface 12a of the semiconductor substrate 12. It is inclined by the off angle in the [11-20] direction. When the implantation angle of p-type impurities is set to the off-angle, the irradiated p-type impurities can reach a deep position from the bottom surface of trench TR by the channeling effect. Thereby, the bottom p-type layer 36 is formed from the bottom surface of the trench TR to a deep position. Further, in this ion implantation step, the p-type impurity is also implanted into one short side surface S1 of the pair of short side surfaces S1 facing in the short side direction of the trench TR, whereby the bottom p-type layer 36 is formed. The connection area 36a is also formed at the same time.

The above manufacturing method and the semiconductor device 1 manufactured by the above manufacturing method can have the following features.
(1) According to the above manufacturing method, the bottom p-type layer 36 can be formed from the bottom surface of the trench gate 22 to a deep position. Such a deep bottom p-type layer 36 can satisfactorily relax the electric field at the bottom surface of the trench gate 22. Therefore, the semiconductor device 1 can have high withstand voltage characteristics.
(2) In ion implantation that does not utilize the channeling effect, a plurality of ion implantations are required to form the deep bottom p-type layer 36. On the other hand, in the ion implantation utilizing the channeling effect as in the above-described manufacturing method, the deep bottom p-type layer 36 can be formed with a small number of ion implantations (for example, even one ion implantation). Therefore, the number of steps required for ion implantation is reduced, so that the manufacturing cost can be suppressed.
(3) According to the manufacturing method described above, since the deep bottom p-type layer 36 can be formed, it is not necessary to thermally diffuse the bottom p-type layer 36 to a deep position, and thermal diffusion can be suppressed. Therefore, heat diffusion in the lateral direction of the bottom p-type layer 36 is also suppressed. Since the heat diffusion in the lateral direction is suppressed, in particular, in the semiconductor device 1, the bottom p is formed with respect to the current path below the short side surface S1 of the trench gate 22 on the side where the channel is formed. The mold layer 36 is formed at a remote position. Therefore, the increase in JFET resistance due to the depletion layer extending from the bottom p-type layer 36 is suppressed.
(4) According to the above manufacturing method, the irradiated p-type impurities pass through the interstitial spaces due to the channeling effect. Therefore, it is possible to form the high-concentration bottom p-type layer 36 while suppressing the crystal defect density. Since the crystal defect density can be suppressed, the drain-source leak can be suppressed. Further, the high-concentration bottom p-type layer 36 can favorably relax the electric field at the bottom surface of the trench gate 22.
(5) According to the above manufacturing method, the connection region 36a that connects the bottom p-type layer 36 to the body region 32 can be simultaneously formed. Therefore, the number of steps required to form the connection region 36a can be reduced, so that the manufacturing cost can be suppressed.

(Second Embodiment) FIGS. 7 and 8 show a semiconductor device 2 according to a second embodiment. The same components as those of the semiconductor device 1 of the first embodiment are designated by the same reference numerals and the description thereof will be omitted. The semiconductor device 2 is characterized in that the bottom p-type layers 136 are arranged in a distributed manner along the longitudinal direction ([1-100] direction) of the trench gate 22. As a result, the connection regions of the bottom p-type layer 136 (portions formed in contact with one short side surface S1 of the trench gate 22) are also dispersed along the longitudinal direction of the trench gate 22. .. As a result, as compared with the semiconductor device 1 of the first embodiment, the semiconductor device 2 has a large area of the channel formed on the short side surface S1 of the trench gate 22, and thus can have a characteristic of low channel resistance. ..

  In the semiconductor device 2, prior to irradiating the trench TR with p-type impurities to form the bottom p-type layer 136, a resist having a pattern dispersed along the longitudinal direction is formed and placed in the trench TR. It can be manufactured by

(Third Embodiment) FIGS. 9 to 11 show a semiconductor device 3 according to a third embodiment. The same components as those of the semiconductor device 1 of the first embodiment are designated by the same reference numerals and the description thereof will be omitted. In the semiconductor device 3, the off direction of the semiconductor substrate 12 is different from that in the semiconductor device 1. In the semiconductor device 3, the semiconductor substrate 12 is tilted by the off angle in the [1-100] direction with respect to the (0001) plane of the base surface. In this example, the off angle is about 4 °. Further, as shown in FIG. 11, the connection region 236a of the bottom p-type layer 236 is in contact with the gate insulating film 24 on one longitudinal side surface S2 of the pair of longitudinal side surfaces S2 opposed to each other in the longitudinal direction of the trench gate 22. ing. The bottom p-type layer 236 is in contact with the body region 32 via the connection region 236a and is electrically connected to the body region 32. Since the semiconductor device 3 has a channel formed on the entire side surface of the trench gate 22, it has a characteristic of low channel resistance as compared with the semiconductor device 1 of the first embodiment and the semiconductor device 2 of the second embodiment. You can

  In the semiconductor device 3, when the semiconductor device 2 forms the bottom p-type layer 36 by irradiating the trench TR with p-type impurities, the implantation angle of the p-type impurities is the (0001) plane of the base surface. The off-angle is set to be perpendicular to it. In this example, since the semiconductor substrate 12 is tilted with respect to the (0001) plane in the [1-100] direction by the off angle, the implantation angle of the p-type impurity is relative to the vertical direction of the upper surface 12a of the semiconductor substrate 12. It is tilted by the off angle in the [1-100] direction. If the implantation angle of the p-type impurity is set to the off-angle, the p-type impurity can be implanted from the bottom surface of the trench TR to a deep position due to the channeling effect. Thereby, the bottom p-type layer 36 is formed from the bottom surface of the trench TR to a deep position. Further, in this ion implantation step, the p-type impurity is also implanted into one longitudinal side surface S2 of the pair of longitudinal side surfaces S2 facing each other in the longitudinal direction of the trench TR, whereby the connection region 236a of the bottom p-type layer 236 is formed. Are also formed at the same time.

  Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exert technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Further, the technique illustrated in the present specification or the drawings achieves a plurality of purposes at the same time, and achieving one of the purposes has technical utility.

1, 2 and 3: semiconductor device 12: semiconductor substrate 22: trench gate 24: gate insulating film 26: gate electrode 28: interlayer insulating film 30: source region 32: body region 34: drift region 35: drain region 36: bottom p Mold layer 36a: Connection region 70: Source electrode 72: Drain electrode S1: Short side surface S2: Long side surface TR: Trench

Claims (4)

A method of manufacturing a semiconductor device comprising a bottom p-type layer in contact with a bottom surface of a trench gate, comprising:
A trench forming step of forming a trench on one main surface of the semiconductor substrate of silicon carbide inclined by an off-angle with respect to the base surface;
A bottom p-type layer forming step of irradiating a p-type impurity toward the inside of the trench to form the bottom p-type layer,
In the bottom p-type layer formation step, a p-type impurity implantation angle is set to the off-angle so that the p-type impurity is implanted in a direction perpendicular to the base surface. Method.   In the bottom p-type layer forming step, the p-type impurity is implanted also into one short side surface of the pair of short side surfaces facing each other in the short side direction of the trench, whereby the bottom p-type layer is formed. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed so as to be connected to a p-type body region provided on the one main surface side of the semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 2, wherein the bottom p-type layers formed on the lateral side surfaces are dispersedly arranged along the longitudinal direction of the trench.   In the bottom p-type layer forming step, the p-type impurity is also implanted into one of the pair of long side surfaces facing each other in the longitudinal direction of the trench, so that the bottom p-type layer is formed on the semiconductor substrate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed so as to be connected to a p-type body region provided on the one main surface side of.

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