JPH07211714A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the over-etching of an insulating layer on circuit elements as well as the contact and electric leakage between wirings while sufficiently securing the thickness of the insulating layer in order to flatten the surface by etching back step. CONSTITUTION:The first spin-coated layer 5 in the first etching rate similar to that of an insulating layer 4 and the second spin-coated layer 6 in the second etching rate lower than the former etching rate are laminatedly formed on the insulating layer 4 covering the circuit elements 3 on a semiconductor substrate 1 so as to be etched back later. Through these procedures, the surface of the layer flattened by the spin-coated layers further flattened by the etching back step thereby making possible the semiconductor device having the flattened insulating layer in sufficient thickness.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as an IC or an LSI device, and particularly to flatten the surface irregularities of an insulating layer formed to cover a circuit element on a semiconductor substrate. It is about the method.

[0002]

2. Description of the Related Art A semiconductor device is manufactured by selectively forming various layers (films) such as a uniform insulating layer and a wiring layer on the surface of a silicon substrate 1 which constitutes an electronic circuit.

However, since such a wiring layer has a predetermined thickness, irregularities are formed in the insulating layer and the like formed thereon. If the unevenness is significant, it causes troubles such as pattern formation of a layer formed over the insulating layer or the like, disconnection of wiring of a wiring layer, and the like, which leads to a reduction in yield of semiconductor devices. Invite. Therefore, it is necessary to reduce this unevenness as much as possible and flatten it.

As a conventional flattening technique therefor, there is a method of forming a SOG (Spin-on-Glass) film which is an insulating film by spin-coating a fluid material. Figure 3
A method of manufacturing a semiconductor device using this conventional technique is shown in FIG.

FIG. 3A is a sectional view of a semiconductor device having an SOG film formed thereon. In the figure, 1 is a semiconductor substrate such as silicon on which an electronic circuit is formed, 2 is a base insulating film such as SiO ₂ formed on the semiconductor substrate 1, and 3 is formed on the base insulating film 2 and is made of silicon. Alternatively, a circuit element 4 such as a memory cell or a wiring layer formed of metal or the like is formed on the base insulating film 2 and the circuit element 3, and SiO ₂ which insulates the elements and wirings forming the electronic circuit from each other.
Insulating layers 5, which are CVD (Chemical Vapor Deposition) oxide films, are SOG (coated glass) films that flatten the surface irregularities of the insulating layer 4 caused by the formation of the circuit element 3.

In FIG. 3B, etch back is performed from the uneven surface of the SOG film 5 to the alternate long and short dash line P in FIG.
FIG. 6 is a cross-sectional view of a semiconductor device in which a part of the insulating layer 4 is removed together with the OG film 5 to flatten the insulating layer 4. Etchback is one of the flattening techniques, in which an uneven insulating layer formed on a wiring layer is further overlaid with SOG or photoresist to make the surface flat, and then the surface is made uniform by etching. By removing at the depth, the insulating layer is flattened. In the semiconductor device whose surface is thus flattened, the circuit element 7 such as the second wiring layer is then formed on the surface of the insulating layer 4 as shown in FIG. 3C.

Next, a conventional method of manufacturing a semiconductor device will be described by taking a memory cell as an example. First, FIG.
In order to obtain the structure of (a), the base insulating layer 2 of the semiconductor substrate 1
A layer of silicon, metal, or the like is formed thereon, and a predetermined pattern is formed by a photolithography technique to form a circuit element 3 such as a predetermined wiring layer. Then, a silicon oxide film which is the insulating layer 4 is formed on the circuit element 3 by the CVD method or the like. In this state, the insulating layer 4 becomes a surface having irregularities (protrusions) corresponding to the pattern of the circuit element 3 due to the thickness of the circuit element 3 in the lower layer.

Then, an organic SOG film 5 which is a coating insulating film is formed on the CVD oxide film 4. The SOG film is a general term for a flattening film formed by spin coating a solution of a silicon compound dissolved in an organic solvent and baking the solution. Since the SOG film 5 has a flattening ability that, when spin-coated, it deeply accumulates in the recesses and remains only slightly on the projections, so when the SOG material is spin-coated, the SOG film 5 is thick on the recesses 21 on the substrate and on the projections 22. A thin film is formed so as to reduce the step. Therefore, the unevenness due to the circuit element 3 can be reduced, and the uneven surface can be made flat. FIG. 3A is a sectional view of the semiconductor device thus formed.

However, since the etching rate of the wet etching of the SOG film 5 (etching performed in a liquid phase) is very high, if the manufacturing process of the semiconductor device is advanced with the SOG film 5 left, the SOG film 5 will be changed to another one. Various problems occur such that the wiring is eroded more than the portion and is depressed, and the wiring of the wiring layer, which is a circuit element to be formed later, is broken. So SO
The G film 5 is removed by dry etching using active plasma or the like under reduced pressure (etch back). Here, SOG film 5
Is a so-called sacrificial layer.

Etchback is performed on the entire surface including the insulating layer 4 which is a CVD oxide film. That is, the SOG film 5, which is a flattening film, and the CVD film 4 are combined and completely etched to flatten the surface of the semiconductor wafer. As a result, as described above, the CVD oxide film 4 is left, while the unevenness caused by the pattern of the circuit element 3 can be reduced, and the entire surface is etched back so that the cross section of the semiconductor device is as shown in FIG. become.

[0011]

In the conventional method of manufacturing a semiconductor device, the SOG film 5 is formed in a portion where the circuit elements 3 are close to each other, such as the central portion of the memory cell.
Is thick and relatively flat. For example, portions 21 and 22 in FIG. 3A are flat. On the other hand, in the portion where the distance between the circuit elements 3 is wide, such as the end portion of the memory cell, the SOG film 5 is deposited according to the thickness of the wiring, and the step cannot be completely eliminated. It becomes like the part shown by 23. Therefore, the total film thickness t of the CVD oxide film 4 and the SOG film 5 at the end 23 of the memory cell is combined.
₁ becomes thinner than the film thickness t ₂ of the memory cell central portions 21 and 22 (t ₁ <t ₂ ).

As described above, the SOG film 5 is effective in embedding a step difference, but in a place where the step difference is significant, such as the memory cell end portion 23, a single coating provides a sufficient film thickness to eliminate the step difference. I can't.

Therefore, by etching back until the SOG film 5 in the central portion 21 of the memory cell is completely removed, the etching is continued at the end 23 of the memory cell even after the SOG film 5 is removed, and the CVD oxidation is performed. The film 4 is also removed. Therefore, the film thickness t ₃ at the memory cell end portion 23 becomes smaller than the film thickness t ₄ of the CVD oxide film 4 at the memory cell center portion 21 (A portion in FIG. 3B). Then, as shown in FIG. 3 (c), the wiring layer 7 is overlaid on the CVD oxide film 4.
Is formed, the thickness t ₅ of the insulating layer (the CVD oxide film 4) between the wiring layer 7 and the circuit element 3 below the wiring layer 7 becomes thin in the portion A in FIG. Part), the circuit element and the wiring or the like are in contact with each other, or there is a problem that an electrical leak occurs between them.

In order to solve the above problems, the present invention provides
An object of the present invention is to provide a method of manufacturing a semiconductor device which can be sufficiently flattened and can reduce the reduction in the film thickness of the insulating layer 4 such as the CVD oxide film at the memory cell end 23 at the time of etch back.

[0015]

According to a method of manufacturing a semiconductor device of the present invention, a circuit element is formed on a semiconductor substrate, an insulating layer covering the circuit element is formed on the semiconductor substrate, and a circuit is formed. A first spin coating layer having a first etching rate equal to the etching rate of the insulating layer is formed on the uneven surface of the insulating layer covering the device, and the first etching is performed on the first spin coating layer. A second spin coat layer having a second etch rate less than the rate is formed and the first and second spin coat layers are etched back.

According to the method of manufacturing a semiconductor device of the second aspect of the present invention, the first spin coating layer and the second spin coating layer are formed of different coating materials.

According to the semiconductor device manufacturing method of the third aspect of the present invention, the first spin coating layer and the second spin coating layer are formed of the same coating material.

According to the semiconductor device manufacturing method of the fourth aspect of the present invention, the first spin coating layer and the second spin coating layer are formed using different or the same coating material under different firing conditions.

[0019]

According to the invention of claim 1, flattening is promoted at the time of etch back and the insulating layer is promoted due to the difference in etching rate between the first spin coating layer and the second spin coating layer. The thickness of can be secured.

In the invention of claim 2, since the first spin coating layer and the second spin coating layer are different coating materials, the etching rate can be changed even under the same etching conditions. , Easy to manufacture.

In the third aspect of the invention, the first spin coating layer and the second spin coating layer are formed of the same coating material, so that the coating step is simplified.

In the invention of claim 4, since the first spin coating layer and the second spin coating layer are formed by using different or the same coating material under different firing conditions, the coating process is simplified. The etching rate can be finely adjusted.

[0023]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a partial cross-sectional view of a semiconductor device showing a method for manufacturing the semiconductor device of this embodiment. In Figure 1 (a),
On the semiconductor substrate 1 made of silicon or the like on which the electronic circuit is formed, an element that constitutes the electronic circuit and an S that mutually insulates the wiring are formed.
A base insulating film ₂ such as iO ₂ is formed. A circuit element 3 such as a memory cell or a wiring layer formed of silicon or metal or the like and having a predetermined thickness is formed on the underlying insulating film 2, and the circuit element 3 is further insulated from each other. An insulating layer 4 which is a CVD oxide film such as SiO ₂ is formed. As is apparent from the drawing, on the surface of the insulating layer 4 on the circuit element 3, in a portion where the distance between the circuit elements 3 is relatively small, a concave portion 11 is formed corresponding to the height of the circuit element 3,
A flat surface 14 is formed at a portion where the convex portion 12 is formed and the circuit element 3 has a wide interval and a low height, and the convex portion and the flat surface 14 are formed.
An inclined surface portion 13 is formed between them.

Next, the insulating layer 4 thus formed
As shown in Fig. 1 (b), the SOG (Spin-O
The first spin coating layer 5 which is an organic or inorganic SOG film formed by spin coating called n-Glass) is formed by spin coating. This first spin coating layer 5 is for filling the unevenness of the insulating layer 4 and reducing the step difference, and the spin coating is performed at an appropriate number of rotations to obtain a desired film thickness. The etching rate of the first spin coating layer 5 is substantially equal to the etching rate of the insulating layer 4 which is a CVD oxide film. After spin coating, baking is performed with a hot plate in the coating device. However, as is apparent from FIG. 1B, the thickness of the spin coating layer 5 deposited on the inclined surface portion 13 of the circuit element 3 such as the memory cell formed by the wiring is only the first spin coating layer 5 as shown in FIG. Not sufficient as shown in part B of b),
Satisfactory surface flatness cannot be obtained.

Next, a second spin coating layer 6 is formed on the first spin coating layer 5 by spin coating a coating solution having an etching rate smaller than that of the first SOG film and baking it. S
As shown in FIG. 1 (c), the OG film has a property of not thickening on the convex portion but thickening on the concave-convex portion or the concave portion, so that it is attached so as to fill the flat surface 14 including the inclined surface portion 13 of the circuit element 3. Then
A sufficient film thickness can be obtained even on the inclined surface portion 13. Thus, when the first spin coating layer 5 and the second spin coating layer 6 are formed, the surface of the semiconductor device becomes sufficiently flat. The material of the spin coating layer is carbon C such as organic component CH _3.
Since the etching rate becomes slower as the content of C increases, the etching rate of the spin coating layer formed by adjusting the content of carbon C in the coating material can be adjusted. In this embodiment, the first spin coating layer 5 is-
CH ₃ : -OH = 1: 1.8 to 2.2 is a coating material, and the second spin coating layer 6 has -CH ₃ : -OH = 1 :.
The coating material has a ratio of 0.8 to 1.2.

Next, dry etching using a mixed gas of CHF3 / CF4 / Ar is performed to etch back from the surface of the second spin coating layer 6 of FIG. 1 (c). Eventually, FIG. 2 (d) will be obtained. As shown, the second spin coating layer 6 is completely removed on the uneven portions 11 and 12 of the semiconductor substrate to form the surface of the second spin coating layer 5, and the inclined portion 13 and the flat surface portion 14 have the first surface. The state where the spin coating layer 6 of No. 2 remains is reached. The etchback from this state is because the etching rate of the first spin coating layer 5 is higher than the etching rate of the second spin coating layer 6, so that the first spin coating layer 5 ( The etchback of the uneven portions 11 and 12 advances faster than the etchback of the second spin coating layer 6 (the inclined portion 13 and the flat portion 14).

Therefore, as shown in FIG. 2 (e), the second
The spin coating layer 6 is completely removed, and the insulating layer 4 of the CVD oxide film is exposed from the remaining first spin coating layer 5. In this figure, the thicknesses of the first rotary coating layer 5 which is etched back during the period from the state shown by the solid line shown in FIG. 2 (d) to the state shown in FIG. 2 (e) at t _13, the second rotation The thickness of the coating layer 6 is indicated by t ₁₄ .

The layer is further etched back from the state shown in FIG. 2 (e). At this time, since the etching rate of the first spin coating layer 5 and the etching rate of the insulating layer 4 are substantially equal to each other, the respective layers are substantially equal to each other. It is etched by an equal thickness t ₁₅ and t _16, resulting in a very flat state as shown in FIG. In this state, the thickness of the insulating layer 4 covering the circuit element 3 such as the memory cell is not sufficient in the conventional technique (see FIG. 3).
In contrast to (a) of (b)), a sufficient thickness of the insulating layer 4 can be obtained even at the end 13 of the circuit element 3 as shown by C in the figure, and its surface becomes flat, It is possible to completely form the wiring layer and the like thereon.

As described above, the first etching rate is different.
Since the two layers of the spin coating layer 5 and the second spin coating layer 6 are formed and etched back at different etching rates, the film thickness of the insulating layer 4 at the end portion 13 of the circuit element 3 becomes excessive. It is possible to prevent a decrease in the number of contacts, and it is possible to prevent problems such as contact between the wiring layer formed on the insulating layer 4 and the circuit element 3 or electrical leakage.

Example 2. In the embodiment described above, the first spin coating layer 5 and the second spin coating layer 6 having different etching rates were formed by using different coating materials, but whether the coating materials are the same or not. Regardless, the firing conditions may be different to form the first spin coating layer 5 and the second spin coating layer 6 having different etching rates.

In the organic SOG film, when the firing temperature (hot plate temperature) is low, the carbon C in the film remains without being decomposed, so that etching is difficult.
The etching rate of the fired spin coating layer is low, and when the firing temperature is high, the decomposition of carbon C proceeds, so the etching rate increases. Therefore, even if the same coating material is used, the spin coating layers having different etching rates can be obtained by adjusting the firing temperature, and the first spin coating layer 5 can be obtained.
It is possible to easily make the etching rate of 2) higher than the etching rate of the second spin coating layer 6.

On the contrary, in the case of an inorganic SOG film, when the baking temperature is low, the SOG film contains a large amount of water, so that the SOG film is easily etched and the etching rate is high. Complete oxide film (SiO ₂ ) with increasing firing temperature
And the etching rate decreases.

Therefore, the first spin coating layer 5 and the second spin coating layer 5 can be formed by adjusting the firing conditions regardless of the properties of the coating material.
The etching rate of the spin coating layer 6 can be adjusted. Accordingly, in the method of manufacturing the semiconductor device according to the first embodiment,
In the step of forming the first spin coating layer 5 and the second spin coating layer 6, for example, the spin first SO using the same coating material.
The etching rate of the G film 8 should be the same as that of the CVD film 4, and the etching rate of the second SOG film 9 should be smaller than that of the first SOG film 8. You can Further, the etching rate can be finely adjusted by appropriately combining the selection of the coating material and the selection of the firing conditions.

In the above embodiment, the case of the two-layer wiring has been described, but it goes without saying that the insulating layer can be flattened even in the case of the multi-layer wiring having three or more layers.

[0035]

According to the present invention, the circuit element is formed on the semiconductor substrate, the insulating layer covering the circuit element is formed on the semiconductor substrate, and the unevenness of the insulating layer formed by covering the circuit element is formed. A first spin coating layer having a first etching rate equal to the etching rate of the insulating layer is formed on the surface, and a second spin coating layer having a first etching rate lower than the first etching rate is formed on the first spin coating layer.
Forming a second spin coat layer having an etching rate of 1 and etching back the first and second spin coat layers.
The surface of the layer planarized by the two spin coating layers is further planarized during the etch back, and a semiconductor device having a flat and sufficiently thick insulating layer can be obtained.

According to the second aspect of the invention, since the first spin coating layer and the second spin coating layer are formed of different coating materials, the etching rate can be changed even if the same etching conditions are used. It is possible and easy to manufacture.

According to the semiconductor device manufacturing method of the third aspect of the present invention, since the first spin coating layer and the second spin coating layer are formed of the same coating material, the coating process can be simplified.

According to the semiconductor device manufacturing method of the fourth aspect of the present invention, the first spin coating layer and the second spin coating layer are formed under different firing conditions using different or the same coating material. The coating process can be simplified and the etching rate can be finely adjusted.

[Brief description of drawings]

FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment of the invention.

[Explanation of symbols]

 1 Semiconductor Substrate 3 Circuit Element 4 Insulating Layer 5 First Spin Coating Layer 6 Second Spin Coating Layer

Claims (4)

[Claims] 1. A circuit element is formed on a semiconductor substrate, an insulating layer covering the circuit element is formed on the semiconductor substrate, and an uneven surface of the insulating layer formed covering the circuit element is formed.
A first spin coating layer having a first etching rate equal to the etching rate of the insulating layer is formed, and a second spin coating layer having a first etching rate lower than the first etching rate is formed on the first spin coating layer.
A method of manufacturing a semiconductor device, wherein a second spin coating layer having an etching rate of 1 is formed, and the first and second spin coating layers are etched back. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first spin coating layer and the second spin coating layer are formed of different coating materials. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first spin coating layer and the second spin coating layer are formed of the same coating material. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the first spin coating layer and the second spin coating layer are formed under different firing conditions.