JPS62245654A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance the accuracy of patterns, to form a wiring pattern having a small stepping, and to improve the reliability of a semiconductor device by a method wherein, when the wiring pattern is going to be formed, a film-forming and patterning process is performed by separating it into two processes so that the edge of the pattern is formed in two steppings. CONSTITUTION:A silicon oxide film 2 is formed on the surface of a silicon substrate 1, and teh first aluminum layer 3a of the prescribed thickness is formed on the film 2. Then, the first resist pattern 4a is formed, and the first layer of wiring layer pattern is formed by performing an etching on the film 3a using the resist pattern 4a as a mask. Then, after the pattern 4a has been removed, the second resist pattern 4b is formed on the first layer by performing the same method as above. subsequently, the second aluminum layer 3b is formed by performing an etching using the pattern 4b as a mask. Then, a film- forming process and an etching process are performed separately so that a stepping is made on the edge of the pattern, and the wiring pattern having a small stepping can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a method of manufacturing a wiring pattern whose cross-sectional shape has a gentle slope.

[Prior art and its problems]

BACKGROUND ART With the progress of semiconductor technology, the degree of integration of semiconductor devices continues to increase, and high-density wiring technology and multilayer wiring technology have become indispensable technologies for increasing the degree of integration of semiconductor devices.

For example, wet etching is often used to pattern the aluminum (AΩ) wiring layer 100. Since this wet etching method is isotropic etching, side etching occurs and the resist pattern 101 is etched from the sides, resulting in a difference in pattern conversion. This pattern conversion difference is as follows: film thickness t = 8000 ~ 1
When the thickness is on the order of μm, it is as shown in FIG. 2(a), and the larger the film thickness is, the larger the problem becomes, which hinders the miniaturization of semiconductor devices.

Further, when a second wiring layer pattern is formed on the first wiring layer pattern 100 formed in this manner via an interlayer insulating film 102 to form a multilayer wiring board, for example, as the interlayer insulating layer 102, When a silicon oxide film is deposited by the CVD method, the film is deposited in an overhang shape as shown in FIG. There was a problem that it was easy to occur.

The present invention has been made in view of the above-mentioned circumstances, and aims to reduce pattern conversion differences, improve pattern accuracy, and alleviate step differences in pattern edges.

[Means for solving problems]

Therefore, in the present invention, when forming a wiring pattern, the film forming step and the patterning step are each performed at least twice so that the pattern edge has a plurality of steps. The first
the second pattern, so as to cover the first pattern;
A second pattern made of the same material and slightly larger than this is formed.

[Operation] In other words, since the patterning process is divided into two or more steps, the etching time for one time is short.
Side etch becomes smaller. Therefore, pattern conversion differences can be reduced.

In addition, there are two steps, and at the pattern edge, there is only a step corresponding to the film thickness in the second film forming step, and the step is alleviated.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(e) are process diagrams for manufacturing a multilayer wiring board according to an embodiment of the present invention.

First, as shown in FIG. 1(a), after forming a silicon oxide film 2 on the surface of a silicon substrate 1 on which a predetermined element region (not shown) is formed, a first film with a film thickness of 4,000 to 5,000
An aluminum layer 3a is formed by sputtering.

Next, as shown in FIG. 1(b), a first resist pattern 4a is formed, and using this as a mask, the first aluminum layer 3a is wet-etched to form the first pattern 3a. (The pattern conversion difference at this time is TA
shall be. ) Subsequently, after removing the first resist pattern 4a, a film with a thickness of 4000 to 50
A second aluminum layer 3a of 00000000000000000000000000000000000000000000000000000000000000 layers, a second aluminum layer 3a is formed on the second resist pattern 4b. This second
When forming the resist pattern 4b, the same photomask as used when forming the first resist pattern is used. Therefore, the pattern width (shape) is the same.

Thereafter, wet etching is performed using the second resist pattern 4b as a mask, as shown in FIG. 1(d).
A second pattern 3b is formed. The overetching time is adjusted so that the pattern conversion difference T at this time becomes T less TA.

In this way, an aluminum wiring pattern 3 (first layer) with a small pattern conversion difference and a small step difference is formed.

Then, as usual, a silicon oxide film is deposited as an interlayer insulating film 5 by CVD on this single layer, and after drilling through holes (not shown), a second wiring layer 6 is formed.
A two-layer wiring board is completed.

(Fig. 1(e)) In the wiring board formed in this way, the level difference in the pattern edge of the first layer wiring pattern base is 1/2 that of the conventional one, which is greatly reduced. , the interlayer insulating film does not have an overhang shape, and is highly reliable.

Further, since the first wiring layer is etched in two stages, the difference in pattern conversion is small and the accuracy is high.

In the example, the first resist pattern and the second resist pattern were made to have the same shape, and the first pattern was made smaller than the second pattern by adjusting the overetching time. , the first resist pattern may be formed smaller than the second resist pattern. In this way, there is no need to perform over-etching, so it is easy to detect the end point of etching.

Further, although the first pattern and the second pattern are made to have the same film thickness, they do not necessarily have to be the same and can be changed as appropriate. If the first pattern is formed to be slightly thicker than the second pattern, the etching time for forming the first pattern will be longer than the etching time for forming the second pattern. Since the amount also increases, it can be seen that the same mask pattern (resist pattern) may be used in this case as well.

Further, the wiring material is not limited to aluminum, and it goes without saying that the present invention is also effective for other wiring materials.

〔effect〕

As explained above, according to the method of the present invention, when forming a wiring pattern, the edges of the pattern are formed in two stages in the film forming process and pattern 26...the second wiring layer.

The patterning process is performed at least twice, and a second pattern, which is slightly larger than the first pattern formed in the first film formation and patterning process, is formed so as to cover the first pattern. As a result, a wiring layer pattern with high pattern accuracy and small steps is formed, making it possible to improve the reliability of the semiconductor device.

[Brief explanation of drawings]

FIGS. 1(a) to (e) are manufacturing process diagrams of a semiconductor device according to an embodiment of the present invention, and FIGS. 2(a) and (b) are diagrams showing wiring layer patterns formed by a conventional method. be. 100... First wiring layer pattern, 101... Resist pattern, 102... Interlayer insulating film, 103...
Second wiring layer pattern, 1... silicon substrate, 2...
- Silicon oxide film, 3a... first aluminum layer,
3b... second aluminum layer, 3... first layer wiring layer pattern, 4a... first resist pattern,
4b... Second resist pattern, 5... Interlayer insulating film, -9=

Claims (2)

[Claims] (1) A semiconductor device in which the edge of a wiring pattern has multiple steps. (2) When forming a wiring pattern for a semiconductor device, the formation process of one wiring pattern includes at least two wiring layer deposition processes and a pattern etching process, and the second deposition and pattern etching process includes the first A method for manufacturing a semiconductor device, comprising forming a second pattern slightly larger than the first pattern in a shape that covers the first pattern formed in the deposition and pattern etching process.