JPH05283378A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05283378A
JPH05283378A JP10364192A JP10364192A JPH05283378A JP H05283378 A JPH05283378 A JP H05283378A JP 10364192 A JP10364192 A JP 10364192A JP 10364192 A JP10364192 A JP 10364192A JP H05283378 A JPH05283378 A JP H05283378A
Authority
JP
Japan
Prior art keywords
film
etching
etched
photoresist pattern
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10364192A
Other languages
Japanese (ja)
Inventor
Yoichi Matsuda
洋一 松田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamaguchi Ltd
Original Assignee
NEC Yamaguchi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamaguchi Ltd filed Critical NEC Yamaguchi Ltd
Priority to JP10364192A priority Critical patent/JPH05283378A/en
Publication of JPH05283378A publication Critical patent/JPH05283378A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain an etching pattern where the width of wiring and the diameter of a hole are in accord with the dimension at design, in the etching process using a photoresist pattern. CONSTITUTION:When forming a photoresist pattern on a film 2 to be etched, and etching the film 2 to be etched, with the photoresist pattern 3 as a mask, a protective film 5 with a required thickness is stacked on the photoresist pattern 3 and the film 2 to be etched, and this protective film 5 and the film 2 to be etched are etched at the same time. Since the protective film 5 is left on the side of the photoresist pattern 3, the side etching of the film 2 to be etched is suppressed, and the error in etching dimension by side etching is suppressed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にエッチング工程の改善に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to improvement of an etching process.

【0002】[0002]

【従来の技術】従来の半導体装置におけるエッチング工
程は、図4(a)に示すように、先ず被エッチング膜で
あるシリコンウェハ21のアルミニウム膜22上にフォ
トレジストパターン23をパターニングする。次いで、
図4(b)のように、このフォトレジストパターン23
をマスクにしてBCl3 ,Cl2 のエッチングガスプラ
ズマ26でアルミニウム膜22をエッチングを行い、ア
ルミニウム配線27を得ている。
2. Description of the Related Art In a conventional semiconductor device etching process, as shown in FIG. 4A, first, a photoresist pattern 23 is patterned on an aluminum film 22 of a silicon wafer 21 which is a film to be etched. Then
As shown in FIG. 4B, this photoresist pattern 23
Using the mask as a mask, the aluminum film 22 is etched by the etching gas plasma 26 of BCl 3 and Cl 2 to obtain the aluminum wiring 27.

【0003】[0003]

【発明が解決しようとする課題】このような従来のエッ
チング工程では、エッチングすることによりサイドエッ
チングが生じ、形成されるアルミニウム配線27の線幅
がフォトレジストパターン23より細くなり、設計寸法
通りのエッチングパターンが得られないという問題点が
あった。又、ホールをエッチング形成する場合には、サ
イドエッチングによってフォトレジストの解像度以上の
微細なエッチングパターンが得られず、ホール径が設計
寸法よりも大きくなるという問題点があった。本発明の
目的は、設計寸法通りの配線幅及びホール径のエッチン
グパターンを得ることができる半導体装置の製造方法を
提供することにある。
In such a conventional etching process, side etching is caused by etching, the line width of the formed aluminum wiring 27 becomes narrower than that of the photoresist pattern 23, and etching according to design dimensions is performed. There was a problem that the pattern could not be obtained. Further, in the case of forming holes by etching, there is a problem that a fine etching pattern having a resolution higher than that of the photoresist cannot be obtained by side etching and the hole diameter becomes larger than the designed size. An object of the present invention is to provide a method of manufacturing a semiconductor device, which can obtain an etching pattern having a wiring width and a hole diameter as designed.

【0004】[0004]

【課題を解決するための手段】本発明は、被エッチング
膜の上にフォトレジストパターンを形成し、このフォト
レジストパターンをマスクにして被エッチング膜をエッ
チングするに際し、フォトレジストパターン及び被エッ
チング膜の上に所要膜厚の保護膜を堆積し、この保護膜
と被エッチング膜とを同時にエッチングする。
According to the present invention, a photoresist pattern is formed on a film to be etched, and when the film to be etched is etched using the photoresist pattern as a mask, the photoresist pattern and the film to be etched are formed. A protective film having a required film thickness is deposited on the protective film and the film to be etched is simultaneously etched.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の第1実施例を製造工程順に示す断面
図である。先ず、図1(a)のように、シリコンウェハ
1のアルミニウム膜2上にフォトレジストパターン3を
パターン形成する。その上で、図1(b)のように、C
HF3 のガスプラズマ4でフォトレジストパターン3及
びアルミニウム膜2上にCF2 高分子の保護膜5を堆積
させる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps. First, as shown in FIG. 1A, a photoresist pattern 3 is patterned on an aluminum film 2 of a silicon wafer 1. Then, as shown in FIG. 1 (b), C
A CF 2 polymer protective film 5 is deposited on the photoresist pattern 3 and the aluminum film 2 by a gas plasma 4 of HF 3 .

【0006】その後、図1(c)のように、BCl3
Cl2 のエッチングガスプラズマ6で保護膜5及びアル
ミニウム膜2のエッチングを行ない、アルミニウム配線
7を形成する。このエッチングにより、保護膜5がフォ
トレジストパターン3の側面に残されるため、その厚さ
分だけアルミニウム膜2のエッチングが抑制される。し
たがって、アルミニウム膜2にサイドエッチングが生じ
ても、フォトレジストパターン3の幅よりもアルミニウ
ム配線7の幅寸法が小さくなることはない。
Thereafter, as shown in FIG. 1 (c), BCl 3 ,
The protective film 5 and the aluminum film 2 are etched with an etching gas plasma 6 of Cl 2 to form an aluminum wiring 7. By this etching, since the protective film 5 is left on the side surface of the photoresist pattern 3, the etching of the aluminum film 2 is suppressed by the thickness thereof. Therefore, even if side etching occurs in the aluminum film 2, the width dimension of the aluminum wiring 7 does not become smaller than the width of the photoresist pattern 3.

【0007】図2は本発明の第2実施例を製造工程順に
示す断面図であり、ここではホールを開設する例を示し
ている。先ず、図2(a)のように、シリコンウェハ1
1のSiO2 膜12上にフォトレジストパターン13を
パターン形成する。その上で、図2(b)のように、C
HF3 のガスプラズマ14でフォトレジストパターン1
3及びSiO2 膜12上にCF2 高分子の保護膜15を
堆積させる
FIG. 2 is a sectional view showing the second embodiment of the present invention in the order of manufacturing steps, and here shows an example in which a hole is opened. First, as shown in FIG. 2A, the silicon wafer 1
A photoresist pattern 13 is formed on the first SiO 2 film 12. Then, as shown in FIG. 2B, C
Photoresist pattern 1 with HF 3 gas plasma 14
3 and a protective film 15 of CF 2 polymer is deposited on the SiO 2 film 12.

【0008】その後、図2(c)のように、CF4 ,C
HF3 ,Arのエッチングガスプラズマ16で保護膜1
5及びSiO2 膜12のエッチングを行う。このエッチ
ングにより、保護膜15はフォトレジストパターン13
の側面で残されるため、その厚さ分だけSiO2 膜12
のエッチングが抑制され、フォトレジストパターン13
より小さな径寸法のホール17が得られる。
Then, as shown in FIG. 2C, CF 4 , C
Protective film 1 with etching gas plasma 16 of HF 3 and Ar
5 and the SiO 2 film 12 are etched. By this etching, the protective film 15 becomes the photoresist pattern 13.
Since it is left on the side surfaces of the SiO 2 film 12,
Of the photoresist pattern 13 is suppressed.
Holes 17 with smaller diameter dimensions are obtained.

【0009】尚、保護膜の厚さを適切に設定すること
で、エッチング後に残される保護膜の厚さにより被エッ
チング膜のサイドエッチング量を適切に調整することが
できる。例えば、図3に示すように、従来の技術では保
護膜厚は0Åであるためサイドエッチング量は 0.2μm
あったが、保護膜厚を3000Åにするとサイドエッチング
量は0μmとなり、設計寸法通りのエッチングパターン
が得られることになる。
By properly setting the thickness of the protective film, the side etching amount of the film to be etched can be appropriately adjusted depending on the thickness of the protective film left after etching. For example, as shown in FIG. 3, in the conventional technique, the protective film thickness is 0Å, so the side etching amount is 0.2 μm.
However, when the protective film thickness is 3000 Å, the side etching amount becomes 0 μm, and the etching pattern according to the design dimension can be obtained.

【0010】[0010]

【発明の効果】以上説明したように本発明は、フォトレ
ジストパターン上に保護膜を堆積させた後エッチングを
行うので、この保護膜によって被エッチング膜のサイド
エッチングが抑制される。したがって、この保護膜の膜
厚を適切にすることで設計寸法通りの線幅或いはホール
径のエッチングパターンを得ることができる効果があ
る。
As described above, according to the present invention, etching is performed after depositing a protective film on a photoresist pattern, so that the protective film suppresses side etching of the film to be etched. Therefore, by appropriately adjusting the thickness of the protective film, it is possible to obtain an etching pattern having a line width or a hole diameter as designed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例を製造工程順に示す断面図
である。
FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

【図2】本発明の第2実施例を製造工程順に示す断面図
である。
FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps.

【図3】保護膜の膜厚とサイドエッチング量の関係を示
す図である。
FIG. 3 is a diagram showing a relationship between a film thickness of a protective film and a side etching amount.

【図4】従来の製造方法を工程順に示す断面図である。FIG. 4 is a cross-sectional view showing a conventional manufacturing method in the order of steps.

【符号の説明】[Explanation of symbols]

1 シリコンウェハ 2 アルミニウム膜 3 フォトレジストパターン 5 保護膜 7 アルミニウム配線 1 Silicon wafer 2 Aluminum film 3 Photoresist pattern 5 Protective film 7 Aluminum wiring

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 被エッチング膜の上にフォトレジストパ
ターンを形成し、このフォトレジストパターンをマスク
にして被エッチング膜をエッチングする工程を含む半導
体装置の製造方法において、前記フォトレジストパター
ン及び被エッチング膜の上に所要膜厚の保護膜を堆積
し、この保護膜と被エッチング膜とを同時にエッチング
することを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, comprising: forming a photoresist pattern on a film to be etched; and etching the film to be etched using the photoresist pattern as a mask. A method of manufacturing a semiconductor device, comprising: depositing a protective film having a required film thickness on top of the film; and simultaneously etching the protective film and the film to be etched.
JP10364192A 1992-03-30 1992-03-30 Manufacture of semiconductor device Pending JPH05283378A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10364192A JPH05283378A (en) 1992-03-30 1992-03-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10364192A JPH05283378A (en) 1992-03-30 1992-03-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05283378A true JPH05283378A (en) 1993-10-29

Family

ID=14359397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10364192A Pending JPH05283378A (en) 1992-03-30 1992-03-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05283378A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009067381A1 (en) * 2007-11-21 2009-05-28 Lam Research Corporation Method of controlling etch microloading for a tungsten-containing layer
KR101274308B1 (en) * 2005-05-31 2013-06-13 램 리써치 코포레이션 Critical dimension reduction and roughness control

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101274308B1 (en) * 2005-05-31 2013-06-13 램 리써치 코포레이션 Critical dimension reduction and roughness control
WO2009067381A1 (en) * 2007-11-21 2009-05-28 Lam Research Corporation Method of controlling etch microloading for a tungsten-containing layer
US8518282B2 (en) 2007-11-21 2013-08-27 Lam Research Corporation Method of controlling etch microloading for a tungsten-containing layer

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