JPH02143523A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable fine wirings to be formed with high precision by a method wherein a spacer film is previously formed between a wiring film and multilayer resist and then the spacer film is removed after removing the lower layer resist. CONSTITUTION:An insulating film 2 and a wiring film 3 are formed on an Si substrate 1 while a pure Cu film 7 as a spacer film is formed on the wiring film 5 by sputtering process. Later, a lower layer resist 4, an SOG 6 and an upper layer resist 6 are formed on the pure Cu film 7 while in such a state, the upper layer resist 6 is photo-etched to etch away the SOG 5 using the resist 6 as a mask. Then, the lower layer resist 4 is patterned by O2 reactive ion etching process using the resist 6 and SOG 5 as masks. At this time, Cu-made sidewall films 7a are formed by overetching process on the sidewalls of the lower layer resist 4 masked under the SOG 5. Then, the pure Cu film 7 and the wiring film 3 are anisotropically etched away to be patterned and then the lower resist 4 is removed. Finally, when the substrate 1 is immersed in a concentrated acid, any residual pure Cu film 7 and the sidewall film 7a are removed to form wirings 3a.

Description

[Detailed Description of the Invention] [Summary] Regarding a wiring formation method for a semiconductor device, for the purpose of forming fine wiring with high precision, multiple layers are formed on a wiring film made of AJ or AJ gold alloy formed on a substrate. In a wiring forming method in which a resist is formed, an upper resist is patterned, a lower resist is patterned using the upper resist as a mask, a wiring film is etched using the patterned resist film as a mask, and the lower resist is removed. , a spacer film is formed in advance between a wiring film and a plurality of resist layers, and the method includes a step of removing the spacer film after removing the lower layer resist.

[Industrial Field of Application] The present invention relates to a method for forming wiring in a semiconductor device.

As semiconductor devices have become more highly integrated in recent years, there has been a demand for finer wiring in the semiconductor devices, and a three-layer resist method has been put into practical use as a method for forming finer wiring.

[Prior Art] The three-layer resist method conventionally used to form fine interconnections will be explained with reference to FIG. 2 (a).
As shown in the figure, there is a 5i02 layer of about 1 micron on the Si substrate 1.
An insulating film 2 made of V or PSGM is formed, and a wiring v, 3 made of an aluminum alloy (for example, Aj-Cu alloy) is formed on the insulating film 2 to a thickness of about 1 micron by sputtering. Subsequently, as shown in FIG. 2(b), a lower resist 4 is coated on the wiring WA3 to a thickness of approximately 2 microns and baked, and as shown in FIG. 2(c), an intermediate layer of approximately 0.2 micron 5OG (spin-on glass) 5 was applied and baked, and then the same figure (d)
), apply the upper layer resist 6 to a thickness of about 1 micron. Both the lower resist 4 and the upper resist 6 are photoresists, but the upper resist 6 has a lower viscosity than the lower resist 4, and the 5OG 5 isolates both resists 4 and 6 to prevent them from melting. .

In this state, normal photoetching is performed as shown in Figure 2(e).
As shown in FIG. 3, the upper resist 6 is patterned in a desired manner, and then, as shown in FIG. For example, the etching process uses a mixed gas of CF4 + CHF3 at 0.1 to 0.5 tOrr, and
Performed in an electric field of ~500W.

After the etching of 5OG5, the lower resist 4 is anisotropically etched using the upper resist 6 and 5OG5 as masks, as shown in FIG. 2(g). That is, the etching is 0.01 to 0.05t.

Reactive ion etching with 02 of rr 40
It is carried out in an electric field of 0-600W.

Thereafter, as shown in FIG. 2<h), the wiring film 3 is anisotropically etched using the 5OG 5 and the lower resist 4 as a mask. The etching is, for example, S+ C, Q 4 +C
j 2 mixed gas at 0.01 tOrr, 500 to 60
This is carried out in an electric field of 0 W, and then the lower resist layer 4 is removed using a 02 plasma assher, as shown in Fig. 2 (1).
As shown in FIG. 3, the wiring PIA3 is patterned to form a desired wiring 3a.

[Problems to be Solved by the Invention] However, in the wiring forming method using the three-layer resist method as described above, when etching the lower resist 4 as shown in FIG. Over-etching is performed to completely remove the resist, and as a result of this over-etching, the surface of the wiring film 3 is sputtered and scattered, and the scattered alloy adheres to the side walls of the lower resist 4 as shown in the figure. A side wall film 3b is formed.Then, such a side wall film 3b is formed as shown in FIG.
), there is a problem in that even after the lower resist 4 is removed, the foreign matter remains on the wiring pattern and causes malfunction of the circuit.

Moreover, this sidewall film 3b has a h
The wiring 3a itself is also etched at the same time as the side wall film 3b is removed.
There was a problem that the accuracy of a could not be maintained.

An object of the present invention is to provide a method for forming fine wiring with high precision in a wiring formation method in which multiple layers of resist are used and the underlying resist is patterned by anisotropic etching as described above.

[Means for solving the problem] The above object is to solve the problem by
Multiple layers of resist are formed on a wiring film made of an alloy via a spacer film, the upper resist is patterned, the lower resist is patterned using the upper resist as a mask, and the patterned resist film and wiring are used as a mask. This is achieved by a manufacturing method in which the lower resist layer is removed after etching the film, and the spacer film is removed after the lower resist layer is removed.

[Operation] When the lower resist layer is anisotropically etched, the sidewall film of the spacer film formed by over-etching the lower spacer film is removed together with the spacer film when the spacer film is removed.

[Example] An example embodying the present invention will be described below with reference to FIG. Note that the same components in this embodiment as those in the conventional example are given the same numbers, and detailed explanation thereof will be omitted.

As shown in FIG. 1(a), first, an insulating film 2 and wiring [3] similar to those in the conventional example are formed on a Si substrate 1, and a pure cut film with a thickness of 500 to 1000 angstroms is formed on the wiring film 3 as a spacer film. The pattern 7 is formed by a sputtering method. After this, as shown in FIG. 1(b), pure Cu JIi
7, a lower layer resist 4.5OG5 and an upper layer resist 6 similar to the conventional example are formed.

In this state, as shown in FIG. 2(c), the upper layer resist 6
5OG5 is etched using the upper layer resist 6 as a mask, as shown in FIG. 2(d). Then, using the upper resists 6 and 5OG5 as masks, the lower resist 4 is patterned by reactive ion etching using 02. At this time, when over-etching is performed to completely remove the lower resist 4 in the etched portion, Cu is sputtered from the pure Cu film 7 as shown in FIG. 1(e), and the lower resist 4 masked with 5OG5 is sputtered. A Cu sidewall film 7a is formed on the sidewall.

Next, the pure CU film 7 and the wiring 11W3 are anisotropically etched under the same conditions as the etching of the wiring WA3 in the conventional example, so that the pure CU film 7 and the wiring WA3 are etched as shown in FIG. 1(f).
Pattern 3. At this time, 5OG which becomes a mask
5 are etched and removed at the same time. In this state, when the lower resist 4 is removed using 02 plasma asher, the wiring 3a and pure CLI are removed as shown in FIG. 1(g).
The sidewall film 7a of Jli7 and CU remains.

Therefore, if this Si substrate 1 is immersed in concentrated nitric acid for 20 to 30 seconds, the pure Cu film 7 will not have any effect on the wiring film 3.
and its side wall rr! A7a is removed, and a wiring 3a is formed as shown in FIG. 1(h).

Therefore, in this wiring formation method, 3
Layered resist method eliminates sidewall film and provides highly accurate alignment.
! 3a can be formed.

In addition to the above-mentioned three-layer cast method, this invention also applies to two methods.
It can be applied to a wiring forming method using a plurality of resist layers or more, and when forming multiple layers of wiring on a substrate, it is also possible to conduct wiring in each layer.

[Effects of the Invention] As described in detail above, the present invention is capable of forming fine wiring with high accuracy in a wiring formation method that uses multiple layers of resist and anisotropically etches the underlying resist for patterning. Demonstrate the best possible effects.

[Brief explanation of the drawing]

FIGS. 1(a) to (h) are process diagrams showing a wiring forming method embodying the present invention, and FIGS. 2(a) to (i) are process diagrams showing a conventional forming method.

Claims (1)

[Claims] 1. Forming multiple layers of resist on a wiring film made of Al or Al alloy formed on a substrate, patterning the upper resist, and then patterning the lower resist using the upper resist as a mask. However, in a wiring forming method in which a wiring film is etched using the patterned resist film as a mask and then the lower resist layer is removed, a spacer film is formed in advance between the wiring film and the plurality of resist layers, and after the lower layer resist is removed. A method for manufacturing a semiconductor device, comprising the step of removing the spacer film.