JPS6028248A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the disconnection of a second layer wiring formed on an Al wiring conductor by forming the conductor to a predetermined shape and forming the fringe of the conductor to a tapered shape through a DC bias sputtering method in which the semiconductor substrate side is brought to negative voltage when the Al wiring conductor is shaped on the substrate through an insulating layer. CONSTITUTION:A SiO2 layer 2 is applied on a Si substrate 1, an Al wiring conductor is laminated on the layer 2, and the conductor is changed into prescribed wiring layers 3 through reactive ion etching using a mixed gas of CCl4 and Cl2. Since the stepped sections of the wiring layers 3 are steep under the state, the following process is executed. That is, high-purity quartz glass is used as a target for sputtering, DC negative voltage applied to the substrate 1 is brought to -600--700V and RF sputtering is executed, and SiO2 films 4 are each formed to the surfaces of the wiring layers 3 and the surfaces of the exposed substrates 1 white the edge sections of the wiring layers 3 are tapered. The films 4 are renewed into a SiO2 film 4' coating the whole surface, and a second layer Al wiring layer 5 is attached on the film 4'.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of smoothing the periphery of a wiring pattern.

[Prior art and its problems]

To form a wiring pattern using, for example, aluminum as the wiring metal, a mask pattern is formed and then the aluminum is selectively etched.

Etching methods include isotropic etching and anisotropic etching, but in either case, the cross-sectional shape after etching takes on a steeply rising square shape at the edges. For this reason, the insulating film formed on the conventional wiring pattern has a thin film thickness on the side surface at the stepped portion, and also causes a decrease in insulation properties due to film stress. Furthermore, when a second wiring layer is formed on the insulating film, the steep left side of the insulating film may cause disconnection of the wiring, reducing the yield and reliability of device manufacturing. There are drawbacks such as

As a method to eliminate the above drawback, a method is known in which a resist with a smooth cross-sectional shape is used as a mask pattern, and the underlying film, for example, an aluminum film, is etched by an anisotropic etching method while also etching the resist. In this method, the controllability of the cross-sectional shape of the resist is poor, so the cross-sectional shape of the aluminum after etching is not reproducible, and the slope at the step part is too gentle, so it is not suitable for forming fine patterns.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor that can improve device reliability by smoothing the periphery of a wiring pattern in order to prevent the insulation of the insulating film on the wiring pattern from decreasing and to prevent disconnection of the 2Nth wiring. An object of the present invention is to provide a method for manufacturing a device.

[Inventor]

A feature of the present invention that combines the above objects is that a bias sputtering method is used to apply a negative DC voltage to the substrate side.
The reason is that only the peripheral edge of the wiring pattern is tapered and smoothed at the initial stage of forming an insulating film on the wiring pattern. That is, when forming an insulating film on a wiring pattern, only the peripheral edge of the wiring pattern is exposed by making the negative DC voltage on the substrate side higher than when forming a normal film.

This area is sputtered with a sputtering gas such as argon ions accelerated by the negative DC voltage, but the sputtering efficiency is maximum when the incident angle of the ions is about 45 degrees, so the exposed peripheral edge of the wiring pattern There will be a taper.

〔Effect of the invention〕

According to the present invention, the peripheral edge of the wiring pattern can have a gentle cross section, and the processing accuracy is also good, so the insulation properties of the insulating film on the wiring pattern are not deteriorated, and the second layer wiring can be Disconnection can be prevented and element reliability can be improved. In addition, since the processing accuracy is high, the degree of integration of the elements is not reduced, so the present invention is extremely effective in forming multilayer wiring for high-density integrated circuits.

[Embodiments of the invention]

1 to 4 are process cross-sectional views showing one embodiment of the present invention. First, as shown in FIG. 1, a silicon oxide film 2 is formed on a silicon substrate 1 by, for example, a thermal oxidation method, and an aluminum wiring layer 3 with a thickness of 1 μm, for example, is formed on this silicon oxide film 2 as a first wiring layer. form. The aluminum wiring N3 is formed by forming an aluminum film by sputtering or the like, applying, for example, a photoresist as a mask, performing buttering, and etching the aluminum film by, for example, a reactive ion etching method using a mixed gas of CCl4 and C12. Form by selectively etching.

In this state, the level difference in the wiring layer 30 is steep. Note that the line width and space width of the wiring layer in Figure 1 are approximately 2
It is μm.

Next, when forming the silicon oxide film 4 on the aluminum wiring layer 3 by RF bias sputtering using, for example, high-purity quartz glass (Si02) as a sputtering target and argon (Ar) as a sputtering residue, for example, Ar pressure is 10mTorr! When sputtering was performed for 30 minutes with DC negative tortoise pressures applied to the target and substrate sides at -600 V and -170 V, respectively, as shown in Figure 2, the silicon oxide film 4 was formed only on the flat part. tsoo
The edge of the Keitaun wiring side i is etched to have a taper of about 45i. In other words, since the negative DC voltage on the substrate side is large, the sputtering rate is higher than the deposition rate of the silicon oxide film at the edge of the wiring layer due to its dependence on the incident angle. As a result, the edge of the wiring layer is sputter-etched with ions, but due to the dependence on the incident angle, the edge of the wiring layer has a taper of about 45 degrees.

Next, R
F sputtering method, plasma C method using SiH4 and N20 gas, reduced pressure C method using SiH4 and O2 gas,
'For example, a silicone film 4' is used as an insulating film using the VD method.
FIG. 3 shows the state in which about 1 μm of the film has been deposited.

FIG. 4 shows a state in which an aluminum wiring layer 5 having a thickness of 1 μm is further formed as a second wiring layer thereon. As can be seen from FIG. 4, the thus formed silicon oxide film 4' and aluminum wiring layer 5 are deposited to approximately the same thickness on the sloped portions as on the flat portions.

It has been found that this does not reduce the insulation properties of the insulating layer, makes it difficult for the second layer wiring to be disconnected, and improves device reliability.

[Embodiment of the Invention Fairy]

The invention is not limited to the embodiments described above. For example, in the step shown in FIG. 2, the silicon oxide film 4 is deposited on a flat portion, but the present invention is effective even if the silicon oxide film 4 is deposited under conditions where it is hardly deposited.

Moreover, although the case of an aluminum film has been described as a wiring layer, metals such as MO, W, PT, and Au, silicide films thereof, polycrystalline silicon films, etc. may also be used.

In addition to the silicon oxide film, the insulating film may be a silicon nitride J-edge, a silicate glass film containing impurities such as phosphorus, 1 liter, boron, or the like.

[Brief explanation of drawings]

1 to 4 are process sectional views showing one embodiment of the present invention. In the figure, 1...Silicon substrate, 2.4.4'...Clicon oxide film (insulating layer) 3.5.
...Aluminum film (wiring layer).

Claims (2)

[Claims] (1) In the process of forming an insulating film on a wiring conductor formed on a semiconductor substrate, a step of tapering the periphery of the wiring conductor by bias sputtering in which a negative DC voltage is applied to the substrate side. A method of manufacturing a semiconductor device, comprising: (2) A method for manufacturing a semiconductor device according to item 1 of the patent encirclement, characterized in that a film containing aluminum as a main component is used as the wiring conductor.