JP2821623B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2821623B2 JP2821623B2 JP18434589A JP18434589A JP2821623B2 JP 2821623 B2 JP2821623 B2 JP 2821623B2 JP 18434589 A JP18434589 A JP 18434589A JP 18434589 A JP18434589 A JP 18434589A JP 2821623 B2 JP2821623 B2 JP 2821623B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal wiring
- wiring layer
- titanium
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置の製造方法に関し、更に詳しく
は、ボンディングパッドと配線用ワイヤとの接続を向上
させる半導体装置の製造方法に係るものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving the connection between a bonding pad and a wiring wire. is there.
［発明の概要］ 本発明は、ボンディングパッドとボンディングワイヤ
とを接続する半導体装置の製造方法において、 ボンディングパッドとなる金属配線層上に窒素とチタ
ンを主成分とする膜を形成し、該膜上にレジスト層を形
成してパターン露光を行なう工程と、レジストパターン
をマスクにして前記金属配線層をパターニングする工程
と、前記金属配線層のパターン上に絶縁膜を形成する工
程と、前記金属配線層のパターンのうちボンディングパ
ッドとなる部分上の絶縁膜を除去して開口部を形成し、
さらに、開口部の金属配線層表面層を除去する工程と、
前記金属配線層露呈部にボンディングワイヤを接続する
工程とを備えたことにより、 ボンディングパッドとボンディングワイヤとの密着強
度の向上を図ったものである。[Summary of the Invention] The present invention relates to a method for manufacturing a semiconductor device for connecting a bonding pad and a bonding wire, comprising forming a film containing nitrogen and titanium as main components on a metal wiring layer to be a bonding pad, and forming the film on the film. Forming a resist layer on the substrate and performing pattern exposure, patterning the metal wiring layer using the resist pattern as a mask, forming an insulating film on the pattern of the metal wiring layer, The opening is formed by removing the insulating film on the portion to be the bonding pad in the pattern of
Further, a step of removing the metal wiring layer surface layer of the opening,
A step of connecting a bonding wire to the exposed portion of the metal wiring layer to improve the adhesion strength between the bonding pad and the bonding wire.
［従来の技術］ 光露光法によってパターンを形成する場合、金属配線
層から反射する光の影響により、パターンの寸法精度が
低下するため、被加工膜である金属配線層表面に窒素と
チタンを主成分とする膜を反射防止膜として形成する技
術が知られている（特開昭61−185928号公報）。このた
め、従来、半導体装置から外部に電極を取り出す場合、
第２図に示すように、オーバーパッシベーション膜１を
選択的に開口して、例えば過酸化水素水とエチレンジア
ミン四酢酸の混合液を用いて金属配線層２表面に形成さ
れた反射防止膜としてのチタンオキシナイトライド（Ti
ON）膜３を除去してボンディングワイヤとの密着性の向
上を図っている。また、第３図は、金属配線層２の表面
の反射防止膜をオーバーパッシベーション膜１の形成す
る前に除去して製造された半導体装置であり、ワイヤボ
ンディングする場合は、オーバーパッシベーション膜１
を選択的に開口すればよい構成となっている。[Prior Art] When a pattern is formed by a light exposure method, since the dimensional accuracy of the pattern is reduced due to the influence of light reflected from the metal wiring layer, nitrogen and titanium are mainly applied to the surface of the metal wiring layer to be processed. A technique of forming a film as a component as an antireflection film is known (Japanese Patent Application Laid-Open No. 61-185928). Therefore, conventionally, when an electrode is taken out from a semiconductor device,
As shown in FIG. 2, the overpassivation film 1 is selectively opened, and a titanium as an antireflection film formed on the surface of the metal wiring layer 2 is formed by using, for example, a mixed solution of hydrogen peroxide and ethylenediaminetetraacetic acid. Oxynitride (Ti
ON) The film 3 is removed to improve the adhesion to the bonding wire. FIG. 3 shows a semiconductor device manufactured by removing the antireflection film on the surface of the metal wiring layer 2 before the formation of the overpassivation film 1.
Can be selectively opened.
なお、図中４は半導体基板を示している。 In the figure, reference numeral 4 denotes a semiconductor substrate.
［発明が解決しようとする課題］ しかしながら、このような従来例にあっては、反射防
止膜（チタンオキシナイトライド）３は、オーバーパッ
シベーション膜１をエッチングするエッチングガスによ
り除去できるが、このエッチングガスは金属配線層（例
えばアルミニウム）２をエッチングしないため、第２図
及び第３図に示すように金属配線層にチタン（Ti）が拡
散した表層拡散領域2aが露呈した状態となる。また、反
射防止膜３を過酸化水素水とエッチングアミン四酢酸の
混合液でエッチングした場合も、金属配線層２に形成さ
れた表層拡散領域2aは除去できないものであった。この
ため、金属配線層（ボンディングパッド）とボンディン
グワイヤ（Au等）との密着性が拡散したチタン（Ti）の
存在により低下し、ボンディング強度が得られない問題
点があった。[Problems to be Solved by the Invention] However, in such a conventional example, the antireflection film (titanium oxynitride) 3 can be removed by an etching gas for etching the overpassivation film 1. Since the metal wiring layer (eg, aluminum) 2 is not etched, the surface diffusion region 2a in which titanium (Ti) is diffused is exposed in the metal wiring layer as shown in FIGS. 2 and 3. Also, when the antireflection film 3 was etched with a mixed solution of hydrogen peroxide and etching amine tetraacetic acid, the surface diffusion region 2a formed in the metal wiring layer 2 could not be removed. Therefore, the adhesion between the metal wiring layer (bonding pad) and the bonding wire (Au or the like) is reduced by the presence of the diffused titanium (Ti), and there is a problem that the bonding strength cannot be obtained.
本発明は、このような従来の問題点に着目して創案さ
れたものであって、ボンディングパッドとボンディング
ワイヤとの密着力を向上させる半導体装置の製造方法を
得んとするものである。The present invention has been made in view of such a conventional problem, and has as its object to obtain a method of manufacturing a semiconductor device in which the adhesion between a bonding pad and a bonding wire is improved.
［課題を解決するための手段］ そこで、本発明は、ボンディングパッドとなる金属配
線層上に窒素とチタンを主成分とする膜を形成し、該膜
上にレジスト層を形成してパターン露光を行なう工程
と、レジストパターンをマスクにして前記金属配線層を
パターニングする工程と、前記金属配線層のパターン上
に絶縁膜を形成する工程と、前記金属配線層のパターン
のうちボンディングパッドとなる部分上の絶縁膜を除去
して開口部を形成し、さらに、開口部の金属配線層表面
層を除去する工程と、前記金属配線層露呈部にボンディ
ングワイヤを接続する工程とを備えたことを、その解決
手段としている。[Means for Solving the Problems] Accordingly, the present invention provides a method of forming a film mainly composed of nitrogen and titanium on a metal wiring layer to be a bonding pad, forming a resist layer on the film, and performing pattern exposure. Performing, a step of patterning the metal wiring layer using a resist pattern as a mask, a step of forming an insulating film on the pattern of the metal wiring layer, and a step of forming a bonding pad in the pattern of the metal wiring layer. Forming an opening by removing the insulating film, further comprising a step of removing a metal wiring layer surface layer of the opening, and a step of connecting a bonding wire to the metal wiring layer exposed portion, The solution.
［作用］ 金属配線層上に形成される膜は、窒素とチタンを主成
分とした、例えば窒化チタン（TiN），チタンオキシナ
イトライド（TiON）等で形成される。金属配線層のボン
ディングパッドとなる部分の表面層を除去することによ
り、金属配線層にチタン又は酸化チタンが拡散された表
層領域が除去されるため、金属配線層とボンディングワ
イヤとのボンディング強度を向上させる作用がある。[Operation] The film formed on the metal wiring layer is formed of, for example, titanium nitride (TiN), titanium oxynitride (TiON), or the like containing nitrogen and titanium as main components. By removing the surface layer at the portion of the metal wiring layer that will become the bonding pad, the surface layer region in which titanium or titanium oxide is diffused in the metal wiring layer is removed, thereby improving the bonding strength between the metal wiring layer and the bonding wire. Has the effect of causing.
［実施例］ 以下、本発明に係る半導体装置の製造方法の詳細を図
面に示す実施例に基づいて説明する。EXAMPLES Hereinafter, details of a method for manufacturing a semiconductor device according to the present invention will be described based on examples shown in the drawings.
歳１図Ａ〜第１図Ｇは、本発明の実施例の各工程を示
す断面図である。FIGS. 1A to 1G are cross-sectional views showing each step of the embodiment of the present invention.
先ず、本実施例は、シリコン基板10の表面にアルミニ
ウム（Al）膜11を形成する。（第１図Ａ）。First, in this embodiment, an aluminum (Al) film 11 is formed on the surface of a silicon substrate 10. (FIG. 1A).
次に、第１図Ｂに示すように、アルミニウム膜11の上
にチタンオキシナイトライド（TiON）膜12を形成する。
この膜12は、例えばチタン（Ti）をターゲットとし、窒
素ガスと酸素ガスとアルゴンガスをスパッタガスとする
リアクティブスパッタ法や、窒化チタンをターゲットと
するスパッタ法などにより堆積，形成することができ
る。Next, as shown in FIG. 1B, a titanium oxynitride (TiON) film 12 is formed on the aluminum film 11.
This film 12 can be deposited and formed by, for example, a reactive sputtering method using titanium (Ti) as a target and using a nitrogen gas, an oxygen gas, and an argon gas as a sputtering gas, or a sputtering method using titanium nitride as a target. .
さらに、同図Ｂに示すように、レジスト13を露光，パ
ターニングし、このレジスト13をマスクとして反応性イ
オンエッチング（RIE）を行ないチタンオキシナイトラ
イド膜12とアルミニウム膜11をパターニングしてボンデ
ィングパッドを含む金属配線層を形成する（第１図
Ｃ）。Further, as shown in FIG. 3B, the resist 13 is exposed and patterned, and the resist 13 is used as a mask to perform reactive ion etching (RIE) to pattern the titanium oxynitride film 12 and the aluminum film 11, thereby forming a bonding pad. Is formed (FIG. 1C).
次に、第１図Ｄに示すように、オーバーパッシベーシ
ョン膜14を全面に積層し、その後、アルミニウム膜11の
うちボンディングパッドとなる部分上方に図示しないレ
ジストパターンを形成し、このレジストパターンをマス
クとしてエッチングを行ない、第１図Ｅに示すように、
チタンオキシナイトライド膜12を除去する。この場合、
アルミニウム膜11が露光するが、このアルミニウム膜11
の表面にはチタン（Ti）やTiONが上記スパッタ等による
際に拡散して形成された表層拡散領域11aが形成されて
いる。Next, as shown in FIG. 1D, an overpassivation film 14 is laminated on the entire surface, and thereafter, a resist pattern (not shown) is formed above a portion of the aluminum film 11 which will be a bonding pad, and this resist pattern is used as a mask. After etching, as shown in FIG. 1E,
The titanium oxynitride film 12 is removed. in this case,
The aluminum film 11 is exposed.
A surface diffusion region 11a formed by diffusion of titanium (Ti) or TION by the above-described sputtering or the like is formed on the surface of the substrate.
次に、スパッタエッチングを行ない表層拡散領域11a
を除去し（第１図Ｆ）、アルミニウム膜11露出面にAuで
成るボンディングワイヤ15を接続すればよい。Next, the surface diffusion region 11a is subjected to sputter etching.
Is removed (FIG. 1F), and a bonding wire 15 made of Au may be connected to the exposed surface of the aluminum film 11.
以上、実施例について説明したが、本発明は、この他
各種の設計変更が可能である。例えば上記実施例におい
ては、アルミニウム膜11の上に反射防止膜としてチタン
オキシナイトライド（TiON）を形成したが、窒素とチタ
ンを主成分とする膜であれば、これに限るものではな
い。Although the embodiments have been described above, various other design changes can be made in the present invention. For example, in the above embodiment, titanium oxynitride (TiON) was formed as an anti-reflection film on the aluminum film 11, but the film is not limited to this as long as it is a film containing nitrogen and titanium as main components.
［発明の効果］ 以上の説明から明らかなように、本発明に係る半導体
装置の製造方法によれば、ボンディングパッドとボンデ
ィングワイヤとの密着性が高まり、ボンディング強度の
大きい半導体装置が得られる効果がある。[Effects of the Invention] As is clear from the above description, according to the method for manufacturing a semiconductor device according to the present invention, the adhesion between the bonding pad and the bonding wire is enhanced, and the effect of obtaining a semiconductor device having a large bonding strength is obtained. is there.
【図面の簡単な説明】 第１図Ａ〜第１図Ｇは本発明に係る半導体装置の製造方
法の実施例の各工程を示す断面図、第２図及び第３図は
従来例を示す断面図である。 10……シリコン基板、11……Al膜、12……TiON膜、13…
…レジスト、14……オーバーパッシベーション膜（絶縁
膜）。BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are cross-sectional views showing steps of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIGS. 2 and 3 are cross-sectional views showing a conventional example. FIG. 10 ... silicon substrate, 11 ... Al film, 12 ... TiON film, 13 ...
... Resist, 14 ... Overpassivation film (insulating film).
Claims (1)
窒素とチタンを主成分とする膜を形成し、該膜上にレジ
スト層を形成してパターン露光を行なう工程と、 レジストパターンをマスクにして前記金属配線層をパタ
ーニングする工程と、 前記金属配線層のパターン上に絶縁膜を形成する工程
と、 前記金属配線層のパターンのうちボンディングパッドと
なる部分上の絶縁膜を除去して開口部を形成し、さら
に、開口部の金属配線層表面層を除去する工程と、 前記金属配線層露呈部にボンディングワイヤを接続する
工程とを備えたことを特徴とする半導体装置の製造方
法。A step of forming a film containing nitrogen and titanium as main components on a metal wiring layer to be a bonding pad, forming a resist layer on the film and performing pattern exposure, and using the resist pattern as a mask. Patterning the metal wiring layer, forming an insulating film on the metal wiring layer pattern, removing the insulating film on a portion of the metal wiring layer pattern that will be a bonding pad to form an opening. Forming a metal wiring layer surface layer in the opening, and connecting a bonding wire to the exposed portion of the metal wiring layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18434589A JP2821623B2 (en) | 1989-07-17 | 1989-07-17 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18434589A JP2821623B2 (en) | 1989-07-17 | 1989-07-17 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0349231A JPH0349231A (en) | 1991-03-04 |
| JP2821623B2 true JP2821623B2 (en) | 1998-11-05 |
Family
ID=16151652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18434589A Expired - Lifetime JP2821623B2 (en) | 1989-07-17 | 1989-07-17 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2821623B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5480748A (en) * | 1992-10-21 | 1996-01-02 | International Business Machines Corporation | Protection of aluminum metallization against chemical attack during photoresist development |
| JPH0851113A (en) * | 1994-08-05 | 1996-02-20 | Sony Corp | Semiconductor integrated circuit and manufacture thereof |
| JP3485752B2 (en) * | 1997-03-18 | 2004-01-13 | 旭化成マイクロシステム株式会社 | Method for manufacturing semiconductor device |
| AT409429B (en) * | 1999-07-15 | 2002-08-26 | Sez Semiconduct Equip Zubehoer | METHOD FOR ETCH TREATING SEMICONDUCTOR SUBSTRATES FOR THE EXPLOSION OF A METAL LAYER |
| KR20010105034A (en) * | 2000-05-18 | 2001-11-28 | 송재인 | Suspension band unit |
| JP5882069B2 (en) | 2011-03-29 | 2016-03-09 | エスアイアイ・セミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| CN114088261A (en) * | 2021-11-22 | 2022-02-25 | 中国电子科技集团公司第四十八研究所 | Titanium oxynitride film pressure sensor and manufacturing method thereof |
-
1989
- 1989-07-17 JP JP18434589A patent/JP2821623B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0349231A (en) | 1991-03-04 |
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