JPH07245286A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH07245286A JPH07245286A JP3512794A JP3512794A JPH07245286A JP H07245286 A JPH07245286 A JP H07245286A JP 3512794 A JP3512794 A JP 3512794A JP 3512794 A JP3512794 A JP 3512794A JP H07245286 A JPH07245286 A JP H07245286A
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- etching
- alloy
- wiring
- wiring metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- ing And Chemical Polishing (AREA)
- Weting (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、高い耐湿性を要求され
る半導体素子の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device which requires high humidity resistance.
【0002】[0002]
【従来の技術】半導体素子、特に電力用の素子について
は、日本電子機械工業会が制定した規格に新たに耐湿性
に関係する項目が追加されたため、顧客側で耐湿性の高
い素子が要求されるようになっている。2. Description of the Related Art Regarding semiconductor elements, particularly power elements, since a new item related to moisture resistance has been added to the standards established by the Japan Electronic Machinery Manufacturers Association, customers are required to have high moisture resistance elements. It has become so.
【0003】[0003]
【発明が解決しようとする課題】耐湿性を劣化させる原
因にはいろいろあるが、最も大きな原因の一つにAlを
主体とする配線材料の腐食が挙げられる。これは、配線
パターンの形成のために、配線材料をエッチングした
際、エッチングされた側面で上縁が下層より突出するオ
ーバーハング状態が生じ、その上に被覆される保護膜
に、樹脂封止による組立ての際の樹脂からの応力、もし
くは試験中あるいは動作中の熱サイクルによる熱応力に
よりその縁部上で亀裂が入り、そこから侵入した水分が
配線材料を腐食するためである。There are various causes of deterioration of the moisture resistance, and one of the biggest causes is corrosion of the wiring material mainly composed of Al. This is because when the wiring material is etched to form a wiring pattern, an overhang state occurs in which the upper edge projects from the lower layer on the etched side surface, and the protective film coated on the overhang state is formed by resin sealing. This is because a stress is generated from the resin at the time of assembly, or a thermal stress due to a thermal cycle during a test or operation causes cracks on the edge portion thereof, and moisture penetrating therethrough corrodes the wiring material.
【0004】図2 (a) 、 (b) はそのようなオーバー
ハングの生ずる従来の配線パターニング工程を示し、同
図 (a) では、シリコン基板1の上にSi1%を含むA
l−Si合金2を蒸着し、その上に感光性高分子樹脂
(以下レジストを記す) 3を塗布したのち、フォトエッ
チングでパターニングする。同図 (b) では、りん酸・
硝酸・酢酸の混酸およびその水溶液を用いてAl−Si
合金2をエッチングし、一度に基板を露出する空隙4を
形成する。この際A部が突出するオーバーハングとな
る。2 (a) and 2 (b) show a conventional wiring patterning process in which such an overhang occurs. In FIG. 2 (a), A containing 1% Si on the silicon substrate 1 is used.
1-Si alloy 2 is vapor-deposited and a photosensitive polymer resin is deposited on it.
(Hereinafter, a resist will be described.) 3 is applied and then patterned by photoetching. In the figure (b), phosphoric acid
Al-Si using mixed acid of nitric acid and acetic acid and its aqueous solution
The alloy 2 is etched to form voids 4 that expose the substrate at one time. At this time, the portion A becomes an overhang that projects.
【0005】このようなオーバーハングに基づく保護膜
の割れのために耐湿性は劣化する。電力用半導体素子で
は、今後ますます薄膜化が進む事が予想され、保護膜も
薄くなって割れやすくなるため、エッチング形状の改善
が必須となる。本発明は、上述の問題を解決し、エッチ
ング形状を改善して配線上の被覆に亀裂の発生すること
のない半導体素子の製造方法を提供することにある。Moisture resistance deteriorates due to cracking of the protective film due to such overhangs. It is expected that the power semiconductor devices will become thinner and thinner in the future, and the protective film will become thinner and more likely to crack, so improvement of the etching shape is essential. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device, which solves the above-mentioned problems, improves etching shapes, and does not cause cracks in the coating on wiring.
【0006】[0006]
【課題を解決するための手段】上述の目的を達成するた
めに、本発明の半導体素子の製造方法は、Alを主体と
する材料からなる配線金属層をレジスト膜のマスクを用
いてパターニングする際に、先ずレジストマスクの窓を
通じてレジスト膜と配線金属層との界面部分をエッチン
グし、次いで配線金属層をエッチングするものとする。
レジスト膜と配線金属層との界面部分のエッチングにふ
っ酸系のエッチング液を用い、配線金属層のエッチング
にりん酸系のエッチング液を用いることが良い方法であ
り、それらのエッチング液が、ふっ酸あるいはりん酸と
硝酸および酢酸との混合液であることが良い。In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of patterning a wiring metal layer made of a material mainly containing Al by using a mask of a resist film. First, the interface between the resist film and the wiring metal layer is first etched through the window of the resist mask, and then the wiring metal layer is etched.
It is a good method to use a hydrofluoric acid-based etching solution for the etching of the interface between the resist film and the wiring metal layer and a phosphoric acid-based etching solution for the etching of the wiring metal layer. A mixed solution of acid or phosphoric acid and nitric acid or acetic acid is preferable.
【0007】[0007]
【作用】まず、レジストと配線金属層との界面をエッチ
ングしたのち、配線金属層をエッチングすれば、配線の
縁部はなだらかにだれた形状となり、オーバーハングが
生じない。When the interface between the resist and the wiring metal layer is etched first, and then the wiring metal layer is etched, the edges of the wiring are gently sloping and no overhang occurs.
【0008】[0008]
【実施例】以下、図2と共通の部分に同一の符号を付し
た図1 (a) 〜 (c) を引用し、本発明の一実施例の配
線パターニング工程を示す。図1 (a) に示すように図
2(a) と同様にレジスト2の20μmの幅の窓を有す
るパターンをSi1%のAl−Si合金2の上に形成し
たのち、ふっ酸・硝酸・酢酸混合液の水溶液を用いるエ
ッチング液に2分浸し、図1 (b) に示すようにレジス
ト2とAl−Si合金3との界面をエッチングして空隙
5を生じさせる。同時にAl−Si合金3の表面層もエ
ッチングされるが、エッチング量は、3〜5μmの配線
層2の厚さの1/3以下とした。エッチング液中のふっ
酸の組成比は、生ずる空隙5の角度により0.5〜2の範
囲で、また水の組成比も20〜40の範囲で調整するの
が良いことがわかった。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The wiring patterning process of one embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 1 (a), a pattern having a window of 20 μm width of the resist 2 is formed on the Al—Si alloy 2 containing 1% of Si as in the case of FIG. 2 (a). It is dipped in an etching solution using an aqueous solution of a mixed solution for 2 minutes, and the interface between the resist 2 and the Al—Si alloy 3 is etched to form a void 5 as shown in FIG. 1 (b). At the same time, the surface layer of the Al—Si alloy 3 is also etched, but the etching amount is set to 1/3 or less of the thickness of the wiring layer 2 of 3 to 5 μm. It was found that the composition ratio of hydrofluoric acid in the etching solution should be adjusted in the range of 0.5 to 2 depending on the angle of the void 5 formed, and the composition ratio of water should be adjusted in the range of 20 to 40.
【0009】次に、通常使用しているりん酸・硝酸・酢
酸の混酸の水溶液を用いて図1 (c) に示すようにAl
−Si合金2をエッチングし、空隙4を形成した。エッ
チングの終点は、エッチング面の反射率のセンサを用い
て決定してもよいが、通常の80%程度のエッチング時
間に設定するのが適当である。これはAl−Si合金2
の厚さが1/2になっていることと、残りの膜厚のばら
つきを考慮した結果である。これにより、図2のA部の
ようなオーバーハングは生じず、配線2の縁部は図示の
ようになだらかな形状になった。これにより、配線上を
被覆する窒化膜などの保護膜の厚さを薄くしても、組立
中、試験中あるいは動作中に保護膜に亀裂が入ることが
なく、耐湿性が向上した。Next, using an aqueous solution of a mixed acid of phosphoric acid / nitric acid / acetic acid which is usually used, as shown in FIG.
-Si alloy 2 was etched to form voids 4. The etching end point may be determined using a sensor of the reflectance of the etching surface, but it is appropriate to set the etching time to the usual etching time of about 80%. This is Al-Si alloy 2
Is a result of taking into account that the thickness of the film is halved and the remaining film thickness variation. As a result, the overhang unlike the portion A in FIG. 2 did not occur, and the edge portion of the wiring 2 had a smooth shape as shown in the figure. As a result, even if the thickness of the protective film such as a nitride film covering the wiring is thinned, the protective film is not cracked during assembly, testing, or operation, and the moisture resistance is improved.
【0010】[0010]
【発明の効果】本発明によれば、Alを主体とする配線
金属層のパターニングを2回のエッチングに分け、第一
のエッチング液を配線金属とレジストの間に侵入させて
その間を離し、第二のエッチングで配線金属を基板面ま
で除去することにより、配線縁部にオーバーハングが生
ぜずなだらかな傾斜が形成される。これにより、配線を
被覆する保護膜の割れが防止でき、耐湿性の高い半導体
素子が製造でき、特に電力用半導体素子の薄膜化の促進
に有効である。According to the present invention, the patterning of the wiring metal layer mainly composed of Al is divided into two etchings, and the first etching solution is made to enter between the wiring metal and the resist to separate them. By removing the wiring metal up to the substrate surface by the second etching, a gentle slope is formed without causing an overhang at the wiring edge. This makes it possible to prevent cracking of the protective film that covers the wiring, manufacture a highly moisture-resistant semiconductor element, and is particularly effective in promoting thinning of the power semiconductor element.
【図1】本発明の一実施例の配線パターニング工程を
(a) 、 (b) 、 (c) の順に示す断面図FIG. 1 shows a wiring patterning process according to an embodiment of the present invention.
Sectional drawing which shows in order of (a), (b), (c)
【図2】従来の配線パターニング工程を (a) 、 (b)
の順に示す断面図FIG. 2 shows a conventional wiring patterning process (a), (b)
Sectional view in order of
1 シリコン基板 2 Al−Si合金 3 レジスト 4、5 空隙 1 Silicon substrate 2 Al-Si alloy 3 Resist 4, 5 Void
Claims (3)
線金属層を感光性高分子樹脂膜のマスクを用いてパター
ニングする際に、先ず感光性高分子樹脂マスクの窓を通
じて感光性高分子樹脂膜と配線金属層との界面部分をエ
ッチングし、次いで配線金属層をエッチングすることを
特徴とする半導体素子の製造方法。1. When patterning a wiring metal layer made of a material mainly composed of aluminum using a mask of a photosensitive polymer resin film, first, a photosensitive polymer resin film is formed through a window of the photosensitive polymer resin mask. A method of manufacturing a semiconductor device, comprising etching an interface portion with a wiring metal layer and then etching the wiring metal layer.
分のエッチングにふっ酸系エッチング液を用い、配線金
属層のエッチングにりん酸系エッチング液を用いる請求
項1記載の半導体素子の製造方法。2. The semiconductor device according to claim 1, wherein a hydrofluoric acid-based etching solution is used for etching the interface between the photosensitive polymer resin film and the wiring metal layer, and a phosphoric acid-based etching solution is used for etching the wiring metal layer. Production method.
硝酸および酢酸との混合液である請求項2記載の半導体
素子の製造方法。3. The method for manufacturing a semiconductor device according to claim 2, wherein the etching solution is a mixed solution of hydrofluoric acid or phosphoric acid and nitric acid and acetic acid.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03512794A JP3158844B2 (en) | 1994-03-07 | 1994-03-07 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03512794A JP3158844B2 (en) | 1994-03-07 | 1994-03-07 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07245286A true JPH07245286A (en) | 1995-09-19 |
JP3158844B2 JP3158844B2 (en) | 2001-04-23 |
Family
ID=12433275
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP03512794A Expired - Fee Related JP3158844B2 (en) | 1994-03-07 | 1994-03-07 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3158844B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8786561B2 (en) | 2011-05-18 | 2014-07-22 | Microsoft Corporation | Disambiguating intentional and incidental contact and motion in multi-touch pointing devices |
KR102219385B1 (en) * | 2018-12-19 | 2021-02-25 | 한국과학기술원 | An user interface apparatus and method thereof |
-
1994
- 1994-03-07 JP JP03512794A patent/JP3158844B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP3158844B2 (en) | 2001-04-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |