KR0172773B1 - Method of forming pad of semiconductor device - Google Patents
Method of forming pad of semiconductor device Download PDFInfo
- Publication number
- KR0172773B1 KR0172773B1 KR1019950064434A KR19950064434A KR0172773B1 KR 0172773 B1 KR0172773 B1 KR 0172773B1 KR 1019950064434 A KR1019950064434 A KR 1019950064434A KR 19950064434 A KR19950064434 A KR 19950064434A KR 0172773 B1 KR0172773 B1 KR 0172773B1
- Authority
- KR
- South Korea
- Prior art keywords
- pad
- etching
- pix
- film
- passivation layer
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 31
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 19
- 238000002161 passivation Methods 0.000 claims abstract description 16
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 5
- 230000001681 protective effect Effects 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims description 8
- 239000010410 layer Substances 0.000 claims 6
- 235000014653 Carica parviflora Nutrition 0.000 claims 1
- 241000243321 Cnidaria Species 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 239000011241 protective layer Substances 0.000 claims 1
- 239000002253 acid Substances 0.000 abstract description 4
- 230000007797 corrosion Effects 0.000 abstract description 3
- 238000005260 corrosion Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Formation Of Insulating Films (AREA)
- Drying Of Semiconductors (AREA)
Abstract
반도체 소자의 패드 형성 방법에 있어서; 하부 절연막 상부에 패드 전도막을 패터닝한 후, 제1 보호막 및 제2 보호막을 차례대로 형성하는 단계; 패드 마스크를 사용한 선택 식각으로 상기 제2 보호막을 식각하는 단계; 전체구조 상부에 PIX를 형성하고, 패드 마스크를 사용한 선택 식각으로 상기 PIX를 식각하는 단계; 상기 PIX의 선택 식각에 의해 노출되는 상기 제1 보호막 상부에 잔류하는 PIX 를 제거하는 단계; 상기 제1 보호막을 식각 제거하는 단계를 포함하여 이루어지는 본 발명은 패드 식각시 PIX를 사용하여 패시베이션(Passivation)하고, 마지막 단계로 PECVD 산화막 식각함으로써, CF4와 O2분위기에서 패드 부위를 오픈시킬때, 알루미늄막 식각시 발생한 강산인자를 더불어 치환하여 패드부식을 방지하는 효과가 있다.A method of forming a pad of a semiconductor device; After patterning the pad conductive layer on the lower insulating layer, sequentially forming a first passivation layer and a second passivation layer; Etching the second passivation layer by selective etching using a pad mask; Forming a PIX on the entire structure, and etching the PIX by selective etching using a pad mask; Removing PIX remaining on the first passivation layer exposed by the selective etching of the PIX; The present invention comprising the step of etching away the first protective film is a passivation (Passivation) using PIX during the pad etching, and the last step by etching the PECVD oxide film, when opening the pad area in CF 4 and O 2 atmosphere In addition, the strong acid factor generated during the etching of the aluminum film is substituted with the effect of preventing pad corrosion.
Description
제1도는 종래 기술에 따라 형성된 패드 형성 공정도.1 is a pad forming process chart formed according to the prior art.
제2a도 내지 제2e도는 본 발명의 일실시예에 따른 패드 형성 공정도.2a to 2e is a process chart for forming a pad according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 절연막 20 : 알루미늄막10 insulating film 20 aluminum film
30 : 산화막 40 : 질화막30 oxide film 40 nitride film
50 : 마스크 60 : PIX50: mask 60: PIX
본 발명은 반도체 소자 제조 공정중 반도체 소자의 패드 형성 방법에 관한 것이다.The present invention relates to a method for forming a pad of a semiconductor device during a semiconductor device manufacturing process.
제1도는 종래 기술에 따른 금속 패드 형성 방법을 도시한 것으로, 하부 절연막(10) 상부에 패드용 금속막(20)을 패터닝한 후, 전체 구조 상부에 PECVD(Plasma Enhanced Chemical Vapor Deposition ; 이하 PECVD라 칭함)에 의한 산화막(30)과 PECVD에 의한 질화막(40)을 차례대로 형성하고 패드 마스크 및 식각공정을 통해 상기 PECVD 산화막과 상기 PECVD 질화막을 차례로 선택 식각하여 패드부위를 오픈시켰다.FIG. 1 illustrates a method for forming a metal pad according to the prior art. After the pad metal film 20 is patterned on the lower insulating film 10, PECVD (Plasma Enhanced Chemical Vapor Deposition) is formed on the entire structure. The oxide layer 30 and the nitride layer 40 by PECVD were formed in this order, and the pad region was opened by selectively etching the PECVD oxide layer and the PECVD nitride layer sequentially by a pad mask and an etching process.
현재까지는 패드용 금속막을 식각하여 패터닝한 감광막 제거제와 용매 그리고 탈이온수(Deionized Water) 린스(Rinse)를 사용하여 강산인자(P,Cl) 성분을 치환하였으나, 완벽하게 치환이 안되어서, 소수의 강산인자가 계속해서 금속위에 잔존하게 되어 후속 외부와의 도선 연결을 위해 패드 단자 형성시 패드 식각에 의해 금속 표면이 노출되어 이 때, 식각용액으로 쓰인 강산기가 대기중의 수분과 반응하여 패드용 금속막을 부식시켜 후속 패키지시 본딩을 방해하는 PCT(Pad Corrosion Test)을 유발시키는 문제점이 있었다.Until now, a strong acid factor (P, Cl) component was substituted by using a photoresist remover, a solvent, and deionized water rinse patterned by etching a metal film for pads, but it was not completely substituted. The prints continue to remain on the metal and the surface of the metal is exposed by the pad etching during the formation of the pad terminals for the subsequent wire connection to the outside. At this time, a strong acid used as an etching solution reacts with moisture in the air to form a pad metal film. There was a problem of causing a corrosion corrodion test (PCT) that corrodes bonding in subsequent packages.
상기와 같은 문제점을 해결하기 위해서 안출된 본 발명은 반도체 제조 공정에 있어서 식각 용액등에 의해 패드부위가 부식되는 것을 방지하는 반도체 소자의 패드 형성 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a pad of a semiconductor device that prevents the pad portion from being corroded by an etching solution or the like in the semiconductor manufacturing process.
상기 목적을 달성하기 위하여 안출된 본 발명은, 반도체 소자의 패드 형성 방법에 있어서; 하부 절연막 상부에 패드 전도막을 패터닝한 후, 제1 보호막 및 제2 보호막을 차례대로 형성하는 단계; 패드 마스크를 사용한 선택 식각으로 상기 제2 보호막을 식각하는 단계; 전체구조 상부에 PIX를 형성하고, 패드 마스크를 사용한 선택식각으로 상기 PIX를 식각하는단계; 상기 PIX의 선택 식각에 의해 노출되는 상기 제1 보호막 상부에 잔류하는 PIX를 제거하는 단계; 상기 제1 보호막을 식각 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a pad of a semiconductor device; After patterning the pad conductive layer on the lower insulating layer, sequentially forming a first passivation layer and a second passivation layer; Etching the second passivation layer by selective etching using a pad mask; Forming a PIX on the entire structure, and etching the PIX by selective etching using a pad mask; Removing PIX remaining on the first passivation layer exposed by selective etching of the PIX; And etching away the first passivation layer.
이하, 첨부된 도면 제2a도 내지 제2e도를 참조하여 본 발명을 상세하게 설명한다.Hereinafter, the present invention will be described in detail with reference to the attached drawings 2A to 2E.
제2a도 내지 제2e도는 본 발명의 일실시예에 따른 반도체 소자의 패드 형성 공정도이다.2A through 2E are diagrams illustrating a pad forming process of a semiconductor device according to an embodiment of the present invention.
제2a도에 도시된 바와 같이, 하부 절연막(10)상부에 패드용 알루미늄막(20)을 패터닝한 후, 전체구조 상부에 PECVD에 의해 산화막(30)을 약 3000Å정도 형성하고, 상기 PECVD 산화막(30)상부에 PECVD에 의해 질화막(40)을 약 5000Å정도를 형성한다.As shown in FIG. 2A, after the pad aluminum film 20 is patterned on the lower insulating film 10, an oxide film 30 is formed on the entire structure by PECVD at about 3000 kPa, and the PECVD oxide film ( 30) A nitride film 40 is formed on the upper surface of the substrate by PECVD.
이어서, 제2b도에 도시된 바와 같이, PECVD 질화막(40)상에 마스크 공정으로 패드부위를 오픈하기 위한 패드 마스크(50)를 형성한다. 이 때, 플라즈마 식각에 의한 손상을 방지하기 위해서 약 3㎛이상 도포하나 본 발명에서는 통상 사용되는 1.2~2㎛ 전도의 마스크 두께를 사용한다.Subsequently, as shown in FIG. 2B, a pad mask 50 is formed on the PECVD nitride film 40 to open the pad portion by a mask process. In this case, in order to prevent damage due to plasma etching, the coating is applied in an amount of about 3 μm or more, but in the present invention, a mask thickness of 1.2 to 2 μm conduction is generally used.
계속해서, 제2c도에 도시된 바와 같이, 상기 PECVD 산화막(30)이 드러날때까지 PECVD 질화막(40)을 식각하고, 패드 마스크(50)를 제거한다.Subsequently, as shown in FIG. 2C, the PECVD nitride film 40 is etched until the PECVD oxide film 30 is exposed, and the pad mask 50 is removed.
이어서, 제2d도에 도시된 바와 같이, 상기 PECVD 질화막(40) 상부에 PIX(60)을 보호막으로 약 16㎛이상 도포한다.Subsequently, as shown in FIG. 2D, a PIX 60 is coated on the PECVD nitride film 40 with a protective film of about 16 μm or more.
마지막으로, 제2e도에 도시된 바와 같이, 상기 PIX(60)를 패드 마스크로 사용하여 선택 식각하고, 노출되는 PECVD 산화막(30) 상부에 잔류하는 PIX를 O2분위기 속에서 플라즈마 식각을 실시한 후, PECVD 산화막(30)을 CF4와 O2분위기 속에서 플라즈마 식각하여 패드부위를 오픈시킨다. 이때, 식각가스비율은 CF4:O2= 10:1 정도로 한다.Finally, as shown in FIG. 2e, after selectively etching using the PIX 60 as a pad mask, plasma etching is performed on PIX remaining on the exposed PECVD oxide layer 30 in an O 2 atmosphere. The PECVD oxide film 30 is plasma-etched in CF 4 and O 2 atmospheres to open the pad region. At this time, the etching gas ratio is about CF 4 : O 2 = 10: 1.
상기와 같이 이루어지는 본 발명은 패드 식각시 PIX를 사용하여 패시베이션(Passivation)하고, 마지막 단계로 PECVD 산화막 식각함으로써, CF4와 O2분위기에서 패드 부위를 오픈시킬때, 알루미늄막 식각시 발생한 강산인자를 더불어 치환하여 패드 부식을 방지하는 효과가 있다.In the present invention made as described above, a strong acid factor generated during etching of an aluminum film when the pad is opened in CF 4 and O 2 atmosphere by passivation using PIX and etching PECVD oxide film as a final step is performed. In addition, there is an effect to prevent the pad corrosion by replacing.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950064434A KR0172773B1 (en) | 1995-12-29 | 1995-12-29 | Method of forming pad of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950064434A KR0172773B1 (en) | 1995-12-29 | 1995-12-29 | Method of forming pad of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970052419A KR970052419A (en) | 1997-07-29 |
| KR0172773B1 true KR0172773B1 (en) | 1999-03-30 |
Family
ID=19446917
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950064434A KR0172773B1 (en) | 1995-12-29 | 1995-12-29 | Method of forming pad of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172773B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11444014B2 (en) | 2019-09-19 | 2022-09-13 | Samsung Electronics Co., Ltd. | Semiconductor packages including an insulating layer including a recessed surface and methods of manufacturing the same |
-
1995
- 1995-12-29 KR KR1019950064434A patent/KR0172773B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11444014B2 (en) | 2019-09-19 | 2022-09-13 | Samsung Electronics Co., Ltd. | Semiconductor packages including an insulating layer including a recessed surface and methods of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970052419A (en) | 1997-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR930005949B1 (en) | Process for fabricating semiconductor device | |
| US5930664A (en) | Process for preventing corrosion of aluminum bonding pads after passivation/ARC layer etching | |
| JPH09298199A (en) | Semiconductor device and its manufacture | |
| KR0172773B1 (en) | Method of forming pad of semiconductor device | |
| JPS59232424A (en) | Semiconductor device and manufacture of the same | |
| KR100289655B1 (en) | Metal wiring formation method of semiconductor device | |
| JP3158844B2 (en) | Method for manufacturing semiconductor device | |
| KR100267778B1 (en) | Method for forming pad of semiconductor device | |
| KR100387761B1 (en) | Method for providing a metal layer in a semiconductor device | |
| KR100591146B1 (en) | Semiconductor device and formation method of bonding pad in the semiconductor device | |
| US7071101B1 (en) | Sacrificial TiN arc layer for increased pad etch throughput | |
| KR100244755B1 (en) | Method of opening input-output pad | |
| KR100264237B1 (en) | Method of forming hole | |
| KR100192173B1 (en) | Method of forming a tungsten plug in a semiconductor device | |
| KR100588892B1 (en) | Method for preventing pads of semiconductor device from being oxidized | |
| KR910002137B1 (en) | Semiconductor device | |
| KR100244293B1 (en) | Semiconductor material manufacturing method | |
| KR100267771B1 (en) | Method for manufacturing semiconductor material | |
| KR100249014B1 (en) | Method of fabricating semiconductor device | |
| KR100329788B1 (en) | Method for forming bonding pad in semiconductor device | |
| KR100532981B1 (en) | Etching method of semiconductor device | |
| KR19990085434A (en) | Pad open method of semiconductor device | |
| KR20000065842A (en) | Manufacturing method for contact hole in semiconductor device | |
| KR20090046574A (en) | Method for fabricating a pad open in a semiconductor | |
| KR20010061546A (en) | Method for contact etching in ferroelectric memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20060920 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |