KR20000065842A - Manufacturing method for contact hole in semiconductor device - Google Patents
Manufacturing method for contact hole in semiconductor device Download PDFInfo
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- KR20000065842A KR20000065842A KR1019990012549A KR19990012549A KR20000065842A KR 20000065842 A KR20000065842 A KR 20000065842A KR 1019990012549 A KR1019990012549 A KR 1019990012549A KR 19990012549 A KR19990012549 A KR 19990012549A KR 20000065842 A KR20000065842 A KR 20000065842A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
Description
본 발명은 반도체 장치의 콘택홀 형성방법에 관한 것으로, 특히 콘택홀을 형성시 발생하는 폴리머를 암모니아, 과수, 순수를 사용하여 제거함으로써, 반도체 장치의 특성을 향상시키는데 적당하도록 한 반도체 장치의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. In particular, a contact hole of a semiconductor device suitable for improving characteristics of a semiconductor device by removing a polymer generated when forming a contact hole using ammonia, fruit water and pure water. It relates to a formation method.
도1a 내지 도1c는 종래 반도체 장치의 콘택홀 제조공정 수순단면도로서, 이에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부에 절연막(2)을 증착하고, 그 절연막(2)의 상부에 포토레지스트(3)를 도포하고, 노광 및 현상하여 패턴을 형성한 후, 그 포토레지스트(3) 패턴을 식각마스크로 하는 식각공정으로 상기 절연막(2)에 콘택홀을 형성하여 상기 반도체 소자의 특정영역을 노출시키는 단계(도1a)와; 산소플라즈마를 이용하여 상기 포토레지스트(3) 패턴을 제거하는 단계(도1b)와; 상기 콘택홀의 형성으로 노출되는 반도체소자의 특정영역상부의 손상영역(5)을 CF4, O2혼합가스를 이용하여 식각하는 단계(도1c)로 구성된다.1A to 1C are cross-sectional views of a process for manufacturing a contact hole in a conventional semiconductor device. As shown therein, an insulating film 2 is deposited on an upper portion of a substrate 1 on which a semiconductor element is formed, and on top of the insulating film 2. After the photoresist 3 is applied, exposed and developed to form a pattern, a contact hole is formed in the insulating film 2 by an etching process using the photoresist 3 pattern as an etching mask to identify the semiconductor device. Exposing the area (FIG. 1A); Removing the photoresist 3 pattern using oxygen plasma (FIG. 1B); The damaged region 5 on the specific region of the semiconductor device exposed by the formation of the contact hole is etched using CF 4 , O 2 mixed gas (FIG. 1C).
이하, 상기와 같이 구성된 종래 반도체 장치의 콘택홀 형성방법을 좀 더 상세히 설명한다.Hereinafter, a method of forming a contact hole in a conventional semiconductor device configured as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부에 산화막 등의 절연막(2)을 증착하고, 그 절연막(2)의 상부전면에 포토레지스트(3)를 도포한다.First, as shown in FIG. 1A, an insulating film 2 such as an oxide film is deposited on the substrate 1 on which the semiconductor element is formed, and the photoresist 3 is coated on the upper surface of the insulating film 2.
그 다음, 상기 포토레지스트(3)를 노광 및 현상하여 상기 절연막(2)의 일부영역을 노출시키는 패턴을 형성하고, 상기 포토레지스트(3) 패턴을 식각마스크로 사용하는 식각공정으로 상기 노출된 절연막(2)을 식각하여 상기 기판(1)에 형성한 반도체 소자의 특정영역을 노출시킨다. 이와 같은 콘택홀의 형성시 상기 노출되는 기판(1) 영역의 상부에는 CFx계의 폴리머(POLYMER,4)가 발생하며, 그 식각공정에 의해 노출되는 기판(1) 영역의 상부는 손상되어 손상영역(5)이 발생된다.Next, the photoresist 3 is exposed and developed to form a pattern exposing a portion of the insulating film 2, and the exposed insulating film is formed by an etching process using the photoresist 3 pattern as an etching mask. Etching (2) is performed to expose a specific region of the semiconductor element formed on the substrate (1). When the contact hole is formed, a CF x- based polymer (POLYMER) 4 is generated on the exposed region of the substrate 1, and the upper portion of the region of the substrate 1 exposed by the etching process is damaged to damage the region. (5) is generated.
그 다음, 도1b에 도시한 바와 같이 산소플라즈마를 이용하여 상기 산화막(2)의 상부에 잔존하는 포토레지스트(3) 패턴을 제거한다.Then, as shown in FIG. 1B, the photoresist 3 pattern remaining on the oxide film 2 is removed using oxygen plasma.
그 다음, 도1c에 도시한 바와 같이 CF4와 O2혼합가스를 이용하는 식각공정으로 상기 기판상에 형성된 손상영역(5)을 식각한다. 상기 손상영역(5)이 식각되지 않고 잔존하는 경우에는 그 손상영역(5)에 의해 상기 형성한 콘택홀을 통해 배선을 형성하는 경우 접촉저항이 증가하게 된다.Then, as shown in FIG. 1C, the damaged region 5 formed on the substrate is etched by an etching process using a CF 4 and O 2 mixed gas. When the damaged region 5 remains unetched, contact resistance increases when wiring is formed through the contact hole formed by the damaged region 5.
그러나, 상기 손상영역(5)의 상부측에는 폴리머(4)가 형성되어 있는 상태이므로, 상기 식각공정으로 손상영역(5)의 식각이 완전하게 일어나지 않으며, 오히려 상기 CF4의 사용으로 CFx계인 폴리머의 탄소간 결합을 더욱 강하게 하여 접촉저항을 더욱 증가시키는 결과를 낳게 된다.However, since the state in which the polymer (4) side of the upper portion of the damaged area 5 is formed, the etching process the etching of the damaged area (5) does not occur completely, the rather CF x sealed polymer by the use of the CF 4 This results in a stronger bond between carbons and an increase in contact resistance.
상기한 바와 같이 종래 반도체 장치의 콘택홀 형성방법은 콘택홀을 형성한 후, 발생하는 폴리머를 제거하지 않고, 그 하부의 기판 손상영역을 제거하여, 손상영역을 완전히 제거할 수 없어 배선과의 접촉저항이 증가하며 이에 따라 반도체 장치의 특성이 열화되는 문제점이 있었다.As described above, in the conventional method of forming a contact hole in a semiconductor device, after forming a contact hole, the substrate damage region underneath is removed without removing the polymer, and thus the damage region cannot be completely removed. There is a problem that the resistance is increased, thereby deteriorating the characteristics of the semiconductor device.
이와 같은 문제점을 감안한 본 발명은 콘택홀 형성으로 발생하는 폴리머를 완전히 제거하여 그 하부측의 기판 손상영역을 완전히 제거할 수 있도록 하여, 콘택홀을 통해접속되는 배선과 기판영역의 접촉저항을 줄일 수 있는 반도체 장치의 콘택홀 형성방법을 제공함에 그 목적이 있다.In view of the above problems, the present invention can completely remove the polymer damage caused by contact hole formation to completely remove the substrate damage region at the lower side thereof, thereby reducing the contact resistance between the wiring and the substrate region connected through the contact hole. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device.
도1a 내지 도1c는 종래 반도체 장치의 콘택홀 제조공정 수순단면도.1A to 1C are cross-sectional views of a process for manufacturing a contact hole in a conventional semiconductor device.
도2a 내지 도2d는 본 발명 반도체 장치의 콘택홀 제조공정 수순단면도.2A to 2D are cross-sectional views of a process for manufacturing a contact hole in a semiconductor device of the present invention.
도3은 종래 기술에 의해 제조된 반도체 장치와 본 발명의 기술에 의해 제조된 반도체 장치의 접촉저항을 비교도시한 그래프도.3 is a graph showing a comparison of contact resistance between a semiconductor device manufactured by the prior art and a semiconductor device manufactured by the technology of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:기판 2:절연막1: Substrate 2: Insulation film
3:포토레지스트 4:폴리머3: Photoresist 4: Polymer
5:손상영역5: damage area
상기와 같은 목적은 반도체 소자가 형성된 기판의 상부에 절연막을 증착하고, 그 절연막의 상부에 포토레지스트 패턴을 형성하는 단계와; 상기 포토레지스트 패턴을 식각마스크로 하는 건식식각공정으로 상기 기판에 형성된 반도체 소자의 특정영역을 노출시키는 콘택홀을 형성하는 단계와; 상기 포토레지스트 패턴을 제거하는 단계와; 상기 노출되는 반도체 소자의 특정영역의 상부측에 상기 콘택홀 형성과정에서 발생하는 손상영역을 식각하는 단계로 구성되는 반도체 장치의 콘택홀 형성방법에 있어서, 상기 포토레지스트를 제거한 후, 상기 콘택홀 형성을 위한 건식식각공정으로 발생하는 폴리머를 암모니아, 과수, 순수를 사용하여 제거하는 폴리머 제거단계를 더 포함하여 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is a step of depositing an insulating film on the substrate on which the semiconductor element is formed, and forming a photoresist pattern on the insulating film; Forming a contact hole exposing a specific region of a semiconductor device formed on the substrate by a dry etching process using the photoresist pattern as an etching mask; Removing the photoresist pattern; A method of forming a contact hole in a semiconductor device, the method comprising: etching a damaged region occurring in the process of forming a contact hole on an upper side of a specific region of the exposed semiconductor device, wherein the photoresist is removed, and then the contact hole is formed. It is achieved by further comprising a polymer removal step of removing the polymer generated by the dry etching process using ammonia, fruit water, pure water, described in detail with reference to the accompanying drawings, the present invention as follows. .
도2a 내지 도2d는 본 발명 반도체 장치의 콘택홀 제조공정 수순단면도로서, 이에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부전면에 절연막(2)을 증착하고, 그 절연막(2)의 상부에 포토레지스트(3) 패턴을 형성한 다음, 그 포토레지스트(3) 패턴을 식각마스크로 사용하는 식각공정으로 상기 절연막(2)에 콘택홀을 형성하여 상기 반도체 소자의 특정영역을 노출시키는 단계(도2a)와; 산소 플라즈마를 이용하여 상기 포토레지스트(3) 패턴을 제거하는 단계(도2b)와; 콘택홀의 형성시 발생하는 폴리머(4)를 암모니아, 과수, 순수를 사용하여 제거하는 단계(도2c)와; 상기 콘택홀의 형성으로 노출되는 반도체 소자의 특정영역 상부인 손상영역(5)을 식각하는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a process for manufacturing a contact hole in a semiconductor device according to the present invention. As shown therein, an insulating film 2 is deposited on the upper surface of a substrate 1 on which a semiconductor element is formed, and the insulating film 2 is After forming a photoresist (3) pattern on the top, and then forming a contact hole in the insulating film (2) in an etching process using the photoresist (3) pattern as an etching mask to expose a specific region of the semiconductor device (FIG. 2A); Removing the photoresist 3 pattern using an oxygen plasma (FIG. 2B); Removing the polymer 4 generated during the formation of the contact hole using ammonia, fruit water and pure water (FIG. 2C); Etching the damaged region 5 that is above the specific region of the semiconductor device exposed by the formation of the contact hole (Fig. 2d).
이하, 상기와 같은 본 발명 반도체 장치의 콘택홀 형성방법을 좀 더 상세히 설명한다.Hereinafter, a method of forming a contact hole in the semiconductor device of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 반도체 소자가 형성된 기판(1)의 상부전면에 절연막(2)을 증착하고, 그 절연막(2)의 상부 전면에 포토레지스트(3)를 도포하고, 노광 및 현상하여 상기 절연막(2)의 일부영역을 노출시키는 포토레지스트(3) 패턴을 형성한다.First, as shown in FIG. 2A, an insulating film 2 is deposited on the entire upper surface of the substrate 1 on which the semiconductor element is formed, a photoresist 3 is applied on the entire upper surface of the insulating film 2, and exposure and development are performed. The photoresist 3 pattern is formed to expose a portion of the insulating film 2.
그 다음, 상기 포토레지스트(3) 패턴을 식각마스크로 하는 건식식각공정으로 상기 노출된 절연막(2)을 식각하여 그 하부의 기판(1)에 형성된 반도체 소자의 특정영역을 노출시킨다. 이때 역시 종래와 같이 폴리머(4)가 발생하고, 상기 식각에 의해 노출되는 반도체 소자의 특정영역 상부측에는 손상영역(5)이 발생하게 된다.Then, the exposed insulating film 2 is etched by a dry etching process using the photoresist 3 pattern as an etching mask to expose a specific region of the semiconductor device formed on the substrate 1 below. At this time, the polymer 4 is generated as in the related art, and the damage region 5 is generated on the upper side of the specific region of the semiconductor device exposed by the etching.
그 다음, 도2b에 도시한 바와 같이 상기 포토레지스트(3) 패턴을 산소 플라즈마를 이용하여 제거한다.Next, as shown in Fig. 2B, the photoresist 3 pattern is removed using an oxygen plasma.
그 다음, 도2c에 도시한 바와 같이 상기 콘택홀을 통해 노출되는 기판영역 상에 형성되어 있는 폴리머(4)를 암모니아, 과수, 순수의 순차적인 처리를 통해 제거한다.Then, as shown in FIG. 2C, the polymer 4 formed on the substrate region exposed through the contact hole is removed through sequential treatment of ammonia, fruit water and pure water.
그 다음, 도2d에 도시한 바와 같이 상기 폴리머(4)의 제거로 그 상부면이 완전히 노출되는 손상영역(5)을 CF4와 O2혼합가스를 사용하여 식각한다. 이와 같이 폴리머(4)가 제거된 상태에서는 그 손상영역(5)을 완전히 제거할 수 있으며, 이에 따라 콘택저항을 감소시킬 수 있게 된다.Next, as shown in FIG. 2D, the damaged region 5 whose upper surface is completely exposed by the removal of the polymer 4 is etched using the CF 4 and O 2 mixed gas. As described above, in the state where the polymer 4 is removed, the damaged area 5 can be completely removed, thereby reducing the contact resistance.
도3은 본 발명과 종래의 기술에 의해 제조된 반도체 장치의 콘택저항을 비교도시한 그래프도로서, 이에 도시한 바와 같이 본 발명은 폴리머의 완전한 제거 및 그 하부의 손상된 기판영역을 식각함에 의해, 종래의 콘택저항에 비해 약 130ohm/ea 정도 감소한 콘택저항을 갖게 된다.FIG. 3 is a graph showing a comparison of contact resistance between a semiconductor device manufactured according to the present invention and the prior art. As shown in the present invention, the present invention is based on the complete removal of a polymer and etching of a damaged substrate region below. It has a contact resistance of about 130 ohm / ea reduced compared to the conventional contact resistance.
상기한 바와 같이 본 발명은 콘택홀 형성후 발생하는 폴리머를 모두 제거하고 그 하부의 손상된 기판영역을 식각함으로써, 콘택저항을 줄이고 이에 따라 반도체 소자의 특성저하를 방지하는 효과가 있다.As described above, the present invention removes all the polymers generated after the formation of the contact hole and etches the damaged substrate region under the contact hole, thereby reducing the contact resistance and thus preventing the deterioration of the characteristics of the semiconductor device.
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| KR1019990012549A KR20000065842A (en) | 1999-04-09 | 1999-04-09 | Manufacturing method for contact hole in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100814259B1 (en) * | 2006-12-27 | 2008-03-17 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
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| KR100814259B1 (en) * | 2006-12-27 | 2008-03-17 | 동부일렉트로닉스 주식회사 | Method of manufacturing semiconductor device |
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