KR20030002714A - Method for forming a contact hole in a semiconductor device - Google Patents

Method for forming a contact hole in a semiconductor device Download PDF

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Publication number
KR20030002714A
KR20030002714A KR1020010038414A KR20010038414A KR20030002714A KR 20030002714 A KR20030002714 A KR 20030002714A KR 1020010038414 A KR1020010038414 A KR 1020010038414A KR 20010038414 A KR20010038414 A KR 20010038414A KR 20030002714 A KR20030002714 A KR 20030002714A
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South Korea
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contact hole
region
hard mask
mask layer
deep
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KR1020010038414A
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Korean (ko)
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KR100425935B1 (en
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허상범
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

PURPOSE: A method for fabricating a contact hole of a semiconductor device is provided to simultaneously form a deep contact hole and a shallow contact hole without leaving a photoresist layer by firstly etching a predetermined thickness of the region for the deep contact hole and by secondly etching the regions for the shallow contact hole and the deep contact hole. CONSTITUTION: A hard mask layer(120) is formed on an interlayer dielectric(110) on a semiconductor substrate(100) having a stepped lower structure. The hard mask layer is patterned to expose the region for the deep contact hole. A predetermined thickness of the region of the deep contact hole is firstly etched by using the patterned hard mask layer. A photoresist layer is applied on the resultant structure and is patterned to expose the region for the shallow contact hole. After the hard mask layer in the exposed region is eliminated, the photoresist layer is removed. The interlayer dielectric is secondly etched until the semiconductor substrate and the lower structure are exposed by using the hard mask layer as a mask so that the deep contact hole and the shallow contact hole are formed.

Description

반도체 소자의 콘택홀 형성 방법{Method for forming a contact hole in a semiconductor device}Method for forming a contact hole in a semiconductor device

본 발명은 콘택홀 형성 방법에 관한 것으로, 특히 단차가 다른 영역에서 딥(deep) 콘택홀과 쉘로우(shallow) 콘택홀을 동시에 형성하는 방법에 관한 것이다.The present invention relates to a method of forming a contact hole, and more particularly, to a method of simultaneously forming a deep contact hole and a shallow contact hole in a region having a different step.

최근에, 반도체 소자의 집적도가 증가함에 따라 콘택(contact)을 서로 다른높낮이로 형성시켜야 하는 경우가 발생한다. 이 때, 깊은 딥(deep) 콘택홀과 상대적으로 얕은 쉘로우(shallow) 콘택홀을 형성시켜야 하는데, 이들을 동시에 형성시켜야 하는 경우에 문제가 발생하게 된다. 높은 단차를 기준으로 콘택홀을 형성하면 낮은 단차에서의 과도한 식각이 문제가 될 것이며, 낮은 단차를 기준으로 콘택홀을 형성하는 경우에는 높은 단차의 영역에서 콘택홀이 형성되지 않는다. 이 경우 낮은 단차 지역에서 과도하게 식각이 되더라도 문제가 되지 않도록 하지막의 두께를 증가시킨다던가, 선택비가 높은 물질을 하지막에 미리 증착시켜 두는 방법들이 사용되고 있으나 공정 조건이 매우 어렵고 불안정하여, 양산화 과정에서 수많은 문제점을 야기시킨다. 또한, 높은 단차 지역, 또는 낮은 단차 지역에서 먼저 콘택홀을 형성한 후 다른 단차 지역에서 콘택홀을 형성하고자 하는 시도는 콘택홀 내에 제거하기 어려운 감광제의 잔여물을 남긴다는 측면에서 바람직하지 못하다. 이러한 시도는 콘택 저항을 증가시키며, 이물질 발생을 촉진시켜 수율을 저하시키게 된다.In recent years, as the degree of integration of semiconductor devices increases, it is necessary to form contacts at different heights. At this time, a deep deep contact hole and a relatively shallow shallow contact hole should be formed, which causes a problem. If the contact hole is formed based on the high step, excessive etching at the low step will be a problem, and when the contact hole is formed based on the low step, the contact hole is not formed in the region of the high step. In this case, there is a method of increasing the thickness of the underlayer so as not to be a problem even if it is excessively etched in a low stepped area, or by depositing a material having a high selectivity on the underlayer in advance, but the process conditions are very difficult and unstable. It causes a lot of problems. In addition, attempts to form contact holes first in high stepped areas or in low stepped areas and then in other stepped areas are undesirable in terms of leaving residues of photoresist that are difficult to remove in the contact holes. This approach increases the contact resistance, promotes the generation of foreign matter and lowers the yield.

상기의 문제점을 해결하기 위하여, 본 발명의 목적은, 반도체 소자에서 단차가 다른 영역에 콘택홀을 형성할 때 딥 콘택홀이 형성될 영역을 먼저 소정 두께 만큼 1차 식각하고 쉘로우 콘택홀이 형성될 영역과 딥 콘택홀이 형성될 영역을 동시에 2차 식각하는 2단계의 식각 방법을 사용함으로써, 콘택홀 형성후 감광막의 잔여물을 남기지 않고 딥 콘택홀과 쉘로우 콘택홀을 동시에 양호하게 형성하는 데 있다.In order to solve the above problems, an object of the present invention is to firstly etch a region where a deep contact hole is to be formed by a predetermined thickness and to form a shallow contact hole when forming a contact hole in a region having a different step height. By using a two-step etching method for simultaneously etching the region and the region in which the deep contact hole is to be formed at the same time, it is possible to form both the deep contact hole and the shallow contact hole at the same time without leaving the residue of the photoresist film after forming the contact hole. .

도 1a 내지 1d는 본 발명에 따른 단차가 다른 영역에서의 콘택홀 형성 방법을 순차적으로 나타낸 단면도.1A to 1D are cross-sectional views sequentially illustrating a method for forming a contact hole in an area having different steps according to the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100: 반도체 기판110: 층간 절연막100: semiconductor substrate 110: interlayer insulating film

120: 하드 마스크층130: 포토레지스트층120: hard mask layer 130: photoresist layer

상기 목적을 달성하기 위하여, 본 발명의 반도체 소자의 콘택홀 형성 방법은, 단차를 가진 하부 구조가 형성되어 있는 반도체 기판의 층간 절연막 상에 하드 마스크층을 형성하는 단계; 딥 콘택홀이 형성될 영역을 노출시키도록 상기 하드 마스크층 패터닝하는 단계; 상기 패터닝된 하드 마스크층을 이용하여 상기 딥 콘택홀이 형성될 영역을 소정 깊이 만큼 1차 식각하는 단계; 상기 전체 구조 상부에 포토레지스트층을 도포한 후 쉘로우 콘택홀이 형성될 영역을 노출시키도록 패터닝하는 단계; 상기 노출된 영역의 하드 마스크층을 제거한 후 상기 포토레지스트층을 제거하는 단계; 및 상기 하드 마스크층을 마스크로 사용하여 반도체 기판 및 하부 구조까지 상기 층간 절연막을 동시에 2차 식각하여 딥 콘택홀 및 쉘로우 콘택홀을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the contact hole forming method of the semiconductor device of the present invention, the step of forming a hard mask layer on the interlayer insulating film of the semiconductor substrate is formed a lower structure having a step; Patterning the hard mask layer to expose a region where a deep contact hole is to be formed; First etching a region where the deep contact hole is to be formed by a predetermined depth using the patterned hard mask layer; Applying a photoresist layer over the entire structure and patterning the photoresist layer to expose a region where a shallow contact hole is to be formed; Removing the photoresist layer after removing the hard mask layer of the exposed region; And forming a deep contact hole and a shallow contact hole by simultaneously etching the interlayer insulating layer to the semiconductor substrate and the lower structure using the hard mask layer as a mask.

이제 도 1a 내지 1d를 참조로 본 발명의 일 실시예를 상세히 설명한다.An embodiment of the present invention will now be described in detail with reference to FIGS. 1A-1D.

먼저 도 1a를 참조하면, 단차를 가진 하부 구조가 형성되어 있는 반도체 기판(100)의 층간 절연막(110) 상에 하드 마스크층(120)을 형성한다. 여기서 "A"로 표시된 부분은 딥(deep) 콘택홀이 형성될 깊이이고 "B"로 표시된 부분은 쉘로우(shallow) 콘택홀이 형성될 깊이이다. 하드 마스크층(120)을 딥 콘택홀이 형성될 부분을 노출하도록 패터닝한다. 그 후 패터닝된 하드 마스크층(120)을 마스크로 사용하여 딥 콘택홀이 형성될 영역의 층간 절연막(110)을 딥 콘택홀의 깊이에서 쉘로우 콘택홀의 깊이 만큼을 뺀 깊이(즉, A-B)만큼 식각한다. 이때 공정 마진 확보를 위해 "A-B"의 깊이보다 약간 과식각(overetch)할 수도 있다. 하드 마스크층(120)은 그대로 둔채로 다음 단계를 진행한다.First, referring to FIG. 1A, a hard mask layer 120 is formed on an interlayer insulating layer 110 of a semiconductor substrate 100 on which a lower structure having a step is formed. Here, the portion labeled "A" is the depth at which the deep contact hole is to be formed and the portion labeled "B" is the depth at which the shallow contact hole is to be formed. The hard mask layer 120 is patterned to expose a portion where a deep contact hole is to be formed. After that, the patterned hard mask layer 120 is used as a mask to etch the interlayer insulating layer 110 in the region where the deep contact hole is to be formed by the depth of the deep contact hole minus the depth of the shallow contact hole (ie, AB). . At this time, it may be overetched slightly than the depth of "A-B" to secure the process margin. The hard mask layer 120 is left as it is and proceeds to the next step.

이제 도 1b를 참조하면, 상기 하드 마스크층(120)를 포함한 전체 구조 상부에 포토레지스트층을 도포한다. 이 포토레지스트층을 노광하고 현상하여 쉘로우 콘택홀이 형성될 영역을 노출시키도록 패터닝하여 포토레지스트 패턴(130)을 형성한다.Referring now to FIG. 1B, a photoresist layer is applied over the entire structure including the hard mask layer 120. The photoresist layer is exposed and developed to pattern the photoresist pattern 130 to expose the region where the shallow contact hole is to be formed.

도 1c를 참조하면, 포토레지스트 패턴을 마스크로 사용하여 하부의 노출된 하드 마스크층(120)을 식각한 후 포토레지스트 패턴을 제거한다. 그럼으로써 딥 콘택홀과 쉘로우 콘택홀을 동시에 식각할 수 있는 하드 마스크 패턴이 형성된다. 딥 콘택홀이 형성될 영역의 소정 깊이를 미리 제거하였으므로, 딥 콘택홀이 형성될 영역과 쉘로우 콘택홀이 형성될 영역의 동시에 식각할 깊이는 "B" 만큼의 동일한 깊이가 된다.Referring to FIG. 1C, the lower exposed hard mask layer 120 is etched using the photoresist pattern as a mask and then the photoresist pattern is removed. As a result, a hard mask pattern capable of simultaneously etching the deep contact hole and the shallow contact hole is formed. Since the predetermined depth of the region where the deep contact hole is to be formed is removed in advance, the depth to be simultaneously etched between the region where the deep contact hole is to be formed and the region where the shallow contact hole is to be formed is the same depth as "B".

도 1d를 참조하면, 하드 마스크 패턴을 마스크로 사용하여 이용하여 층간 절연막을 식각하여 딥 콘택홀과 쉘로우 콘택홀을 형성한다. 그 후에, 하드 마스크층을 제거한다.Referring to FIG. 1D, the interlayer insulating layer is etched using the hard mask pattern as a mask to form a deep contact hole and a shallow contact hole. After that, the hard mask layer is removed.

상기 설명한 바와 같이, 본 발명에 따르면, 반도체 소자에서 단차가 다른 영역에 콘택홀을 형성할 때 딥 콘택홀이 형성될 영역을 먼저 소정 두께 만큼 1차 식각하고 쉘로우 콘택홀이 형성될 영역과 딥 콘택홀이 형성될 영역을 동시에 2차 식각하는 2단계의 식각 방법을 사용함으로써, 콘택홀 형성후 감광막의 잔여물을 남기지 않고 딥 콘택홀과 쉘로우 콘택홀을 동시에 양호하게 형성할 수 있다.As described above, according to the present invention, when forming a contact hole in a region having a different step in a semiconductor device, first, the region in which the deep contact hole is to be formed is first etched by a predetermined thickness, and the region in which the shallow contact hole is to be formed and the deep contact are formed. By using the two-step etching method of simultaneously etching the region in which the hole is to be formed, the deep contact hole and the shallow contact hole can be satisfactorily formed simultaneously without leaving the residue of the photoresist film after forming the contact hole.

Claims (2)

단차를 가진 하부 구조가 형성되어 있는 반도체 기판의 층간 절연막 상에 하드 마스크층을 형성하는 단계;Forming a hard mask layer on the interlayer insulating film of the semiconductor substrate having the stepped lower structure formed thereon; 딥 콘택홀이 형성될 영역을 노출시키도록 상기 하드 마스크층 패터닝하는 단계;Patterning the hard mask layer to expose a region where a deep contact hole is to be formed; 상기 패터닝된 하드 마스크층을 이용하여 상기 딥 콘택홀이 형성될 영역을 소정 깊이 만큼 1차 식각하는 단계;First etching a region where the deep contact hole is to be formed by a predetermined depth using the patterned hard mask layer; 상기 전체 구조 상부에 포토레지스트층을 도포한 후 쉘로우 콘택홀이 형성될 영역을 노출시키도록 패터닝하는 단계;Applying a photoresist layer over the entire structure and patterning the photoresist layer to expose a region where a shallow contact hole is to be formed; 상기 노출된 영역의 하드 마스크층을 제거한 후 상기 포토레지스트층을 제거하는 단계; 및Removing the photoresist layer after removing the hard mask layer of the exposed region; And 상기 하드 마스크층을 마스크로 사용하여 반도체 기판 및 하부 구조까지 상기 층간 절연막을 동시에 2차 식각하여 딥 콘택홀 및 쉘로우 콘택홀을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법Forming a deep contact hole and a shallow contact hole by simultaneously etching the interlayer insulating film to the semiconductor substrate and the underlying structure by using the hard mask layer as a mask, and forming a deep contact hole and a shallow contact hole. 제1항에 있어서, 상기 딥 콘택홀이 형성될 영역을 1차 식각하는 깊이는 상기 딥 콘택홀의 깊이에서 상기 쉘로우 콘택홀의 깊이 만큼을 뺀 깊이인 것을 특징으로 하는 반도체 소자의 콘택홀 형성 방법.The method of claim 1, wherein the depth of the first etching of the region in which the deep contact hole is to be formed is a depth obtained by subtracting the depth of the shallow contact hole by the depth of the deep contact hole.
KR10-2001-0038414A 2001-06-29 2001-06-29 Method for forming a contact hole in a semiconductor device KR100425935B1 (en)

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KR970013032A (en) * 1995-08-21 1997-03-29 김광호 Contact Forming Method for Highly Integrated Semiconductor Devices

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KR101132730B1 (en) * 2006-12-14 2012-04-06 에스케이케미칼주식회사 Anti-gastritis and anti-ulcer agent containing Momordica saponin?

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