KR20030044338A - Method of forming via hole for semiconductor device - Google Patents

Method of forming via hole for semiconductor device Download PDF

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Publication number
KR20030044338A
KR20030044338A KR1020010075054A KR20010075054A KR20030044338A KR 20030044338 A KR20030044338 A KR 20030044338A KR 1020010075054 A KR1020010075054 A KR 1020010075054A KR 20010075054 A KR20010075054 A KR 20010075054A KR 20030044338 A KR20030044338 A KR 20030044338A
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KR
South Korea
Prior art keywords
via hole
hard mask
film
forming
sacrificial layer
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KR1020010075054A
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Korean (ko)
Inventor
조윤석
조준희
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주식회사 하이닉스반도체
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Priority to KR1020010075054A priority Critical patent/KR20030044338A/en
Publication of KR20030044338A publication Critical patent/KR20030044338A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

PURPOSE: A method for forming a via hole in a semiconductor device is provided to be capable of preventing damage of a lower metal wiring by using an additional sacrificial layer. CONSTITUTION: A sacrificial layer(23) and an intermetal dielectric(24) are sequentially formed on a substrate(20) having a lower metal line(21). A hard mask(25A) is formed on the intermetal dielectric(24). The intermetal dielectric(24) is entirely etched, and the sacrificial layer(23) is partially etched using the hard mask(25A) as a mask. After removing the hard mask(25A), then a via hole is formed by etching of the sacrificial layer(23), wherein the sacrificial layer(23) has relatively high etching selectivity compared to the hard mask(25A). Preferably, polysilicon is used as the hard mask(25A) and nitride is used as the sacrificial layer(23).

Description

반도체 소자의 비아홀 형성방법{METHOD OF FORMING VIA HOLE FOR SEMICONDUCTOR DEVICE}Via hole formation method of semiconductor device {METHOD OF FORMING VIA HOLE FOR SEMICONDUCTOR DEVICE}

본 발명은 반도체 제조 기술에 관한 것으로, 특히 하드 마스크(hard mask)를 이용한 반도체 소자의 비아홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of forming via holes in a semiconductor device using a hard mask.

일반적으로, 비아홀은 다층 금속 배선에서 상부배선과 하부배선을 연결하기 위하여 형성하며, 비아홀 형성을 위한 식각공정시 마스크로서는 포토레지스트 패턴을 이용한다. 한편, 반도체 소자의 고집적화에 따라 포토레지스트 패턴의 두께가 감소됨에 따라, 비아홀 형성을 위한 식각시 비아홀 상부가 손상되는 등의 문제가 발생하기 때문에, 최근에는 폴리실리콘 등을 이용한 하드 마스크(hard mask)를 적용하여 비아홀을 형성하고 있다.In general, the via hole is formed to connect the upper wiring and the lower wiring in the multilayer metal wiring, and a photoresist pattern is used as a mask during the etching process for forming the via hole. On the other hand, as the thickness of the photoresist pattern decreases as the semiconductor device is highly integrated, a problem such as damage to the upper part of the via hole occurs during etching to form the via hole, and thus, recently, a hard mask using polysilicon is used. Is applied to form via holes.

도 1a 내지 도 1d는 상기 하드 마스크를 이용한 종래의 반도체 소자의 비아홀 형성방법을 나타낸 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a via hole in a conventional semiconductor device using the hard mask.

도 1a를 참조하면, 알루미늄(Al)막으로 이루어진 하부 금속배선(11)이 형성된 반도체 기판(10) 상부에 산화막으로 이루어진 층간절연막(12)을 형성한다. 그 다음, 층간절연막(12) 상부에 폴리실리콘막(13)을 증착하고, 그 상부에 포토레지스트 패턴(14)을 형성한다.Referring to FIG. 1A, an interlayer insulating film 12 made of an oxide film is formed on a semiconductor substrate 10 on which a lower metal wiring 11 made of an aluminum (Al) film is formed. Next, a polysilicon film 13 is deposited on the interlayer insulating film 12, and a photoresist pattern 14 is formed thereon.

도 1b를 참조하면, 포토레지스트 패턴(14)을 마스크로하여 하부의 폴리실리콘막(13)을 식각하여, 층간절연막(12)을 일부 노출시키는 비아홀 형성용 하드 마스크(13A)를 형성한다.Referring to FIG. 1B, the lower polysilicon layer 13 is etched using the photoresist pattern 14 as a mask to form a via hole forming hard mask 13A that partially exposes the interlayer insulating layer 12.

도 1c를 참조하면, 하드 마스크(13A)를 식각 마스크로하여 노출된 층간절연막(12)을 식각하여, 하부 금속배선(11)을 일부 노출시키는 비아홀(15)을 형성한 후, 공지된 방법으로 포토레지스트 패턴(12)을 제거한다. 그 다음, 도 1d에 도시된 바와 같이, 공지된 방법으로 하드 마스크(13A)를 제거한다.Referring to FIG. 1C, the exposed interlayer insulating layer 12 is etched using the hard mask 13A as an etch mask to form a via hole 15 exposing a part of the lower metal wiring 11, and then, by a known method. The photoresist pattern 12 is removed. Then, as shown in Fig. 1D, the hard mask 13A is removed by a known method.

그 후, 도시되지는 않았지만, 비아홀(15)을 통하여 하부 금속배선(11)과 콘택하는 상부 금속배선을 형성한다.Thereafter, although not shown, an upper metal wiring contacting the lower metal wiring 11 is formed through the via hole 15.

그러나, 상술한 하드 마스크(13A)를 적용한 종래의 비아홀 형성방법에 있어서는, 하드 마스크(13A)의 제거시 하부 금속배선(11)인 알루미늄막과 하드 마스크(13A)인 폴리실리콘막과의 낮은 식각 선택비에 의해, 도 1d의 도면부호 100에 도시된 바와 같이, 하부 금속배선(11)이 손상되어 배선불량 등이 야기되는 문제가 있었다.However, in the conventional via hole forming method to which the hard mask 13A is applied, the low etching of the aluminum film as the lower metal wiring 11 and the polysilicon film as the hard mask 13A when the hard mask 13A is removed. Due to the selectivity, as shown by reference numeral 100 in FIG. 1D, the lower metal wiring 11 is damaged to cause wiring defects.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 비아홀 형성시 적용되는 하드 마스크의 제거시 하부 금속배선이 노출되지 않도록 하여 하부 금속배선의 손상을 방지할 수 있는 반도체 소자의 비아홀 형성방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the problems of the prior art as described above, the via hole of the semiconductor device that can prevent the lower metal wiring from being exposed by removing the lower metal wiring when removing the hard mask applied when the via hole is formed. The purpose is to provide a formation method.

도 1a 내지 도 1d는 종래의 반도체 소자의 비아홀 형성방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views illustrating a method of forming a via hole in a conventional semiconductor device.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 단면도.2A to 2F are cross-sectional views illustrating a method of forming a via hole in a semiconductor device according to an embodiment of the present invention.

※ 도면의 주요부분에 대한 부호의 설명※ Explanation of code for main part of drawing

20 : 반도체 기판 21 : 하부 금속배선20: semiconductor substrate 21: lower metal wiring

22 : 접착막 23 : 희생막22: adhesive film 23: sacrificial film

24 : 층간절연막 25A : 하드 마스크24: interlayer insulating film 25A: hard mask

26 : 포토레지스트 패턴 27 : 비아홀26: photoresist pattern 27: via hole

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 하부 금속배선이 형성된 반도체 기판 상부에 희생막을 형성하는 단계; 희생막 상부에 층간절연막을 형성하는 단계; 층간절연막 상부에 비아홀 형성용 하드 마스크를 형성하는 단계; 하드 마스크를 식각 마스크로하여 희생막의 일부가 노출되도록 상기 층간절연막을 식각하는 단계; 하드 마스크를 제거하는 단계; 및 노출된 희생막을 제거하여 비아홀을 형성하는 단계를 포함하는 반도체 소자의 비아홀 형성방법에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, an object of the present invention is the step of forming a sacrificial film on the upper semiconductor substrate formed with a lower metal wiring; Forming an interlayer insulating film on the sacrificial film; Forming a via mask for forming via holes on the interlayer insulating film; Etching the interlayer insulating layer to expose a portion of the sacrificial layer by using a hard mask as an etching mask; Removing the hard mask; And forming a via hole by removing the exposed sacrificial layer.

바람직하게, 희생막은 하드 마스크와의 식각 선택비가 우수한 막, 더욱 바람직하게 하드 마스크가 폴리실리콘막인 경우 질화막으로 형성한다. 또한, 하부 금속배선은 알루미늄막으로 이루어지고, 하부 금속배선과 희생막 사이에 TiN막 또는 Ti/TiN막으로 이루어진 접착막을 개재한다.Preferably, the sacrificial film is formed of a film having an excellent etching selectivity with respect to the hard mask, more preferably a nitride film when the hard mask is a polysilicon film. In addition, the lower metal wiring is made of an aluminum film, and interposes an adhesive film made of a TiN film or a Ti / TiN film between the lower metal wiring and the sacrificial film.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체 소자의 비아홀 형성방법을 설명하기 위한 단면도이다.2A through 2F are cross-sectional views illustrating a method of forming a via hole in a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 알루미늄(Al)막으로 이루어진 하부 금속배선(21)이 형성된 반도체 기판(20) 상부에, 이후 형성되는 폴리실리콘막으로 이루어진 하드 마스크와의 식각 선택비가 우수한 절연막, 바람직하게 질화막으로 희생막(23)을 형성한다. 이때, 희생막(23)인 질화막과 하부 금속배선(21) 사이에 이들 사이의 접착력을 향상시키기 위하여 TiN막 또는 Ti/TiN막으로 이루어진 접착막(22)을 개재한다. 그 후, 희생막(23) 상부에 산화막으로 이루어진 층간절연막(24)을 형성하고, 그 상부에 폴리실리콘막(25)을 증착한 다음, 폴리실리콘막(25) 상부에 포토레지스트 패턴(26)을 형성한다.Referring to FIG. 2A, an insulating film having an excellent etching selectivity with a hard mask made of a polysilicon film formed on the semiconductor substrate 20 on which the lower metal wiring 21 made of aluminum (Al) film is formed, preferably a nitride film The sacrificial film 23 is formed. In this case, in order to improve the adhesion between the sacrificial film 23, the nitride film and the lower metal wiring 21, an adhesive film 22 made of a TiN film or a Ti / TiN film is interposed therebetween. Thereafter, an interlayer insulating film 24 made of an oxide film is formed on the sacrificial film 23, a polysilicon film 25 is deposited on the sacrificial film 23, and then the photoresist pattern 26 is formed on the polysilicon film 25. To form.

도 2b를 참조하면, 포토레지스트 패턴(26)을 마스크로하여 하부의 폴리실리콘막(25)을 식각하여, 층간절연막(24)을 일부 노출시키는 비아홀 형성용 하드 마스크(25A)를 형성한다.Referring to FIG. 2B, the lower polysilicon layer 25 is etched using the photoresist pattern 26 as a mask to form a via hole forming hard mask 25A that partially exposes the interlayer insulating layer 24.

도 2c를 참조하면, 하드 마스크(25A)를 식각 마스크로하여 노출된 층간절연막(24)을 하부의 희생막(23)이 노출되도록 식각한다.Referring to FIG. 2C, the exposed interlayer insulating layer 24 is etched using the hard mask 25A as an etching mask to expose the lower sacrificial layer 23.

도 2d를 참조하면, 공지된 방법으로 포토레지스트 패턴(26)을 제거한 후, 잔여 포토레지스트와 폴리머 등을 제거하기 위하여 제 1 세정공정을 실시한다.Referring to FIG. 2D, after removing the photoresist pattern 26 by a known method, a first cleaning process is performed to remove residual photoresist, polymer, and the like.

도 2e를 참조하면, 공지된 방법으로 하드 마스크(25A)를 제거한다. 이때, 폴리실리콘막으로 이루어진 하드 마스크(25A)와 질화막으로 이루어진 희생막(23)과의 우수한 식각 선택비에 의해 하부 금속배선(21)과 같은 하부막들의 손상없이 하드 마스크(25A)만이 제거된다.Referring to FIG. 2E, the hard mask 25A is removed in a known manner. At this time, only the hard mask 25A is removed without damaging the lower layers such as the lower metal interconnection 21 by the excellent etching selectivity between the hard mask 25A made of the polysilicon film and the sacrificial film 23 made of the nitride film. .

도 2f를 참조하면, 노출된 희생막(23)을 제거하여 접착막(22)의 표면을 노출시킴으로써 비아홀(27)을 형성한다. 그 후, 제 2 세정공정을 실시한 다음, 도시되지는 않았지만, 비아홀(27)을 통하여 하부 금속배선(21)과 콘택하는 상부 금속배선을 형성한다.Referring to FIG. 2F, the via hole 27 is formed by removing the exposed sacrificial layer 23 to expose the surface of the adhesive layer 22. Thereafter, after performing the second cleaning process, an upper metal wiring contacting the lower metal wiring 21 is formed through the via hole 27, although not shown.

상기 실시예에 의하면, 하부 금속배선(21)을 덮고 있는 희생막(23)에 의해 하드 마스크(25A)의 제거시 하부 금속배선(21)의 손상이 방지된다.According to the above embodiment, the sacrificial film 23 covering the lower metal wiring 21 prevents damage to the lower metal wiring 21 when the hard mask 25A is removed.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

전술한 본 발명은 하드 마스크를 적용하여 비아홀을 형성하는 반도체 소자의 제조시 발생되는 하부 금속배선의 손상을 효과적으로 방지하여, 종래와 같은 배선불량 등의 문제를 해결함으로써, 반도체 소자의 신뢰성을 향상시킬 수 있는 효과를 얻을 수 있다.The present invention described above effectively prevents damage to the lower metal wirings generated during fabrication of a semiconductor device forming a via hole by applying a hard mask, thereby improving reliability of the semiconductor device by solving problems such as conventional wiring defects. The effect can be obtained.

Claims (8)

하부 금속배선이 형성된 반도체 기판 상부에 희생막을 형성하는 단계;Forming a sacrificial layer on the semiconductor substrate on which the lower metal wiring is formed; 상기 희생막 상부에 층간절연막을 형성하는 단계;Forming an interlayer insulating layer on the sacrificial layer; 상기 층간절연막 상부에 비아홀 형성용 하드 마스크를 형성하는 단계;Forming a hard mask for forming a via hole on the interlayer insulating layer; 상기 하드 마스크를 식각 마스크로하여 상기 희생막의 일부가 노출되도록 상기 층간절연막을 식각하는 단계;Etching the interlayer insulating layer to expose a portion of the sacrificial layer by using the hard mask as an etching mask; 상기 하드 마스크를 제거하는 단계; 및Removing the hard mask; And 상기 노출된 희생막을 제거하여 비아홀을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 비아홀 형성방법.And forming a via hole by removing the exposed sacrificial layer. 제 1 항에 있어서,The method of claim 1, 상기 희생막은 상기 하드 마스크와의 식각 선택비가 우수한 막으로 형성하는 것을 특징으로 하는 반도체 소자의 비아홀 형성방법.And the sacrificial layer is formed of a film having an excellent etch selectivity with respect to the hard mask. 제 2 항에 있어서,The method of claim 2, 상기 하드 마스크는 폴리실리콘막으로 형성하는 것을 특징으로 하는 반도체 소자의 비아홀 형성방법.The hard mask is formed of a polysilicon film, the via hole forming method of a semiconductor device. 제 3 항에 있어서,The method of claim 3, wherein 상기 희생막은 질화막으로 형성하는 것을 특징으로 하는 반도체 소자의 비아홀 형성방법.And the sacrificial layer is formed of a nitride layer. 제 1 항에 있어서,The method of claim 1, 상기 하부 금속배선은 알루미늄막으로 형성하는 것을 특징으로 하는 반도체 소자의 비아홀 형성방법.The lower metal wiring is formed of an aluminum film, the via hole forming method of a semiconductor device. 제 1 항에 있어서,The method of claim 1, 상기 하부 금속배선과 상기 희생막 사이에 접착막을 개재하는 것을 특징으로 하는 반도체 소자의 비아홀 형성방법.And forming an adhesive layer between the lower metal interconnection and the sacrificial layer. 제 6 항에 있어서,The method of claim 6, 상기 접착막은 TiN막 또는 Ti/TiN막으로 이루어진 것을 특징으로 하는 반도체 소자의 비아홀 형성방법.The adhesive film is a via hole forming method of a semiconductor device, characterized in that consisting of a TiN film or Ti / TiN film. 제 1 항에 있어서,The method of claim 1, 상기 비아홀이 형성된 기판을 세정하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 비아홀 형성방법.And cleaning the substrate on which the via hole is formed.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7307014B2 (en) 2004-07-05 2007-12-11 Samsung Electronics Co., Ltd. Method of forming a via contact structure using a dual damascene process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7307014B2 (en) 2004-07-05 2007-12-11 Samsung Electronics Co., Ltd. Method of forming a via contact structure using a dual damascene process

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