KR20050034029A - Method for forming metal line of semiconductor device - Google Patents
Method for forming metal line of semiconductor device Download PDFInfo
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- KR20050034029A KR20050034029A KR1020030069810A KR20030069810A KR20050034029A KR 20050034029 A KR20050034029 A KR 20050034029A KR 1020030069810 A KR1020030069810 A KR 1020030069810A KR 20030069810 A KR20030069810 A KR 20030069810A KR 20050034029 A KR20050034029 A KR 20050034029A
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- insulating oxide
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 title abstract description 25
- 239000002184 metal Substances 0.000 title abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 35
- 150000004767 nitrides Chemical class 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000003667 anti-reflective effect Effects 0.000 claims description 5
- 238000000059 patterning Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
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- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 금속배선 형성방법을 개시한다. 개시된 발명 은 반도체기판상에 형성된 제1절연산화막내에 플러그콘택홀을 형성하는 단계; 상기 플러그콘택홀을 포함한 제1절연산화막내에 상면에 심(seam)이 형성된 콘택플러그를 형성하는 단계; 상기 콘택플러그를 포함한 제1절연산화막상에 식각정지용 질화막과 제2절연산화막을 순차적으로 형성하는 단계; 상기 제2절연산화막을 선택적으로 제거 하여 배선콘택홀을 형성하는 단계; 상기 배선콘택홀 아래에 노출된 식각정지용 질화막부분을 등방성식각에 의해 제거하는 단계; 상기 배선콘택홀내에 상기 콘택플러그와 전기적으로 연결되는 도전층배선을 형성하는 단계를 포함하여 구성되며, 드레인 폴리플러그에 V자 형태로 심(seam) 존재시에 후속 다마신 구조의 라인 패터닝 공정에서 상부산화막의 손실없이 식각정지막을 제거할 수 있는 것이다. The present invention discloses a method for forming metal wiring of a semiconductor device. The disclosed invention includes forming a plug contact hole in a first insulating oxide film formed on a semiconductor substrate; Forming a contact plug having a seam formed on an upper surface of the first insulating oxide layer including the plug contact hole; Sequentially forming an etch stop nitride film and a second insulating oxide film on the first insulating oxide film including the contact plug; Selectively removing the second insulating oxide layer to form a wiring contact hole; Removing the etch stop nitride film portion exposed under the wiring contact hole by isotropic etching; And forming a conductive layer wiring electrically connected to the contact plug in the wiring contact hole, and in a subsequent patterning process of a damascene structure when a V-shaped seam is present in the drain polyplug. The etch stop layer can be removed without losing the upper oxide layer.
Description
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로서, 보다 상세하게는 드레인 폴리플러그위에 다마신 구조의 메탈라인을 형성하는 반도체소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and more particularly, to a method for forming metal wiring in a semiconductor device in which metal lines having a damascene structure are formed on a drain poly plug.
종래기술에 따른 반도체소자의 금속배선 형성방법에 대해 도 1 및 도 2를 참조하여 설명하면 다음과 같다.A method of forming metal wirings of a semiconductor device according to the related art will be described with reference to FIGS. 1 and 2 as follows.
도 1은 종래기술에 따른 반도체소자의 금속배선 형성방법을 설명하기 위한 공정단면도이고, 도 2는 종래기술에 따른 반도체소자의 금속배선 평면도이다. 1 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to the prior art, and FIG. 2 is a plan view of a metal wiring of a semiconductor device according to the prior art.
종래기술에 따른 금속배선 형성방법은, 도 1a에 도시된 바와같이, 반도체기판(1)상에 패드질화막(미도시)을 형성한후 패드질화막(미도시)과 반도체기판(1)을 선택적으로 제거하여 소자분리막을 형성하기 위해 트렌치(미도시)을 형성한다.In the method of forming a metal wiring according to the related art, as shown in FIG. 1A, after forming a pad nitride film (not shown) on the semiconductor substrate 1, the pad nitride film (not shown) and the semiconductor substrate 1 are selectively formed. A trench (not shown) is formed to remove to form an isolation layer.
그다음, 상기 트렌치(미도시)내에 소자분리막용 산화막을 증착한후 이를 선택적으로 제거하여 소자분리막(3)을 형성한다음 상기 패드질화막(미도시)을 제거한다.Then, an oxide film for device isolation film is deposited in the trench (not shown) and then selectively removed to form the device isolation film 3, and then the pad nitride film (not shown) is removed.
이어서, 상기 소자분리막(3)을 포함한 반도체기판(1)상에 식각방지용 질화막(5)을 증착한후 그 위에 제1절연산화막(7)을 두껍게 증착한다.Subsequently, an etch-resistant nitride film 5 is deposited on the semiconductor substrate 1 including the device isolation film 3, and then a thick first insulating oxide film 7 is deposited thereon.
그다음, 상기 제1절연산화막(7)과 식각방지용 질화막(5)을 순차적으로 제거하여 상기 반도체기판(1)의 일부분을 노출시키는 플러그콘택홀(9)을 형성한다. Thereafter, the first insulating oxide film 7 and the etching preventing nitride film 5 are sequentially removed to form a plug contact hole 9 exposing a portion of the semiconductor substrate 1.
이어서, 도 1b에 도시된 바와같이, 상기 플러그콘택홀(9)을 포함한 제1절연산화막(7)상에 도전층으로 폴리실리콘층(11)을 증착하여 상기 플러그콘택홀(9)을 매립한다.Subsequently, as shown in FIG. 1B, the polysilicon layer 11 is deposited as a conductive layer on the first insulating oxide film 7 including the plug contact hole 9 to fill the plug contact hole 9. .
그다음, 도 1c에 도시된 바와같이, 전면식각공정을 통해 상기 폴리실리콘층(11)을 상기 제1절연산화막(7)표면이 드러날 때까지 선택적으로 제거하여 상기 플러그콘택홀(9)내에 폴리플러그(11a)를 형성한다. 이때, 상기 전면식각된 폴리플러그(11a)상부표면에 "V"자 형태의 심(seam)(A)이 형성된다.Then, as illustrated in FIG. 1C, the polysilicon layer 11 is selectively removed through a front surface etching process until the surface of the first insulating oxide film 7 is exposed, thereby removing the poly plug in the plug contact hole 9. (11a) is formed. At this time, a seam A having a “V” shape is formed on an upper surface of the front etched polyplug 11a.
이어서, 도 1d에 도시된 바와같이, 상기 전면식각된 폴리플러그(11a)를 포함한 전체 구조의 상면에 식각정지용 질화막(13)을 증착한후 상기 식각정지용 질화막(13)상에 제2절연산화막(15)을 증착한다.Subsequently, as illustrated in FIG. 1D, an etch stop nitride film 13 is deposited on the top surface of the entire structure including the front etched polyplug 11a, and then a second insulating oxide layer 13 is formed on the etch stop nitride film 13. 15) Deposit.
그다음, 도 1e에 도시된 바와같이, 상기 제2절연산화막(15)상에 난반사방지 유기막(17)과 레지스트막(미도시)을 차례로 형성한후 라인을 패터닝하기 위해 상기 레지스트막(미도시)을 포토리소그라피공정기술에 의한 노광 및 현상공정을 거쳐 선택적으로 패터닝하여 레지스트막패턴(19)을 형성한다.Next, as shown in FIG. 1E, after forming an anti-reflective organic film 17 and a resist film (not shown) on the second insulating oxide film 15 in sequence, the resist film (not shown) is used to pattern lines. ) Is selectively patterned through an exposure and development process using a photolithography process technology to form a resist film pattern 19.
이어서, 도 1f에 도시된 바와같이, 상기 레지스트막패턴(19)을 마스크로 상기 난반사 방지 유기막(17)과 제2절연산화막(15)을 순차적으로 제거하여 배선콘택홀(21)을 형성한다.Subsequently, as shown in FIG. 1F, the diffuse reflection prevention organic film 17 and the second insulating oxide film 15 are sequentially removed using the resist film pattern 19 as a mask to form a wiring contact hole 21. .
그다음, 도 1g에 도시된 바와 같이, 상기 배선콘택홀(21)아래에 있는 식각정지용 질화막(3)부분을 비등방성 식각공정(23)을 통해 제거하여 상기 폴리플러그 (11a)의 상면을 노출시킨다. 이때, 비등방성 식각공정시에 상기 배선콘택홀(21) 주위의 레지스트막패턴(19)의 일부분과 함께 제2절연산화막(즉, 산화막)의 일부분이 제거된다.Next, as shown in FIG. 1G, the etch stop nitride film 3 under the wiring contact hole 21 is removed through an anisotropic etching process 23 to expose the top surface of the polyplug 11a. . At this time, during the anisotropic etching process, a part of the second insulating oxide film (ie, an oxide film) is removed together with a part of the resist film pattern 19 around the wiring contact hole 21.
이어서, 도 1h에 도시된 바와같이, 상기 잔류하는 레지스트막패턴(49)과 난반사 방지유기막(47)을 제거한다.Subsequently, as shown in FIG. 1H, the remaining resist film pattern 49 and the diffuse reflection preventing organic film 47 are removed.
그다음, 도 1i에 도시된 바와같이, 상기 배선콘택홀(21)을 포함한 전체 구조의 상면에 메탈라인을 형성하기 위한 도전층(25)을 증착하여 상기 배선콘택홀(21)을 매립한다.Next, as shown in FIG. 1I, a conductive layer 25 for forming a metal line is deposited on the upper surface of the entire structure including the wiring contact hole 21 to fill the wiring contact hole 21.
이어서, 도 1j에 도시된 바와같이, 상기 도전층(25)을 CMP하여 도전층패턴(25a)을 형성한다. 이때, 상기 CMP 공정은 상기 제2절연산화막(15)상면이 드러나는 시점까지 진행한다. Subsequently, as illustrated in FIG. 1J, the conductive layer 25 is CMP to form a conductive layer pattern 25a. In this case, the CMP process proceeds to a point where the top surface of the second insulating oxide film 15 is exposed.
또한, 도 2에 따르면, 상기 제조공정을 통해 얻어진 종래기술에 따른 다수의 도전층패턴(25a)들이 브릿지되어 있는 것을 보여 준다.In addition, according to Figure 2, it shows that a plurality of conductive layer patterns 25a according to the prior art obtained through the manufacturing process is bridged.
상기 종래기술에 의하면, 드레인 폴리플러그 형성시에 CMP대신 전면식각방법을 사용하면 "V"자 형태의 심(seam)이 형성되기 때문에 후속 다마신 구조에서 라인패턴 식각시에 문제가 있었다.According to the related art, when the front etching method is used instead of the CMP when the drain polyplug is formed, a “V” shaped seam is formed, which causes a problem in the subsequent pattern etching of the damascene structure.
그 문제는 디자인 룰이 축소됨에 따라 라인 패터닝을 위한 포토레지스트의 두께를 낮춰야 하고 그럴 경우 식각시 포토레지스트에 대한 선택비가 높지 않은 상태에서 식각할 수 있는 양은 한정되어 있다.The problem is that as the design rule shrinks, the thickness of the photoresist for line patterning needs to be reduced, and in this case, the amount that can be etched in a state where the selectivity to the photoresist is not high during etching is limited.
그래서, "V"자 형태의 심(seam) 구조에서 라인과 드레인 폴리플러그를 전기적으로 연결하기 위해 식각양을 늘릴 경우, 도 1g에서와 같이, 라인패턴의 상부부분이 포토레지스트 손상에 의해 산화막의 손실을 발생시킬 수 있고 식각 양을 줄일 경우 심(seam) 부분에 잔류물이 남아 콘택 저항에 문제를 일으킬 수 있다.Thus, when the etching amount is increased to electrically connect the line and the drain polyplug in the “V” shaped seam structure, as shown in FIG. 1G, the upper portion of the line pattern may be damaged by photoresist damage. Losses can occur, and if the amount of etching is reduced, residues in the seam can cause problems in contact resistance.
또한, 이렇게 레지스트손상에 의해 산화막의 손실이 발생되므로 인해 라인패턴의 형성시에 도 2에서와 같이 라인패턴이 브릿지되는 현상이 발생하게 된다.In addition, since the loss of the oxide film is caused by the damage of the resist, the phenomenon of the line pattern is bridged as shown in FIG. 2 when the line pattern is formed.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 드레인 폴리플러그에 V자 형태로 심(seam) 존재시에 후속 다마신 구조의 라인 패터닝 공정에서 상부산화막의 손실없이 식각정지막을 제거할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, the etch stop film in the line patterning process of the subsequent damascene structure in the presence of a seam in the V-shaped drain polyplug without loss of the upper oxide film It is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device that can be removed.
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 형성방법은, 반도체기판상에 형성된 제1절연산화막내에 플러그콘택홀을 형성하는 단계;According to another aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method including: forming a plug contact hole in a first insulating oxide film formed on a semiconductor substrate;
상기 플러그콘택홀을 포함한 제1절연산화막내에 상면에 심(seam)이 형성된 콘택플러그를 형성하는 단계;Forming a contact plug having a seam formed on an upper surface of the first insulating oxide layer including the plug contact hole;
상기 콘택플러그를 포함한 제1절연산화막상에 식각정지용 질화막과 제2절연산화막을 순차적으로 형성하는 단계;Sequentially forming an etch stop nitride film and a second insulating oxide film on the first insulating oxide film including the contact plug;
상기 제2절연산화막을 선택적으로 제거하여 배선콘택홀을 형성하는 단계;Selectively removing the second insulating oxide layer to form a wiring contact hole;
상기 배선콘택홀아래에 노출된 식각정지용 질화막부분을 등방성식각에 의해 제거하는 단계;Removing an etch stop nitride film portion exposed under the wiring contact hole by isotropic etching;
상기 배선콘택홀내에 상기 콘택플러그와 전기적으로 연결되는 도전층배선을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.And forming a conductive layer wiring electrically connected to the contact plug in the wiring contact hole.
(실시예)(Example)
이하, 본 발명에 따른 반도체소자의 금속배선 형성방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of forming metal wirings of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3j는 본 발명에 따른 반도체소자의 금속배선 형성방법을 설명하기 위한 공정단면도이다.3A to 3J are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the present invention.
도 4는 본 발명에 따른 반도체소자의 금속배선의 평면도이다.4 is a plan view of a metal wiring of a semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 금속배선 형성방법은, 도 3a에 도시된 바와같이, 반도체기판(31)상에 패드질화막(미도시)을 형성한후 패드질화막(미도시)과 반도체기판(31)을 선택적으로 제거하여 소자분리막을 형성하기 위해 트렌치(미도시)을 형성한다.In the method for forming metal wirings of a semiconductor device according to the present invention, as shown in FIG. 3A, after forming a pad nitride film (not shown) on the semiconductor substrate 31, the pad nitride film (not shown) and the semiconductor substrate 31 are formed. Is selectively removed to form a trench (not shown) to form an isolation layer.
그다음, 상기 트렌치(미도시)내에 소자분리막용 산화막을 증착한후 이를 선택적으로 제거하여 소자분리막(33)을 형성한다음 상기 패드질화막(미도시)을 제거한다.Then, an oxide film for device isolation film is deposited in the trench (not shown) and then selectively removed to form the device isolation film 33, and then the pad nitride film (not shown) is removed.
이어서, 상기 소자분리막(33)을 포함한 반도체기판(31)상에 식각방지용 질화막(35)을 증착한후 그 위에 제1절연산화막(37)을 두껍게 증착한다.Subsequently, an etch-resistant nitride film 35 is deposited on the semiconductor substrate 31 including the device isolation layer 33, and then a thick first insulating oxide layer 37 is deposited thereon.
그다음, 상기 제1절연산화막(37)과 식각방지용 질화막(35)을 순차적으로 제거하여 상기 반도체기판(31)의 일부분을 노출시키는 플러그콘택홀(39)를 형성한다. 이때, 플러그콘택홀(39)의 크기는 약 110∼170 nm 범위를 가지며, 플러그콘택홀의 깊이는 8000∼12000Å 범위를 가진다. Thereafter, the first insulating oxide layer 37 and the etching preventing nitride layer 35 are sequentially removed to form a plug contact hole 39 exposing a portion of the semiconductor substrate 31. At this time, the size of the plug contact hole 39 is in the range of about 110 to 170 nm, and the depth of the plug contact hole is in the range of 8000 to 12000 Å.
이어서, 도 3b에 도시된 바와같이, 상기 플러그콘택홀(39)을 포함한 제1절연산화막(37)상에 폴리실리콘층(41)을 증착하여 상기 플러그콘택홀(39)을 매립한다.Next, as shown in FIG. 3B, the polysilicon layer 41 is deposited on the first insulating oxide layer 37 including the plug contact hole 39 to fill the plug contact hole 39.
그다음, 도 3c에 도시된 바와같이, 전면식각공정을 통해 상기 폴리실리콘층 (41)을 상기 제1절연산화막(37)표면이 드러날 때까지 선택적으로 제거하여 상기 플러그콘택홀(39)내에 폴리플러그(41a)를 형성한다. 이때, 상기 전면식각된 폴리플러그(41a)상부표면에 "V"자 형태의 심(seam)(A)이 형성된다. 또한, 상기 심(seam) (A)의 깊이는 50∼100 nm 범위인 갖는다.3C, the polysilicon layer 41 is selectively removed through a front surface etching process until the surface of the first insulating oxide layer 37 is exposed, thereby removing the polyplug in the plug contact hole 39. It forms 41a. In this case, a seam A having a “V” shape is formed on an upper surface of the front etched polyplug 41a. In addition, the depth of the seam (A) has a range of 50 to 100 nm.
이어서, 도 3d에 도시된 바와같이, 상기 전면식각된 폴리플러그(41a)를 포함한 전체 구조의 상면에 식각정지용 질화막(43)을 증착한후 상기 식각정지용 질화막(43)상에 제2절연산화막(45)을 증착한다. 이때, 상기 식각정지용 질화막(43)의 두께는 300∼700Å 범위를 가지며, 제2절연산화막(45)의 두께는 2500∼4000Å 범위를 가진다.Subsequently, as illustrated in FIG. 3D, an etch stop nitride film 43 is deposited on the top surface of the entire structure including the front etched polyplug 41a, and then a second insulating oxide layer 43 is formed on the etch stop nitride film 43. 45). In this case, the thickness of the etch stop nitride film 43 is in the range of 300 to 700 kPa, and the thickness of the second insulating oxide film 45 is in the range of 2500 to 4000 kPa.
그다음, 도 3e에 도시된 바와같이, 상기 제2절연산화막(45)상에 난반사방지 유기막(47)과 레지스트막(미도시)을 차례로 형성한후 라인을 패터닝하기 위해 상기 레지스트막(미도시)을 포토리소그라피공정기술에 의한 노광 및 현상공정을 거쳐 선택적으로 패터닝하여 레지스트막패턴(49)을 형성한다. 이때, 상기 난반사방지 유기막(47)의 두께는 400∼800Å 범위를 가지며, 레지스트막은 약 3000∼5000Å 두께로 도포한다.Next, as shown in FIG. 3E, after forming an anti-reflective organic film 47 and a resist film (not shown) on the second insulating oxide film 45, the resist film (not shown) is used to pattern lines. ) Is selectively patterned through an exposure and development process using a photolithography process technology to form a resist film pattern 49. At this time, the anti-reflective organic film 47 has a thickness in the range of 400 to 800 kPa, and the resist film is applied at a thickness of about 3000 to 5000 kPa.
이어서, 도 3f에 도시된 바와같이, 상기 레지스트막패턴(39)을 마스크로 상기 난반사 방지 유기막(47)과 제2절연산화막(45)을 순차적으로 제거하여 배선콘택홀(51)을 형성한다. 이때, 난반사 방지유기막 식각시에 산화막과의 식각선택비가 1:1∼1:2 이다. 또한, 제2절연산화막(45) 식각후 남아 있는 식각정지용 질화막(43)의 두께는 100∼300Å이다. 그리고, 상기 식각정지용 질화막의 식각타겟은 남은 식각정지용 질화막께의 50∼100%가 되게 한다. Subsequently, as shown in FIG. 3F, the diffuse reflection prevention organic film 47 and the second insulating oxide film 45 are sequentially removed using the resist film pattern 39 as a mask to form a wiring contact hole 51. . At this time, the etching selectivity with the oxide film during the anti-reflective organic film etching is 1: 1 to 1: 2. In addition, the thickness of the etch stop nitride film 43 remaining after etching the second insulating oxide film 45 is 100 to 300 kPa. Then, the etching target of the etch stop nitride film is 50 to 100% of the remaining etch stop nitride film.
그다음, 도 3g에 도시된 바와 같이, 상기 배선콘택홀(51)아래에 있는 식각정지용 질화막(43)부분을 등방성 식각공정(53)을 통해 제거하여 상기 폴리플러그 (41a)의 상면을 노출시킨다. 이때, 상기 식각정지용 질화막 식각후 제1절연산화막의 손실두께는 300∼800Å정도이다.Next, as shown in FIG. 3G, the portion of the nitride film 43 for etching stop under the wiring contact hole 51 is removed through an isotropic etching process 53 to expose the top surface of the polyplug 41a. At this time, the loss thickness of the first insulating oxide film after etching the nitride film for etching stop is about 300 ~ 800Å.
이어서, 도 3h에 도시된 바와같이, 상기 잔류하는 레지스트막(49)과 난반사 방지유기막(47)을 제거한다. Subsequently, as shown in FIG. 3H, the remaining resist film 49 and diffuse reflection preventing organic film 47 are removed.
그다음, 도 3i에 도시된 바와같이, 상기 배선콘택홀(51)을 포함한 전체 구조의 상면에 메탈라인을 형성하기 위한 도전층(55)을 증착하여 상기 배선콘택홀(51)을 매립한다. 이때, 상기 도전층(55) 물질로는 텅스텐이나 알루미늄 등을 사용한다.Next, as shown in FIG. 3I, a conductive layer 55 for forming a metal line is deposited on the upper surface of the entire structure including the wiring contact hole 51 to fill the wiring contact hole 51. In this case, tungsten, aluminum, or the like is used as the conductive layer 55 material.
이어서, 도 3j에 도시된 바와같이, 상기 도전층(55)을 CMP하여 금속패턴 (55a)을 형성한다. 이때, 상기 CMP 공정은 상기 제2절연산화막(45)상면이 드러나는 시점까지 진행한다.Subsequently, as illustrated in FIG. 3J, the conductive layer 55 is CMP to form a metal pattern 55a. In this case, the CMP process is performed until the upper surface of the second insulating oxide film 45 is exposed.
상기 구성을 통해 얻어진 본 발명에 따른 다마신 라인패턴에 대한 평면도가 도 4에 도시되어 있는데, 기존의 방법(도 2 참조)을 통해 얻어진 금속배선에서 나타난 브릿지 현상이 발생하지 않음을 알 수 있다.A plan view of the damascene line pattern according to the present invention obtained through the above configuration is shown in FIG. 4, but it can be seen that the bridge phenomenon shown in the metal wiring obtained through the existing method (see FIG. 2) does not occur.
상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 다마신 라인패턴 형성방법에 의하면, 기존의 다마신 구조의 라인패턴 식각시에 산화막 식각후 하부의 식각 정지용 질화막 제거시 등방성 식각 특성을 이용하여 식각양을 감소시킬 수 있어 포토레지스트의 손상을 방지할 수 있고, 산화막으로 이루어진 라인패턴의 상부분의 손상을 방지할 수 있어 메탈라인과의 누설전류를 방지할 수 있어서 소자 제조시에 수율을 향상시킬 수 있다.As described above, according to the method for forming a damascene line pattern of a semiconductor device according to the present invention, an etching method is performed by using an isotropic etching characteristic when removing the nitride layer for etching stop of the lower part after etching the oxide layer during the etching of the line pattern of the conventional damascene structure. It is possible to reduce the amount of the photoresist to prevent damage to the photoresist, to prevent damage to the upper portion of the line pattern formed of the oxide film, and to prevent leakage current with the metal line, thereby improving the yield during device manufacturing. Can be.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
도 1은 종래기술에 따른 반도체소자의 금속배선 형성방법을 설명하기 위한 공정단면도,1 is a cross-sectional view illustrating a method for forming a metal wiring of a semiconductor device according to the prior art;
도 2는 종래기술에 따른 반도체소자의 금속배선 평면도,2 is a plan view of a metal wiring of a semiconductor device according to the prior art;
도 3a 내지 도 3j는 본 발명에 따른 반도체소자의 금속배선 형성방법을 설명하기 위한 공정단면도,3A to 3J are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the present invention;
도 4는 본 발명에 따른 반도체소자의 금속배선의 평면도.4 is a plan view of a metal wiring of a semiconductor device according to the present invention.
[도면부호의설명][Description of Drawing Reference]
31 : 반도체기판 33 : 소자분리막31: semiconductor substrate 33: device isolation film
35 : 식각방지질화막 37 : 제1절연산화막35 etch-resistant nitride film 37 first insulating oxide film
39 : 플러그콘택홀 41 : 폴리실리콘층39: plug contact hole 41: polysilicon layer
41a : 콘택플러그 43 : 식각정지용 질화막41a: contact plug 43: nitride film for etching stop
45 : 제2절연산화막 47 : 난반사 방지유기막45: second insulating oxide film 47: diffuse reflection organic film
49 : 레지스트막패턴 51 : 배선콘택홀49: resist film pattern 51: wiring contact hole
53 : 등방성 식각 55 : 도전층53: Isotropic Etching 55: Conductive Layer
55a : 금속배선55a: metal wiring
Claims (10)
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| KR1020030069810A KR20050034029A (en) | 2003-10-08 | 2003-10-08 | Method for forming metal line of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020030069810A KR20050034029A (en) | 2003-10-08 | 2003-10-08 | Method for forming metal line of semiconductor device |
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| KR20050034029A true KR20050034029A (en) | 2005-04-14 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007096324A (en) * | 2005-09-28 | 2007-04-12 | Samsung Electronics Co Ltd | Method of forming metal wiring structure |
| KR100735518B1 (en) * | 2005-09-28 | 2007-07-04 | 삼성전자주식회사 | Methods of forming a metal interconnect structure |
-
2003
- 2003-10-08 KR KR1020030069810A patent/KR20050034029A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007096324A (en) * | 2005-09-28 | 2007-04-12 | Samsung Electronics Co Ltd | Method of forming metal wiring structure |
| KR100735518B1 (en) * | 2005-09-28 | 2007-07-04 | 삼성전자주식회사 | Methods of forming a metal interconnect structure |
| US7435673B2 (en) | 2005-09-28 | 2008-10-14 | Samsung Electronics Co., Ltd. | Methods of forming integrated circuit devices having metal interconnect structures therein |
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