KR100358569B1 - A method for forming a metal line of semiconductor device - Google Patents

A method for forming a metal line of semiconductor device Download PDF

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KR100358569B1
KR100358569B1 KR1019990064091A KR19990064091A KR100358569B1 KR 100358569 B1 KR100358569 B1 KR 100358569B1 KR 1019990064091 A KR1019990064091 A KR 1019990064091A KR 19990064091 A KR19990064091 A KR 19990064091A KR 100358569 B1 KR100358569 B1 KR 100358569B1
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South Korea
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metal wiring
forming
contact plug
metal
etch stop
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KR1019990064091A
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Korean (ko)
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KR20010061595A (en
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권세한
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Abstract

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로,The present invention relates to a method for forming metal wiring of a semiconductor device,

반도체기판 상부에 제1금속배선 물질인 제1알루미늄막을 형성하고 상기 제1금속배선 물질 상부에 식각방지막을 형성한 다음, 상기 식각방지막을 제1금속배선 마스크를 이용하여 패터닝하고 전체표면상부에 금속배선 콘택플러그 물질인 제2알루미늄막을 형성한 다음, 상기 금속배선 콘택플러그 물질 상부에 감광막패턴을 형성하고 상기 감광막패턴과 식각방지막을 이용한 식각공정으로 상기 금속배선 콘택플러그 물질과 제1금속배선 물질을 식각하여 콘택플러그 및 제1금속배선을 형성한 다음, 상기 감광막패턴을 제거하고, 상기 콘택플러그의 상부면을 노출시키는 평탄화된 층간절연막을 형성한 다음, 상기 콘택플러그에 접속되는 제2금속배선을 형성하고 상기 제2금속배선 상부를 포함한 전체표면상부에 보호막을 형성함으로써 안정된 공정으로 금속배선을 형성하여 반도체소자의 생산성을 향상시킬 수 있는 기술이다.A first aluminum layer, the first metal interconnection material, is formed on the semiconductor substrate, and an etch stop layer is formed on the first metal interconnection material. Then, the etch stop layer is patterned using a first metal interconnection mask, and the metal is formed on the entire surface. After forming a second aluminum layer, which is a wiring contact plug material, a photoresist pattern is formed on the metal wiring contact plug material, and the metallization contact plug material and the first metal wiring material are formed by an etching process using the photoresist pattern and the etch stop layer. Etching to form a contact plug and a first metal wiring, and then removing the photoresist pattern, forming a planarized interlayer insulating film exposing the top surface of the contact plug, and then forming a second metal wiring connected to the contact plug. Gold in a stable process by forming a protective film on the entire surface including the upper portion of the second metal wiring. By forming the wiring is a technique that can improve the productivity of semiconductor devices.

Description

반도체소자의 금속배선 형성방법{A method for forming a metal line of semiconductor device}A method for forming a metal line of semiconductor device

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 특히 일반적인 듀얼 다마신 ( dual damascene ) 공정에서와 같이 금속 플러그와 금속배선을 형성시키는 방법이 아니라 금속배선과 금속 플러그를 형성시키는 방법으로 단차가 높은 경우에도 형성시킬 수 있으며, 저항이 낮은 금속으로 플러그를 형성하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and in particular, a method for forming a metal wiring and a metal plug, rather than a method for forming a metal plug and a metal wiring, as in a general dual damascene process. The present invention relates to a technique for forming a plug with a metal having low resistance, which can be formed even in a high case.

금속 인터콘넥션 ( metal interconnection ) 에서는 금속배선 사이를 콘택에 텅스텐 플러그를 형성시켜 연결하고 있다.In metal interconnection, tungsten plugs are connected between metal interconnects by forming contacts.

이때, 텅스텐의 매립과 식각이 필요하며 잔류물과 파티클에 의하여 수율이 저하되고 높은 콘택 저항을 가진다.At this time, the buried and etched tungsten is required, the yield is reduced by the residue and particles and has a high contact resistance.

또한 이런 문제를 해결하기 위하여 금속 콘택과 금속배선을 동시에 형성시키는 듀얼 다마신 공정을 이용하여 금속 콘택과 금속배선에 금속을 증착하는 방법이 있으나, 공정이 어렵고 단차가 큰 경우에는 금속 매립이 어려워 텅스텐 플러그를 사용해야 하는 단점이 있다.In order to solve this problem, there is a method of depositing a metal on the metal contact and the metal wiring by using a dual damascene process which simultaneously forms the metal contact and the metal wiring. However, when the process is difficult and the step is large, the metal is difficult to be buried. The disadvantage is the use of plugs.

도 1a 내지 도 1c 는 종래기술의 제1실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to a first embodiment of the prior art.

먼저, 반도체기판(11) 상부에 제1금속배선(13)을 형성한다. 그리고, 상기 제1금속배선(13) 상부를 평탄화시키는 층간절연막(15)을 형성한다.First, the first metal wiring 13 is formed on the semiconductor substrate 11. Then, an interlayer insulating film 15 is formed to planarize the upper portion of the first metal wiring 13.

그리고, 상기 층간절연막(15)을 CMP 공정으로 평탄화식각한다. (도 1a)The interlayer insulating film 15 is planarized by a CMP process. (FIG. 1A)

그 다음, 상기 제1금속배선(13)을 노출시키는 금속배선 콘택홀(17)을 형성한다.Next, a metal wiring contact hole 17 exposing the first metal wiring 13 is formed.

이때, 상기 금속배선 콘택홀(17)은 금속배선 마스크(도시안됨)를 이용한 사진식각공정으로 형성한다.In this case, the metal wiring contact hole 17 is formed by a photolithography process using a metal wiring mask (not shown).

그 다음, 상기 제1금속배선(13)에 접속되는 텅스텐 플러그(19)를 형성한다. 이때, 상기 텅스텐 플러그(19)는 전체표면상부에 텅스텐을 형성하고 이를 평탄화식각하여 형성한다.Next, a tungsten plug 19 connected to the first metal wiring 13 is formed. In this case, the tungsten plug 19 is formed by forming tungsten on the entire surface and flattening it.

이때, 상기 평탄화식각공정은 CMP 공정이나 에치백공정으로 실시한다.(도 1b)In this case, the planarization etching process is performed by a CMP process or an etch back process (FIG. 1B).

그 다음, 상기 텅스텐 플러그(19)에 접속되는 제2금속배선(21)을 형성한다. 이때, 상기 제1금속배선(21)은 전체표면상부에 제2금속배선 물질을 증착하고 이를 금속배선 마스크를 이용하여 사진식각함으로써 형성한다.Next, a second metal wiring 21 connected to the tungsten plug 19 is formed. In this case, the first metal wiring 21 is formed by depositing a second metal wiring material on the entire surface and etching the same using a metal wiring mask.

그리고, 상기 제2금속배선(21) 상부를 평탄화된 보호막(23)을 형성한다. (도 1c)In addition, the passivation layer 23 is formed on the upper portion of the second metal wiring 21. (FIG. 1C)

상기한 종래기술은, 텅스텐 플러그를 사용하여 저항이 높고 공정중 잔류물이나 파티클이 용이하게 형성되어 반도체소자의 수율을 저하시킨다.The above-described conventional technique uses a tungsten plug to have high resistance and to easily form residues or particles in the process, thereby lowering the yield of semiconductor devices.

도 2a 내지 도 2d 는 종래기술의 제1실시예의 문제점을 해결하기 위하여, 듀얼 다마신 방법을 이용하는 반도체소자의 금속배선 형성방법을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a metal wiring forming method of a semiconductor device using a dual damascene method in order to solve the problems of the first embodiment of the prior art.

먼저, 반도체기판(31) 상부에 제1금속배선(33)을 형성한다. 이때, 상기 제1금속배선(33)은 전체표면 상부에 제1금속배선 물질을 증착하고 이를 제1금속배선 마스크(도시안됨)를 이용한 사진식각공정으로 형성한다.First, the first metal wiring 33 is formed on the semiconductor substrate 31. In this case, the first metal wiring 33 is formed by depositing a first metal wiring material on the entire surface of the first metal wiring 33 by a photolithography process using a first metal wiring mask (not shown).

그리고, 상기 제1금속배선(33)을 상부를 CMP 방법으로 평탄화시켜 제1층간절연막(35)을 형성한다.In addition, the first interlayer insulating layer 35 is formed by planarizing the upper portion of the first metal wiring 33 by the CMP method.

그리고, 상기 제1층간절연막(35) 상부에 식각방지막(37)을 형성한다.An etch stop layer 37 is formed on the first interlayer insulating layer 35.

그리고, 제2금속배선 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 식각방지막(37)을 식각한다. (도 2a)The etch stop layer 37 is etched by a photolithography process using a second metal wiring contact mask (not shown). (FIG. 2A)

그 다음, 전체표면상부에 제2층간절연막(39)을 형성한다. (도 2b)Next, a second interlayer insulating film 39 is formed over the entire surface. (FIG. 2B)

그리고, 제2금속배선 콘택마스크(도시안됨)를 이용한 사진식각공정으로 상기 제2층간절연막(39) 및 제1층간절연막(35)을 식각하여 상기 제1금속배선(33)을 노출시키는 콘택홀(41)을 형성하는 동시에 제1금속배선(33)이 형성될 영역의 상기 제2층간절연막(39)을 식각한다.The contact hole exposing the first metal wiring 33 by etching the second interlayer insulating film 39 and the first interlayer insulating film 35 by a photolithography process using a second metal wiring contact mask (not shown). The second interlayer insulating film 39 in the region where the first metal wiring 33 is to be formed is etched at the same time as the 41 is formed.

여기서, 상기 제2금속배선 콘택마스크(도시안됨)를 이용한 사진식각공정은, 상기 식각방지막(37)로 인하여 상기 제1층간절연막(35)의 콘택영역만을 식각된다. (도 2c)In the photolithography process using the second metal wiring contact mask (not shown), only the contact region of the first interlayer insulating layer 35 is etched due to the etch stop layer 37. (FIG. 2C)

그 다음, 상기 제1금속배선(33)에 접속되는 제2금속배선 물질을 전체표면상부에 형성하고 이를 CMP 하여 제2금속배선(43)을 형성한다.Next, a second metal wiring material connected to the first metal wiring 33 is formed on the entire surface and CMP is formed to form the second metal wiring 43.

이때, 상기 제2금속배선(43) 물질의 증착공정으로 콘택홀(41)을 매립하는 제2금속배선 콘택플러그와 제2금속배선을 동시에 형성한다.In this case, the second metal wire contact plug and the second metal wire which fill the contact hole 41 are simultaneously formed by the deposition process of the material of the second metal wire 43.

그 다음, 상기 제2금속배선(43) 상부에 보호막(45)을 형성한다. (도 2d)Next, a passivation layer 45 is formed on the second metal interconnection 43. (FIG. 2D)

상기한 바와같이 종래기술의 제2실시예에 따른 반도체소자의 금속배선 형성방법은, 낮은 콘택저항을 얻을 수 있으나, 매립이 어렵고 CMP 공정이 2번이나 사용되고, 식각방지막을 이용한 패터닝공정은 높은 식각선택비가 필요하여 첨단 공정기술이 사용되어야 하여 높은 생산단가를 필요로 하는 문제점이 있다.As described above, in the method of forming a metal wiring of the semiconductor device according to the second embodiment of the prior art, a low contact resistance can be obtained, but it is difficult to bury and the CMP process is used twice, and the patterning process using an etch stop layer has a high etching rate. There is a problem in that a high cost of production is required because advanced process technology must be used because a selection cost is required.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 텅스텐과 알루미늄의 식각선택비 차이를 이용하여 콘택플러그와 제1금속배선을 형성하고 후속공정으로 제2금속배선을 형성함으로써 공정을 단순화시키고 플러그 형성공정시 잔류물 및 파티클 발생을 방지하여 반도체소자의 특성 열화를 방지하는 동시에 반도체소자의 생산성을 향상시킬 수 있는 반도체소자의 금속배선 형성방법을 제공하는데 그 목적이 있다.The present invention, in order to solve the above problems of the prior art, by using the difference in the etching selectivity of tungsten and aluminum to form a contact plug and the first metal wiring, and to form a second metal wiring in a subsequent process to simplify the process and plug It is an object of the present invention to provide a method for forming metal wirings of a semiconductor device that can prevent residues and particles from being formed during the forming process, thereby preventing deterioration of characteristics of the semiconductor device and improving productivity of the semiconductor device.

도 1a 내지 도 1c 는 종래기술의 제1실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to a first embodiment of the prior art.

도 2a 내지 도 2d 는 종래기술의 제2실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to a second embodiment of the prior art.

도 3a 내지 도 3g 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.3A to 3G are cross-sectional views illustrating a metal wiring forming method of a semiconductor device according to an embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11,31,51 : 반도체기판 13,33 : 제1금속배선11,31,51: semiconductor substrate 13,33: first metal wiring

15,62 : 층간절연막 17,41 : 금속배선 콘택홀15,62: interlayer insulating film 17,41: metal wiring contact hole

19 : 텅스텐 플러그 21,43 : 제2금속배선19: tungsten plug 21,43: second metal wiring

23,45,65 : 보호막 35 : 제1층간절연막23,45,65: protective film 35: first interlayer insulating film

37 : 식각방지막 39 : 제2층간절연막37: etching prevention film 39: second interlayer insulating film

53 : 제1알루미늄막 55 : 텅스텐막53 first aluminum film 55 tungsten film

57 : 제1감광막패턴 59 : 제2알루미늄막57: first photosensitive film pattern 59: second aluminum film

61 : 제2감광막패턴 63 : 제3알루미늄막61: second photosensitive film pattern 63: third aluminum film

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 금속배선 형성방법은,In order to achieve the above object, a metal wiring forming method of a semiconductor device according to the present invention,

반도체기판 상부에 제1금속배선 물질인 제1알루미늄막을 형성하는 공정과,Forming a first aluminum film, which is a first metal wiring material, on the semiconductor substrate;

상기 제1금속배선 물질 상부에 식각방지막을 형성하는 공정과,Forming an etch stop layer on the first metal wiring material;

상기 식각방지막을 제1금속배선 마스크를 이용하여 패터닝하는 공정과,Patterning the etch stop layer using a first metal wiring mask;

전체표면상부에 금속배선 콘택플러그 물질인 제2알루미늄막을 형성하는 공정과,Forming a second aluminum film of a metallization contact plug material on the entire surface thereof;

상기 금속배선 콘택플러그 물질 상부에 금속배선 콘택마스크를 이용하여 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the metallization contact plug material using a metallization contact mask;

상기 감광막패턴과 식각방지막을 이용한 식각공정으로 상기 금속배선 콘택플러그 물질과 제1금속배선 물질을 식각하여 콘택플러그 및 제1금속배선을 형성하는 공정과,Forming a contact plug and a first metal wiring by etching the metal wiring contact plug material and the first metal wiring material by an etching process using the photoresist pattern and the etch stop layer;

상기 감광막패턴을 제거하고, 상기 콘택플러그의 상부면을 노출시키는 평탄화된 층간절연막을 형성하는 공정과,Removing the photoresist pattern and forming a planarized interlayer insulating film exposing an upper surface of the contact plug;

상기 콘택플러그에 접속되는 제2금속배선을 형성하는 공정과,Forming a second metal wiring connected to the contact plug;

상기 제2금속배선 상부를 포함한 전체표면상부에 보호막을 형성하는 공정을 특징으로 한다.Forming a protective film on the entire surface including the upper portion of the second metal wiring.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3g 는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도이다.3A to 3G are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

먼저, 반도체기판(51) 상부에 제1금속배선 물질인 제1알루미늄막(53)을 형성하고 그 상부에 제1텅스텐막(55)을 형성한다. 이때, 상기 제1텅스텐막(55)은 식각방지막으로서, 구리, 구리합금 또는 텅스텐 합금 중에서 한가지로 대신 형성할 수 있다.그리고, 상기 제1텅스텐막(55) 상부에 제1감광막패턴(57)을 형성한다.First, the first aluminum film 53, which is the first metal wiring material, is formed on the semiconductor substrate 51, and the first tungsten film 55 is formed on the semiconductor substrate 51. In this case, the first tungsten film 55 may be formed of copper, a copper alloy, or a tungsten alloy instead of the etch stop film. The first photoresist film pattern 57 may be formed on the first tungsten film 55. To form.

이때, 상기 제1감광막패턴(57)은 제1금속배선 마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다. (도 3a)In this case, the first photoresist layer pattern 57 is formed by an exposure and development process using a first metal wiring mask (not shown). (FIG. 3A)

그 다음, 상기 제1감광막패턴(57)을 마스크로하여 상기 제1텅스텐막(55)을 식각하고 상기 제1감광막패턴(57)을 제거한다. (도 3b)Next, the first tungsten film 55 is etched using the first photoresist film pattern 57 as a mask, and the first photoresist film pattern 57 is removed. (FIG. 3B)

그리고, 전체표면상부에 제2알루미늄막(59)을 전체표면상부에 형성한다. (도 3c)Then, a second aluminum film 59 is formed over the entire surface over the entire surface. (FIG. 3C)

그 다음, 상기 제2알루미늄막(59) 상부에 제2감광막패턴(61)을 형성한다. 이때, 상기 제2감광막패턴(61)은 제1금속배선을 노출시킬 수 있는 제2금속배선 콘택마스크(도시안됨)를 이용한 노광 및 현상공정으로 형성한다. (도 3d)Next, a second photoresist layer pattern 61 is formed on the second aluminum layer 59. In this case, the second photoresist layer pattern 61 is formed by an exposure and development process using a second metal wiring contact mask (not shown) that can expose the first metal wiring. (FIG. 3D)

그리고, 상기 제2감광막패턴(61)을 마스크로하고 상기 텅스텐막(55)을 식각장벽으로 하여 상기 제2,1알루미늄막(59,53)을 식각함으로써 텅스텐 플러그와 제1금속배선를 형성한다.The tungsten plug and the first metal wiring are formed by etching the second and first aluminum films 59 and 53 using the second photoresist pattern 61 as a mask and the tungsten film 55 as an etch barrier.

이때, 상기 제2,1알루미늄막(59,53)의 식각공정은 BCl3가스를 이용하여 실시함으로써 상기 텅스텐막(55)과 상기 제2,1알루미늄막(59,53)이 식각선택비 차이를 가질 수 있도록 실시한다.In this case, the etching process of the second and first aluminum films 59 and 53 is performed by using BCl 3 gas, so that the etching selectivity difference between the tungsten film 55 and the second and first aluminum films 59 and 53 is different. To be able to have.

그 다음, 상기 제2감광막패턴(61)을 제거하고, 전체표면상부를 평탄화시키는 층간절연막(62)를 형성한다. (도 3e, 도 3f)Next, the second photoresist layer pattern 61 is removed, and an interlayer insulating layer 62 is formed to planarize the entire upper surface. (FIG. 3E, 3F)

그 다음, 상기 텅스텐막(59)으로 형성된 텅스텐 플러그를 노출시키도록 상기 층간절연막(62)을 CMP 한다.Next, the interlayer insulating film 62 is CMP to expose the tungsten plug formed from the tungsten film 59.

그리고, 상기 텅스텐 플러그에 접속되는 제3알루미늄막(63)으로 제2금속배선을 형성한다.Then, a second metal wiring is formed by the third aluminum film 63 connected to the tungsten plug.

그리고, 상기 제2금속배선 상부에 보호막(65)을 형성한다. (도 3g)In addition, a passivation layer 65 is formed on the second metal wiring. (Figure 3g)

본 발명의 다른 실시예는 상기 제1,2알루미늄(53,59) 대신 구리막을 사용하는 것이다.Another embodiment of the present invention is to use a copper film instead of the first and second aluminum (53, 59).

이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 서로 다른 금속배선 간의 단차가 커도 텅스텐막의 증착두께에 관계없이 식각방지막으로 사용하므로 플러그 형성시 알루미늄의 증착 두께만을 증가시켜 저항이 낮은 안정된 플러그를 형성할 수 있도록 하여 반도체소자의 제조공정을 단순화시키고 그에 따른 반도체소자의 생산성을 향상시킬 수 있는 효과를 제공한다.As described above, the metal wiring forming method of the semiconductor device according to the present invention is used as an etching prevention film regardless of the deposition thickness of the tungsten film even if the step difference between different metal wirings is large, so that only the deposition thickness of aluminum is increased when the plug is formed. It is possible to form a low stable plug to simplify the manufacturing process of the semiconductor device, thereby providing an effect that can improve the productivity of the semiconductor device.

Claims (4)

반도체기판 상부에 제1금속배선 물질인 제1알루미늄막을 형성하는 공정과,Forming a first aluminum film, which is a first metal wiring material, on the semiconductor substrate; 상기 제1금속배선 물질 상부에 식각방지막을 형성하는 공정과,Forming an etch stop layer on the first metal wiring material; 상기 식각방지막을 제1금속배선 마스크를 이용하여 패터닝하는 공정과,Patterning the etch stop layer using a first metal wiring mask; 전체표면상부에 금속배선 콘택플러그 물질인 제2알루미늄막을 형성하는 공정과,Forming a second aluminum film of a metallization contact plug material on the entire surface thereof; 상기 금속배선 콘택플러그 물질 상부에 금속배선 콘택마스크를 이용하여 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the metallization contact plug material using a metallization contact mask; 상기 감광막패턴과 식각방지막을 이용한 식각공정으로 상기 금속배선 콘택플러그 물질과 제1금속배선 물질을 식각하여 콘택플러그 및 제1금속배선을 형성하는 공정과,Forming a contact plug and a first metal wiring by etching the metal wiring contact plug material and the first metal wiring material by an etching process using the photoresist pattern and the etch stop layer; 상기 감광막패턴을 제거하고, 상기 콘택플러그의 상부면을 노출시키는 평탄화된 층간절연막을 형성하는 공정과,Removing the photoresist pattern and forming a planarized interlayer insulating film exposing an upper surface of the contact plug; 상기 콘택플러그에 접속되는 제2금속배선을 형성하는 공정과,Forming a second metal wiring connected to the contact plug; 상기 제2금속배선 상부를 포함한 전체표면상부에 보호막을 형성하는 공정을 특징으로하는 반도체소자의 금속배선 형성방법.Forming a protective film over the entire surface including the upper portion of the second metal wiring. 제 1 항에 있어서,The method of claim 1, 상기 금속배선 콘택플러그 물질과 제1금속배선 물질을 식각하는 공정은 BCl3가스를 이용하여 실시하는 것을 특징으로하는 반도체소자의 금속배선 형성방법.And etching the metallization contact plug material and the first metallization material using BCl 3 gas. 제 1 항에 있어서,The method of claim 1, 상기 제2금속배선 물질은 알루미늄막인 것을 특징으로하는 반도체소자의 금속배선 형성방법.The second metal wiring material is a metal film forming method of the semiconductor device, characterized in that the aluminum film. 제 1 항에 있어서,The method of claim 1, 상기 식각방지막은 구리, 텅스텐, 구리합금 또는 텅스텐 합금 중에서 한가지로 형성하는 것을 특징으로하는 반도체소자의 금속배선 형성방법. 」The etch stop layer is formed of one of copper, tungsten, copper alloy or tungsten alloy metal wiring forming method of the semiconductor device. 」
KR1019990064091A 1999-12-28 1999-12-28 A method for forming a metal line of semiconductor device KR100358569B1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06125010A (en) * 1992-10-12 1994-05-06 Fujitsu Ltd Manufacture of semiconductor device
US5385867A (en) * 1993-03-26 1995-01-31 Matsushita Electric Industrial Co., Ltd. Method for forming a multi-layer metallic wiring structure
US5534462A (en) * 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same
JPH08293585A (en) * 1995-02-20 1996-11-05 Matsushita Electric Ind Co Ltd Memory device and manufacture thereof
JPH10125679A (en) * 1996-10-21 1998-05-15 Oki Electric Ind Co Ltd Semiconductor device and its manufacture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06125010A (en) * 1992-10-12 1994-05-06 Fujitsu Ltd Manufacture of semiconductor device
US5385867A (en) * 1993-03-26 1995-01-31 Matsushita Electric Industrial Co., Ltd. Method for forming a multi-layer metallic wiring structure
JPH08293585A (en) * 1995-02-20 1996-11-05 Matsushita Electric Ind Co Ltd Memory device and manufacture thereof
US5534462A (en) * 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same
JPH10125679A (en) * 1996-10-21 1998-05-15 Oki Electric Ind Co Ltd Semiconductor device and its manufacture

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