KR100324935B1 - Method of forming wiring for semiconductor device - Google Patents
Method of forming wiring for semiconductor device Download PDFInfo
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- KR100324935B1 KR100324935B1 KR1019990023739A KR19990023739A KR100324935B1 KR 100324935 B1 KR100324935 B1 KR 100324935B1 KR 1019990023739 A KR1019990023739 A KR 1019990023739A KR 19990023739 A KR19990023739 A KR 19990023739A KR 100324935 B1 KR100324935 B1 KR 100324935B1
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- self
- pattern
- substrate
- insulating film
- film
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 125000006850 spacer group Chemical group 0.000 claims abstract description 21
- 230000001681 protective effect Effects 0.000 claims abstract description 19
- 238000009413 insulation Methods 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000001312 dry etching Methods 0.000 claims abstract description 3
- 238000001039 wet etching Methods 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims 4
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 자기정렬패턴의 상부폭을 하부폭보다 넓게 형성하여 상부배선과의 충분한 오버랩 마진을 확보할 수 있는 반도체 소자의 배선 형성방법을 제공한다.The present invention provides a method for forming a semiconductor device wiring that can form an upper width of the self-aligned pattern wider than the lower width to ensure sufficient overlap margin with the upper wiring.
본 발명에 따라, 상부에 보호막을 구비한 다수개의 도전층 패턴이 형성된 반도체 기판을 제공하고, 도전층 패턴 및 보호막의 양 측벽에 절연막 스페이서를 형성한다. 그런 다음, 기판 전면에 층간절연을 위한 제 1 절연막을 형성하고, 제 1 절연막의 표면을 일부 두께만큼 건식식각으로 제 1 식각하여, 보호막 상부에 보호막의 폭보다 작은 폭을 갖는 제 1 절연막의 돌출부를 형성한다. 그 후, 돌출부의 측벽에 희생산화막 스페이서를 형성하고, 절연막 스페이서 사이의 제 1 절연막을 기판의 표면이 노출되도록 제 2 식각하여 자기정렬 패턴용 제 1 콘택홀을 형성한 다음, 희생산화막 스페이서를 습식식각으로 제거한다. 그리고 나서, 제 1 콘택홀에 매립되도록 기판 전면에 자기정렬 패턴용 도전막을 형성하고, 도전막을 제 1 절연막의 돌출부 표면이 노출되도록 CMP로 전면식각하여, 그의 상부가 하부보다 1.5 내지 2배 정도 큰폭을 갖는 자기정렬 패턴을 형성한다. 그런 다음, 기판 전면에 층간절연을 위한 제 2 절연막을 형성하고, 자기정렬 패턴의 일부가 노출되도록 제 2 절연막을 식각하여 배선용 제 2 콘택홀을 형성한다.According to the present invention, a semiconductor substrate having a plurality of conductive layer patterns having a protective film formed thereon is provided, and insulating film spacers are formed on both sidewalls of the conductive layer pattern and the protective film. Then, a first insulating film for interlayer insulation is formed on the entire surface of the substrate, and the surface of the first insulating film is first etched by dry etching by a partial thickness, so that the protrusion of the first insulating film having a width smaller than the width of the protective film on the protective film. To form. Thereafter, a sacrificial oxide spacer is formed on the sidewall of the protrusion, and the first insulating layer between the insulating layer spacers is etched to expose the surface of the substrate to form a first contact hole for the self-aligning pattern, and then the sacrificial oxide spacer is wetted. Remove by etching. Then, a conductive film for a self-aligned pattern is formed on the entire surface of the substrate so as to be filled in the first contact hole, and the conductive film is etched by CMP so that the surface of the protrusion of the first insulating film is exposed. To form a self-aligned pattern having a. Then, a second insulating film for interlayer insulation is formed on the entire surface of the substrate, and the second insulating film is etched to expose a portion of the self-aligned pattern to form a second contact hole for wiring.
Description
본 발명은 반도체 소자의 배선형성방법에 관한 것으로, 특히 자기정렬 패턴을 이용한 반도체 소자의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method of a semiconductor device, and more particularly, to a wiring forming method of a semiconductor device using a self-aligning pattern.
일반적으로, 고집적화에 따른 반도체 소자의 배선 형성시, 상부 배선과의 오버랩 마진을 확보하기 위하여 자기정렬 패턴을 이용하였다.In general, in the formation of the wiring of the semiconductor device due to the high integration, a self-aligning pattern is used to secure an overlap margin with the upper wiring.
도 1a 내지 도 1d는 자기정렬 패턴을 이용한 종래의 반도체 소자의 배선형성방법을 설명하기 위한 단면도이다.1A to 1D are cross-sectional views illustrating a wiring forming method of a conventional semiconductor device using a self-aligned pattern.
도 1a를 참조하면, 필드 산화막(11)이 형성된 반도체 기판(10) 상에 그의 하부에는 게이트 절연막(12)이 형성되고, 상부에는 보호막(14)이 형성된 다수개의 도전층 패턴 (13), 예컨대 게이트를 형성한다. 여기서, 도전층 패턴(13)은 폴리실리콘막 패턴이다. 또한, 보호막(14)은 이후 형성되는 자기정렬 패턴과 도전층 패턴(13)과의 단락(short)을 방지한다. 그런 다음, 게이트 절연막(12), 도전층 패턴(13) 및 보호막(14)의 양 측벽에 절연막 스페이서(15)를 형성하고, 기판 전면에 층간절연을 위한 제 1 절연막(16)을 형성한다. 그런 다음, 절연막 스페이서(15) 사이의 제 1 절연막(16)을 기판(10)의 표면이 노출되도록 식각하여 자기정렬 패턴용 제 1 콘택홀 (17)을 형성한다.Referring to FIG. 1A, a plurality of conductive layer patterns 13 may be formed on a semiconductor substrate 10 on which a field oxide film 11 is formed, and a gate insulating film 12 may be formed at a lower portion thereof, and a protective film 14 may be formed at an upper portion thereof. Form a gate. Here, the conductive layer pattern 13 is a polysilicon film pattern. In addition, the protective layer 14 prevents a short between the self-aligned pattern and the conductive layer pattern 13 formed thereafter. Next, insulating film spacers 15 are formed on both sidewalls of the gate insulating film 12, the conductive layer pattern 13, and the protective film 14, and the first insulating film 16 for interlayer insulation is formed on the entire surface of the substrate. Then, the first insulating film 16 between the insulating film spacers 15 is etched to expose the surface of the substrate 10 to form the first contact hole 17 for the self-aligning pattern.
도 1b를 참조하면, 제 1 콘택홀(17)에 매립되도록 기판 전면에 자기정렬 패턴용 제 1 도전막(18)을 형성한다. 그런 다음, 화학기계연마(Chemical Mechanical Polishing; CMP)로 제 1 도전막(18)을 보호막(14)의 표면이 노출되도록 전면식각하여, 도 1c에 도시된 바와 같이, 자기정렬 패턴(18A)을 형성한다.Referring to FIG. 1B, a first conductive layer 18 for a self alignment pattern is formed on the entire surface of the substrate so as to be filled in the first contact hole 17. Then, the first conductive film 18 is etched by chemical mechanical polishing (CMP) so that the surface of the protective film 14 is exposed, and as shown in FIG. 1C, the self-aligned pattern 18A is formed. Form.
도 1d를 참조하면, 도 1c의 구조 상에 층간절연을 위한 제 2 절연막(19)을 형성하고, 제 2 절연막(19) 상부에 포토리소그라피로 포토레지스트막 패턴(20)을 형성한다. 그런 다음, 포토레지스트막 패턴(20)을 식각 마스크로하여 제 2 절연막 (19)을 자기정렬 패턴(18A)의 일부가 노출되도록 식각하여 배선용 제 2 콘택홀(21)을 형성한다.Referring to FIG. 1D, a second insulating film 19 for interlayer insulation is formed on the structure of FIG. 1C, and a photoresist film pattern 20 is formed by photolithography on the second insulating film 19. Thereafter, the second insulating layer 19 is etched using the photoresist layer pattern 20 as an etch mask to expose a portion of the self-aligning pattern 18A to form the second contact hole 21 for wiring.
그리고 나서, 도시되지는 않았지만, 공지된 방법으로 포토레지스트막 패턴 (20)을 제 2 콘택홀(21)에 매립되도록 배선용 제 2 도전막을 증착하고 패터닝하여, 자기정렬 패턴(18A)을 통하여 기판(10)과 콘택하는 배선을 형성한다.Then, although not shown, a second conductive film for wiring is deposited and patterned so that the photoresist film pattern 20 is embedded in the second contact hole 21 by a known method, and then the substrate (through the self-aligning pattern 18A) is formed. A wiring in contact with 10) is formed.
그러나, 배선형성을 위한 콘택홀(21)의 형성시, 소정의 마스크 오정렬이 발생될 경우, 도 1d의 A 부분에 도시된 바와 같이, 보호막(14)이 식각되고, 심한 경우에는 도전층 패턴(14)의 손상을 야기시킨다. 이에 따라, 배선과 도전층 패턴(14) 사이의 단락이 발생되어 소자의 동작에 치명적인 영향을 미칠뿐만 아니라 특성을 소자의 수율을 저하시킨다.However, when a predetermined mask misalignment occurs in forming the contact hole 21 for wiring formation, as shown in part A of FIG. 1D, the protective film 14 is etched, and in severe cases, the conductive layer pattern ( 14) causes damage. As a result, a short circuit between the wiring and the conductive layer pattern 14 occurs, which not only adversely affects the operation of the device, but also lowers the yield of the device.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 자기정렬 패턴의 상부폭을 하부폭보다 넓게 형성하여 상부 배선과의 오버랩 마진을 충분히 확보할 수 있는 반도체 소자의 배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, to provide a wiring forming method of a semiconductor device that can ensure a sufficient margin of overlap with the upper wiring by forming the upper width of the self-aligned pattern than the lower width. The purpose is.
도 1a 내지 도 1d는 종래의 반도체 소자의 배선 형성방법을 설명하기 위한 단면도.1A to 1D are cross-sectional views for explaining a wiring forming method of a conventional semiconductor device.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 배선 형성방법을 설명하기 위한 단면도.2A to 2E are cross-sectional views illustrating a method of forming wirings in a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
30 : 반도체 기판 31 : 필드 산화막30 semiconductor substrate 31 field oxide film
32 : 게이트 절연막 33 : 도전층 패턴32: gate insulating film 33: conductive layer pattern
34 : 보호막 35 : 절연막 스페이서34 protective film 35 insulating film spacer
36 : 제 1 절연막 36A : 제 1 절연막의 돌출부36: first insulating film 36A: protrusion of first insulating film
37 : 희생산화막 37A : 희생산화막 스페이서37: sacrificial oxide film 37A: sacrificial oxide film spacer
38 : 제 1 콘택홀 39 : 제 1 도전막38: first contact hole 39: first conductive film
39A : 자기정렬 패턴 40 : 제 2 절연막39A: self-aligned pattern 40: second insulating film
41 : 포토레지스트막 패턴41: photoresist film pattern
42 : 제 2 콘택홀42: second contact hole
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라, 상부에 보호막을 구비한 다수개의 도전층 패턴이 형성된 반도체 기판을 제공하고, 도전층 패턴 및 보호막의 양 측벽에 절연막 스페이서를 형성한다. 그런 다음, 기판 전면에 층간절연을 위한 제 1 절연막을 형성하고, 상기 제 1 절연막의 보호막과 대응된 부분을 일정 두께만큼 제 1 식각하여, 하부가 보호막과 동일폭을 가지며 상부가 보호막의 폭보다 작은 폭을 가진 돌출부를 형성한다. 그 후, 돌출부의 측벽에 희생산화막 스페이서를 형성하고, 돌출부를 포함한 희생산화막 스페이서를 마스크로 하여 제 1 절연막을 제 2 식각하여 기판의 표면을 노출시키는 자기정렬 패턴용 제 1 콘택홀을 형성한 다음, 희생산화막 스페이서를 습식식각으로 제거한다. 그리고 나서, 제 1 콘택홀에 매립되도록 기판 전면에 자기정렬 패턴용 도전막을 형성하고, 도전막을 제 1 절연막의 돌출부 표면이 노출되도록 CMP로 전면식각하여, 그의 상부가 하부보다 1.5 내지 2배 정도 큰폭을 갖는 자기정렬 패턴을 형성한다. 그런 다음, 기판 전면에 층간절연을 위한 제 2 절연막을 형성하고, 자기정렬 패턴의 일부가 노출되도록 제 2 절연막을 식각하여 배선용 제 2 콘택홀을 형성한다.In order to achieve the above object of the present invention, according to the present invention, there is provided a semiconductor substrate having a plurality of conductive layer patterns having a protective film thereon, and insulating film spacers are formed on both sidewalls of the conductive layer pattern and the protective film. Thereafter, a first insulating film for interlayer insulation is formed on the entire surface of the substrate, and the portion corresponding to the protective film of the first insulating film is first etched by a predetermined thickness so that the lower portion has the same width as the protective layer and the upper portion is larger than the width of the protective layer. Form a protrusion with a small width. Thereafter, a sacrificial oxide spacer is formed on the sidewall of the protrusion, and the first insulating layer is etched a second time using the sacrificial oxide spacer including the protrusion as a mask to form a first contact hole for a self-aligning pattern to expose the surface of the substrate. The sacrificial oxide spacers are removed by wet etching. Then, a conductive film for a self-aligned pattern is formed on the entire surface of the substrate so as to be filled in the first contact hole, and the conductive film is etched by CMP so that the surface of the protrusion of the first insulating film is exposed. To form a self-aligned pattern having a. Then, a second insulating film for interlayer insulation is formed on the entire surface of the substrate, and the second insulating film is etched to expose a portion of the self-aligned pattern to form a second contact hole for wiring.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 배선 형성방법을 설명하기 위한 단면도이다.2A through 2E are cross-sectional views illustrating a method of forming wirings in a semiconductor device in accordance with an embodiment of the present invention.
도 2a를 참조하면, 필드 산화막(31)이 형성된 반도체 기판(30) 상에 그의 하부에는 게이트 절연막(32)이 형성되고, 상부에는 보호막(34)이 형성된 다수개의 도전층 패턴(33), 예컨대 게이트를 형성한다. 여기서, 도전층 패턴(33)은 폴리실리콘막 패턴이다. 또한, 보호막(34)은 이후 형성되는 자기정렬 패턴과 도전층 패턴(33)과의 단락을 방지한다. 그런 다음, 게이트 절연막(32), 도전층 패턴(33) 및 보호막(34)의 양 측벽에 절연막 스페이서(35)를 형성하고, 기판 전면에 층간절연을 위한 제 1 절연막(36)을 형성한다. 그런 다음, 제 1 절연막(16)의 표면을 일부 두께만큼 건식식각으로 제 1 식각하여, 보호막(34) 상부에 보호막(34)의 폭보다 작은 폭을 갖는 돌출부(36A)를 형성하고, 기판 전면에 희생산화막(37)을 형성한다.Referring to FIG. 2A, a plurality of conductive layer patterns 33 may be formed on a semiconductor substrate 30 on which a field oxide layer 31 is formed, and a gate insulating layer 32 may be formed at a lower portion thereof, and a protective layer 34 may be formed at an upper portion thereof. Form a gate. Here, the conductive layer pattern 33 is a polysilicon film pattern. In addition, the protective film 34 prevents a short circuit between the self-aligned pattern and the conductive layer pattern 33 formed thereafter. Next, insulating film spacers 35 are formed on both sidewalls of the gate insulating film 32, the conductive layer pattern 33, and the protective film 34, and the first insulating film 36 for interlayer insulation is formed on the entire surface of the substrate. Thereafter, the surface of the first insulating film 16 is first etched by dry etching by a partial thickness to form a protrusion 36A having a width smaller than the width of the protective film 34 on the protective film 34, and the front surface of the substrate. A sacrificial oxide film 37 is formed on the substrate.
도 2b를 참조하면, 희생막(37)을 블랭킷 건식식각하여 제 1 절연막(36)의 돌출부(36A) 측벽에 희생산화막 스페이서(37A)를 형성하고, 인시튜(in-situ) 방식으로 절연막 스페이서(35) 사이의 제 1 절연막(36)을 기판(30) 표면이 노출되도록 제 2 식각하여 자기정렬 패턴용 제 1 콘택홀(38)을 형성한다.Referring to FIG. 2B, the sacrificial layer 37 is blanket-etched to form a sacrificial oxide spacer 37A on the sidewall of the protrusion 36A of the first insulating layer 36, and the insulating layer spacer is formed in-situ. The first insulating layer 36 between the second portions 35 is etched to expose the surface of the substrate 30 to form the first contact hole 38 for the self-aligning pattern.
도 2c를 참조하면, 희생산화막 스페이서(37A)를 습식식각을 이용하여 선택적으로 제거하고, 제 1 콘택홀(38)에 매립되도록 기판 전면에 자기정렬 패턴용 제 1 도전막(39)을 형성한다. 바람직하게, 습식식각은 보호막(34)에 대한 희생산화막의 선택비가 최소 10 이상인 습식식각용액을 이용하여 진행한다. 그런 다음, CMP로 제 1 도전막(39)을 제 1 절연막(36)의 돌출부(36A) 표면이 노출되도록 전면식각하여, 도 2d에 도시된 바와 같이, 자기정렬 패턴(39A)을 형성한다. 이때, 전면식각은 돌출부(36A)의 표면이 일부 두께만큼 제거되도록 진행한다. 또한, 본 발명의 자기정렬 패턴(39A)은 그의 상부가 하부보다 넓은 폭을 갖는다. 바람직하게, 자기정렬 패턴(39A)의 상부폭은 하부폭보다 1.5 내지 2배 정도 넓다.Referring to FIG. 2C, the sacrificial oxide spacer 37A is selectively removed using wet etching, and a first conductive layer 39 for a self-aligning pattern is formed on the entire surface of the substrate to be buried in the first contact hole 38. . Preferably, the wet etching is performed using a wet etching solution in which the selectivity of the sacrificial oxide film to the protective layer 34 is at least 10 or more. Then, the first conductive film 39 is etched with CMP so that the surface of the protrusion 36A of the first insulating film 36 is exposed, thereby forming a self-aligning pattern 39A, as shown in FIG. 2D. At this time, the front etching proceeds so that the surface of the protrusion 36A is removed by some thickness. In addition, the self-aligning pattern 39A of the present invention has a wider upper portion than the lower portion. Preferably, the upper width of the self-aligning pattern 39A is 1.5 to 2 times wider than the lower width.
도 2e를 참조하면, 기판 도 2d의 구조 상에 층간절연을 위한 제 2 절연막 (40)을 형성하고, 제 2 절연막(40) 상부에 포토리소그라피로 포토레지스트막 패턴(41)을 형성한다. 그런 다음, 포토레지스트막 패턴(41)을 식각 마스크로하여 제 2 절연막(40)을 자기정렬 패턴(39A)의 일부가 노출되도록 식각하여 배선용 제 2 콘택홀(42)을 형성한다. 이때, 넓은 상부폭을 갖는 자기정렬 패턴(39A)에 의해, 마스크 오정렬이 발생되더라도, 보호막(34)의 손상이 발생되지 않는다.Referring to FIG. 2E, a second insulating film 40 for interlayer insulation is formed on the structure of the substrate of FIG. 2D, and a photoresist film pattern 41 is formed on the second insulating film 40 by photolithography. Thereafter, the second insulating layer 40 is etched using the photoresist layer pattern 41 as an etch mask to expose a portion of the self-alignment pattern 39A to form a second contact hole 42 for wiring. At this time, even when the mask misalignment is caused by the self-aligning pattern 39A having a wide upper width, damage to the protective film 34 does not occur.
그리고 나서, 도시되지는 않았지만, 공지된 방법으로 포토레지스트막 패턴 (41)을 제 2 콘택홀(42)에 매립되도록 배선용 제 2 도전막을 증착하고 패터닝하여, 자기정렬 패턴(39A)을 통하여 기판(30)과 콘택하는 배선을 형성한다.Then, although not shown, a second conductive film for wiring is deposited and patterned so that the photoresist film pattern 41 is embedded in the second contact hole 42 by a known method, and then the substrate (through the self-aligning pattern 39A) is formed. A wiring in contact with 30 is formed.
상기한 본 발명에 의하면, 자기정렬 패턴의 상부폭을 하부폭보다 넓게 형성함으로써, 상부 배선과의 충분한 오버랩 마진을 확보하는 것이 가능하다. 또한, 콘택홀의 형성시 마스크 오정렬이 발생되더라도 보호막의 손상이 발생되지 않기 때문에, 도전층 패턴의 손상이 방지됨으로써, 소자의 동작특성 및 수율이 향상된다.According to the present invention described above, by forming the upper width of the self-aligning pattern wider than the lower width, it is possible to ensure sufficient overlap margin with the upper wiring. In addition, even if mask misalignment occurs when forming the contact hole, damage to the protective film does not occur, thereby preventing damage to the conductive layer pattern, thereby improving operation characteristics and yield of the device.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
Claims (7)
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| KR100625188B1 (en) * | 2005-05-10 | 2006-09-15 | 삼성전자주식회사 | Method of manufacturing a semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR980005592A (en) * | 1996-06-28 | 1998-03-30 | 김광호 | Self-aligned contact hole forming method |
| KR19980015079A (en) * | 1996-08-19 | 1998-05-25 | 김광호 | Semiconductor memory device and manufacturing method thereof |
| KR19980015073A (en) * | 1996-08-19 | 1998-05-25 | 김광호 | Method for manufacturing semiconductor device having landing pad |
| KR19980026089A (en) * | 1996-10-07 | 1998-07-15 | 김광호 | Method for forming self-aligned contact hole in semiconductor device |
| KR19980066718A (en) * | 1997-01-28 | 1998-10-15 | 김광호 | Method for forming contact pad of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR980005592A (en) * | 1996-06-28 | 1998-03-30 | 김광호 | Self-aligned contact hole forming method |
| KR19980015079A (en) * | 1996-08-19 | 1998-05-25 | 김광호 | Semiconductor memory device and manufacturing method thereof |
| KR19980015073A (en) * | 1996-08-19 | 1998-05-25 | 김광호 | Method for manufacturing semiconductor device having landing pad |
| KR19980026089A (en) * | 1996-10-07 | 1998-07-15 | 김광호 | Method for forming self-aligned contact hole in semiconductor device |
| KR19980066718A (en) * | 1997-01-28 | 1998-10-15 | 김광호 | Method for forming contact pad of semiconductor device |
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