KR100413043B1 - Gate electrode formation method of semiconductor device - Google Patents
Gate electrode formation method of semiconductor device Download PDFInfo
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- KR100413043B1 KR100413043B1 KR1019970027847A KR19970027847A KR100413043B1 KR 100413043 B1 KR100413043 B1 KR 100413043B1 KR 1019970027847 A KR1019970027847 A KR 1019970027847A KR 19970027847 A KR19970027847 A KR 19970027847A KR 100413043 B1 KR100413043 B1 KR 100413043B1
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 6
- 239000010937 tungsten Substances 0.000 claims abstract description 6
- 150000004767 nitrides Chemical class 0.000 claims description 19
- 125000006850 spacer group Chemical group 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28238—Making the insulator with sacrificial oxide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 제조 분야에 관한 것임.Regarding the field of semiconductor manufacturing.
2. 발명이 해결하고자 하는 기술적 과제 2. Technical problem to be solved by the invention
미세한 크기를 갖는 고집적 반도체 장치의 게이트 형성 방법에 있어서 비교적 간단한 마스크 공정으로 형성되며 식각 손상을 방지할 수 있는 반도체 장치의 게이트 전극 제조 방법을 제공한다.Provided is a method of manufacturing a gate electrode of a semiconductor device, which is formed by a relatively simple mask process in the gate forming method of a highly integrated semiconductor device having a fine size and can prevent etching damage.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
소자분리막에 의해 발생하는 단차를 유동성이 좋은 절연막으로 평탄화시키고, 절연막을 식각하여 형성한 홀에 게이트 전극을 형성하기 위하여 전도막내에 전도층을 일부 형성시키고 전도층 상에만 형성되는 선택적 텅스텐을 이용한 고집적 반도체 장치의 게이트 전극을 형성한다.High density using selective tungsten formed only on the conductive layer and partially forming a conductive layer in the conductive film to form a gate electrode in the hole formed by etching the insulating film by flattening the step generated by the device isolation film with a good fluidity insulating film. A gate electrode of the semiconductor device is formed.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 장치 제조 공정에 이용됨Used in semiconductor device manufacturing process
Description
본 발명은 일반적으로 반도체 장치 제조 방법에 관한 것으로, 특히 고집적 반도체 장치의 게이트 전극 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a gate electrode of a highly integrated semiconductor device.
게이트를 형성하는 종래의 기술은 게이트 전극을 형성하기 위한 전도막을 증착한 후 사진식각 공정으로 게이트 전극을 형성한다.The conventional technique of forming a gate forms a gate electrode by a photolithography process after depositing a conductive film for forming the gate electrode.
0.20 ㎛이하의 미세 패턴이 필요한 디램인 경우에는 몇가지 공정 기술상에 있어서 어려운 점이 있는데, 첫째로 하부 절연막이 평탄하지 못하기 때문에 마스크를 이용한 사진식각 작업이 매우 어렵다. 따라서, 건조 현상(dry development) 기술 중에 삼중감광막 (three layer resist)방법을 사용한다. 그러나, 공정이 복잡하고, 원하는 패턴을 마스킹 층을 통해 식각하고자 하는 박막 위로 전이할 때 손실이 매우 크다. 또한, 게이트 절연막이 55Å 이하로 매우 얇기 때문에 게이트 전극을 형성하기 위한 식각 공정에서 고식각 선택비를 요구한다. 이때 너무 선택비가 높으면 식각이 정지되고, 선택비가 낮으면 식각 손상이 발생하는 문제점이 있다.In the case of a DRAM which requires a fine pattern of 0.20 μm or less, there are difficulties in some process technologies. First, since the lower insulating film is not flat, photolithography using a mask is very difficult. Therefore, a three layer resist method is used in a dry development technique. However, the process is complex and the losses are very high when transferring the desired pattern over the thin film to be etched through the masking layer. In addition, since the gate insulating film is very thin, which is 55 kW or less, a high etching selectivity is required in the etching process for forming the gate electrode. At this time, if the selection ratio is too high, the etching is stopped, if the selection ratio is low, there is a problem that the etching damage occurs.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 비교적 간단한 고집적 반도체 장치의 게이트 전극 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method of forming a gate electrode of a relatively simple integrated semiconductor device.
상기 목적을 달성하기 위한 본 발명은 반도체 장치의 게이트 전극 형성 방법에 있어서, 소정의 하부층이 형성된 반도체 기판 상에 소자분리막을 형성하는 단계; 상기 전체 구조 상에 제1 질화막을 형성하는 단계; 상기 전체 구조 상에 단차를 제거하기 위한 절연막을 형성하는 단계; 상기 절연막을 선택적으로 식각하여 게이트 전극이 형성될 홀을 형성하는 단계; 상기 전체 구조 상부에 제2 질화막을 형성하는 단계; 상기 제2 질화막을 전면 식각하여 상기 홀 측면에 스페이서를 형성함과 동시에 상기 홀 바닥의 반도체 기판이 노출되도록 하는 단계; 상기 홀의 바닥에 게이트 절연막을 형성하는 단계; 상기 홀의 일부분에 전도막을 형성하는 단계;상기 전도막에만 증착되는 선택 텅스텐 막을 형성하는 단계; 상기 산화막을 제거하는 단계; 상기 소자분리막 상에 형성된 제1 질화막을 제거하는 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of forming a gate electrode of a semiconductor device, the method including: forming an isolation layer on a semiconductor substrate on which a predetermined lower layer is formed; Forming a first nitride film on the entire structure; Forming an insulating film for removing a step on the entire structure; Selectively etching the insulating layer to form a hole in which a gate electrode is to be formed; Forming a second nitride film over the entire structure; Etching the entire surface of the second nitride layer to form a spacer on the side of the hole and simultaneously exposing the semiconductor substrate at the bottom of the hole; Forming a gate insulating film on the bottom of the hole; Forming a conductive film in a portion of the hole; forming a selective tungsten film deposited only on the conductive film; Removing the oxide film; And removing the first nitride film formed on the device isolation film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 살펴본다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도1A 내지 도1F는 본 발명의 일실시예에 따른 반도체 장치의 게이트 전극 형성 방법을 도시한 것이다.1A to 1F illustrate a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
먼저, 도1A에 도시한 바와 같이 소정의 하부층이 형성된 실리콘 기판(11) 상에 소자분리를 위한 필드 산화막(12)을 형성한다. First, as shown in FIG. 1A, a
다음으로, 도1B에 도시한 바와 같이 상기 전체 구조 상에 제1 질화막(13)을 형성하고 상기 필드 산화막(12)에 의한 단차를 제거하기 위하여 유동성이 큰 산화막(14)막을 증착시킨다. 이어서, 상기 산화막(14) 상에 음성 감광막을 도포하고 종래의 게이트 전극을 형성하기 위한 마스크를 이용하여 상기 감광막을 패터닝하여 게이트 전극이 형성될 영역 상부의 상기 산화막(14)을 노출하는 감광막 패턴(15)을 형성한다. Next, as shown in Fig. 1B, a first
다음으로, 도1C에 도시한 바와 같이 상기 감광막 패턴(15)을 식각 장벽으로하여 상기 산화막(14)과 상기 제1 질화막(13)을 순차적으로 식각하여 게이트 전극이 형성될 홀(h)을 형성한다. 이어서 상기 감광막 패턴(15)을 02 플라즈마로 제거하고 제2 질화막(16)을 얇게 증착한다.Next, as shown in FIG. 1C, the
다음으로, 도1D에 도시한 바와 같이 상기 질화막(16)을 전면 식각하여 상기 홀(h) 측면에 스페이서(17)를 형성함과 동시에 활성영역을 노출하고, 상기 홀(h)의 바닥의 노출된 활성영역에 게이트 절연막(18)을 형성한다. 이어서, 게이트 전극을 형성하기 위하여 도핑된 폴리실리콘막(19)을 두껍게 형성한다. 여기서 상기 폴리실리콘막(19)을 상기 홀(A) 내부에 보이드 없이 형성한다.Next, as shown in FIG. 1D, the
다음으로, 도1E에 도시한 바와 같이 상기 폴리실리콘막(19)을 전면식각하여 상기 폴리실리콘막(19)이 상기 홀(h) 내부에만 남도록 한다. 이어서, 도전층 위에만 증착되는 선택적 텅스텐(selective tungsten)막(20)을 증착시킨다.Next, as shown in FIG. 1E, the
다음으로, 도1F에 도시한 바와 같이 습식공정으로 상기 산화막(14)을 제거한다, 이때 상기 스페이서(17)는 습식식각으로 인한 게이트 절연막의 손실을 막고, 상기 제1 질화막(13)은 필드산화막(12)을 보호하는 역할을 한다, 이어서, 상기 산화막(14)막이 완전히 제거되면 질화막과 산화막에 대한 식각선택비가 매우 큰 식각제로 전면 식각을 하여 필드산화막 상에 형성된 제1 질화막(13)을 비등방성 건식 식각 방법으로 제거한다. 이 과정에서 제2 질화막으로 상기 홀(h)의 측벽에 형성된 상기 스페이서(17)는 그대로 남게 된다.Next, as shown in FIG. 1F, the
본 발명은 55Å 두께 이하의 얇은 게이트 절연막 상에 게이트 전극을 형성하는 방법에 있어서 증착되는 막의 특성을 이용하는 것으로 식각 과정에서 야기되는 문제점을 극복할 수 있다. 또한 하부의 소자분리막에 의하여 발생하는 단차를 평탄화시킴으로써 간단한 마스크 공정을 실시하는 것이 가능하다.The present invention can overcome the problems caused by the etching process by using the characteristics of the deposited film in the method for forming a gate electrode on a thin gate insulating film less than 55Å thickness. In addition, it is possible to perform a simple mask process by flattening the level difference generated by the lower device isolation film.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 4G 디램급 이상에서 0.20 ㎛ 이하의 미세 패턴 형성시 하부 구조의 차를 극복하여 보다 간단한 마스크 공정으로 실시할 수 있고, 도전체 물질 위에만 증착되는 선택적 텅스텐의 특성을 이용하여 게이트 전극을 형성하기 때문에 소자의 신뢰성을 향상시킬 수 있다. 또한, 게이트 전극의 측벽에 스페이서가 자동 정렬 방식으로 형성되므로 공정의 단계를 줄일 수 있다.The present invention made as described above can be carried out in a simpler mask process by overcoming the difference of the lower structure when forming a fine pattern of 0.20 ㎛ or less in the 4G DRAM class or more, using the characteristic of selective tungsten deposited only on the conductor material By forming the gate electrode, the reliability of the device can be improved. In addition, since spacers are formed on the sidewalls of the gate electrode in an automatic alignment method, the steps of the process may be reduced.
도1A 내지 도1F는 본 발명의 일실시예에 따른 반도체 장치의 게이트 전극 형성 공정 단면도1A to 1F are cross-sectional views of a gate electrode forming process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing
11: 실리콘 기판 12: 필드산화막11: silicon substrate 12: field oxide film
13: 제1 질화막 14: 산화막13: first nitride film 14: oxide film
15: 감광막 16: 제2 질화막15: Photosensitive film 16: 2nd nitride film
17: 스페이서 18: 게이트 절연막17: spacer 18: gate insulating film
19: 폴리실리콘막 20: 선택 텅스텐막19: polysilicon film 20: optional tungsten film
h: 홀h: hall
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970027847A KR100413043B1 (en) | 1997-06-26 | 1997-06-26 | Gate electrode formation method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970027847A KR100413043B1 (en) | 1997-06-26 | 1997-06-26 | Gate electrode formation method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990003884A KR19990003884A (en) | 1999-01-15 |
| KR100413043B1 true KR100413043B1 (en) | 2005-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970027847A KR100413043B1 (en) | 1997-06-26 | 1997-06-26 | Gate electrode formation method of semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR100413043B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR900017103A (en) * | 1989-04-07 | 1990-11-15 | 정몽헌 | FET gate electrode fine pattern formation method |
| JPH04346422A (en) * | 1991-05-24 | 1992-12-02 | Nec Corp | Semiconductor device and manufacture thereof |
| KR920022449A (en) * | 1991-05-28 | 1992-12-19 | 홍신남 | Self-aligned gate trench MOSFET manufacturing method |
| US5464782A (en) * | 1994-07-05 | 1995-11-07 | Industrial Technology Research Institute | Method to ensure isolation between source-drain and gate electrode using self aligned silicidation |
-
1997
- 1997-06-26 KR KR1019970027847A patent/KR100413043B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR900017103A (en) * | 1989-04-07 | 1990-11-15 | 정몽헌 | FET gate electrode fine pattern formation method |
| JPH04346422A (en) * | 1991-05-24 | 1992-12-02 | Nec Corp | Semiconductor device and manufacture thereof |
| KR920022449A (en) * | 1991-05-28 | 1992-12-19 | 홍신남 | Self-aligned gate trench MOSFET manufacturing method |
| US5464782A (en) * | 1994-07-05 | 1995-11-07 | Industrial Technology Research Institute | Method to ensure isolation between source-drain and gate electrode using self aligned silicidation |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990003884A (en) | 1999-01-15 |
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