KR20010064074A - Method for forming self-aligned contact in semiconductor device - Google Patents

Method for forming self-aligned contact in semiconductor device Download PDF

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Publication number
KR20010064074A
KR20010064074A KR1019990062194A KR19990062194A KR20010064074A KR 20010064074 A KR20010064074 A KR 20010064074A KR 1019990062194 A KR1019990062194 A KR 1019990062194A KR 19990062194 A KR19990062194 A KR 19990062194A KR 20010064074 A KR20010064074 A KR 20010064074A
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South Korea
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self
contact hole
forming
aligned contact
semiconductor device
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KR1019990062194A
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Korean (ko)
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박성찬
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990062194A priority Critical patent/KR20010064074A/en
Publication of KR20010064074A publication Critical patent/KR20010064074A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

Abstract

PURPOSE: A method for manufacturing a self-aligned contact hole of a semiconductor device is provided to improve contact resistance by guaranteeing a lower area of the contact hole, and to improve an electrical characteristic by preventing a substrate from being damaged. CONSTITUTION: A gate structure having a hard mask layer composed of a material having etch selectivity with an interlayer dielectric and a sidewall spacer layer is formed on a semiconductor substrate(20). A planarized interlayer dielectric is formed on the entire structure. The interlayer dielectric in a self-aligned contact region is selectively dry-etched, in which the dry etching process is performed to expose the sidewall spacer layer and to expose the semiconductor substrate.

Description

반도체 소자의 자기정렬 콘택홀 형성방법{Method for forming self-aligned contact in semiconductor device}Method for forming self-aligned contact in semiconductor device

본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자 제조시 자기정렬 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly, to a method for forming a self-aligned contact hole in manufacturing a semiconductor device.

반도체 장치의 집적도가 증가함에 따라 반도체 장치의 다층화는 필수적인 사항이 되어 있으며, 그 각 층을 이루는 각종 패턴의 미세화도 가속화되고 있다. 이에 따라 일반적인 리소그래피 공정으로는 층간의 정확한 중첩 정확도를 확보하기가 어렵다. 특히, 이러한 리소그래피 공정의 한계에 의해 콘택 형성시 도전층간의 단락이 발생하는 문제점을 극복하기 위한 많은 연구·개발이 진행되어 왔다.As the integration degree of a semiconductor device increases, the multilayering of a semiconductor device becomes an essential matter, and the refinement | miniaturization of the various patterns which comprise each layer is also accelerating. As a result, it is difficult to ensure accurate overlapping accuracy between layers in a general lithography process. In particular, due to the limitation of the lithography process, a lot of researches and developments have been conducted to overcome the problem of a short circuit between conductive layers during contact formation.

최근에는 하부층의 토폴로지(topology) 및 절연막간의 식각 선택비를 이용하여 콘택 형성시의 마진을 확보하고자 하는 자기정렬 콘택(self-aligned contact, SAC) 기술이 일반화되어 있다.Recently, self-aligned contact (SAC) technology has been generalized to secure a margin at the time of forming a contact using a topology of an underlying layer and an etching selectivity between insulating layers.

첨부된 도면 도 1a 내지 도 1b는 종래기술에 따른 자기정렬 방식의 비트라인 콘택홀 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1A to 1B illustrate a process of forming a bit line contact hole in a self-aligning method according to the related art, which will be described below with reference to the drawing.

도 1a는 게이트 구조가 형성된 실리콘 기판(10) 층간절연 산화막(15)을 증착하고, 그 상부에 콘택홀 마스크를 사용한 사진 공정을 통해 포토레지스트 패턴(16)이 형성된 상태를 나타낸 것으로, 게이트 구조는 차례로 적층된 게이트 산화막(11), 게이트 전극(12), 하드 마스크 질화막(13)과 그 패턴 측벽의 스페이서 질화막(14)으로 구성된다.FIG. 1A illustrates a state in which a photoresist pattern 16 is formed by depositing an interlayer insulating oxide layer 15 of a silicon substrate 10 having a gate structure and using a contact hole mask thereon. The gate oxide film 11, the gate electrode 12, the hard mask nitride film 13, and the spacer nitride film 14 on the sidewalls of the pattern are sequentially formed.

다음으로, 도 1b는 포토레지스트 패턴(16)을 식각 마스크로 사용하여 스페이서 질화막(14)이 노출될 정도로 층간절연 산화막(15)을 건식 식각한 상태를 나타낸 것으로, 식각된 층간절연 산화막(15) 측벽에 폴리머(17)가 형성됨을 나타내고 있다.Next, FIG. 1B illustrates a state in which the interlayer insulating oxide film 15 is dry-etched to the extent that the spacer nitride film 14 is exposed using the photoresist pattern 16 as an etching mask. The polymer 17 is formed on the side wall.

계속하여, 도 1c는 건식 식각을 종료한 후의 콘택홀 프로파일을 나타낸 것으로, SAC 메커니즘 상 스페이서 질화막(14)이 노출되면서 다량의 폴리머가 발생하여 측벽 패시베이션 효과를 일으키고, 이에 따라 식각 프로파일의 경사가 유발되어 콘택홀 하부의 면적이 축소되는 문제점(A)이 나타난다. 이 경우 후속 콘택 물질 매립시의 스텝 커버리지 감소, 접촉 저항의 증가 등의 문제점이 우려된다.Subsequently, FIG. 1C illustrates the contact hole profile after the dry etching is completed, and a large amount of polymer is generated as the spacer nitride layer 14 is exposed on the SAC mechanism, thereby causing a sidewall passivation effect, thereby causing an inclination of the etching profile. This results in a problem (A) in which the area under the contact hole is reduced. In this case, there are concerns such as a decrease in step coverage and an increase in contact resistance during subsequent contact material filling.

또한, 건식 식각에 의한 콘택홀 형성은 실리콘 기판(10)의 식각 손상을 피할 수 없으며, 이러한 식각 손상은 누설전류의 증가와 같은 소자의 전기적 특성 열화를 초래한다.In addition, contact hole formation by dry etching cannot avoid etching damage of the silicon substrate 10, and such etching damage causes deterioration of electrical characteristics of the device such as an increase in leakage current.

본 발명은 자기정렬 식각시 콘택홀 하부 면적 축소와 기판의 식각 손상을 방지할 수 있는 자기정렬 콘택홀 형성방법을 제공하는데 그 목적이 있다.It is an object of the present invention to provide a method for forming a self-aligned contact hole which can prevent the contact hole lower area and the etching damage of the substrate during self-aligned etching.

도 1a 내지 도 1c는 종래기술에 따른 자기정렬 방식의 비트라인 콘택홀 형성 공정도.1A to 1C are diagrams illustrating a process of forming a bit line contact hole using a self-aligning method according to the related art.

도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 자기정렬 방식의 비트라인 콘택홀 형성 공정도.2A to 2D are diagrams illustrating a process of forming a bit line contact hole in a self-aligning method according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

20 : 실리콘 기판 21 : 게이트 산화막20 silicon substrate 21 gate oxide film

22 : 게이트 전극 23 : 하드 마스크 질화막22 gate electrode 23 hard mask nitride film

24 : 스페이서 질화막 25 : 층간절연 산화막24 spacer nitride film 25 interlayer insulating oxide film

26 : 포토레지스트 패턴 27 : 폴리머26 photoresist pattern 27 polymer

상기의 기술적 과제를 해결하기 위한 본 발명의 특징적인 자기정렬 콘택홀 형성방법은, 반도체 기판 상에 층간절연막과 식각 선택비를 가지는 물질로 하드 마스크층 및 측벽 스페이서층을 구비한 게이트 구조를 형성하는 제1 단계; 상기 제1 단계를 마친 전체 구조 상부에 평탄화된 상기 층간절연막을 형성하는 제2 단계; 자기정렬 콘택 영역의 상기 층간절연막을 선택적으로 건식 식각하되, 상기 측벽 스페이서층이 노출되고 상기 반도체 기판이 노출되지 않을 정도로 상기 건식 식각을 수행하는 제3 단계; 및 상기 자기정렬 콘택 영역에 잔류하는 상기 층간절연막을 습식 제거하는 제4 단계를 포함하여 이루어진다.In order to solve the above technical problem, a method of forming a self-aligned contact hole according to the present invention includes forming a gate structure including a hard mask layer and a sidewall spacer layer on a semiconductor substrate using a material having an interlayer insulating layer and an etching selectivity. First step; A second step of forming the planarized interlayer insulating film on the entire structure after the first step; Selectively dry etching the interlayer dielectric layer in a self-aligned contact region, wherein the dry etching is performed such that the sidewall spacer layer is exposed and the semiconductor substrate is not exposed; And a fourth step of wet removing the interlayer dielectric film remaining in the self-aligned contact region.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

첨부된 도면 도 2a 내지 도 2d는 본 발명의 일 실시예에 따른 자기정렬 방식의 비트라인 콘택홀 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A to 2D illustrate a process of forming a bit line contact hole in a self-aligning method according to an embodiment of the present invention, which will be described below with reference to the drawing.

본 실시예에 따른 자기정렬 방식의 비트라인 콘택홀 형성 공정은, 우선 도 2a에 도시된 바와 같이 게이트 구조가 형성된 실리콘 기판(20) 층간절연 산화막(주로 실리콘산화막)(25)을 증착하고, 그 상부에 콘택홀 마스크를 사용한 사진 공정을 통해 포토레지스트 패턴(26)을 형성한다. 게이트 구조는 차례로 적층된 게이트 산화막(21), 게이트 전극(22), 하드 마스크 질화막(23)과 그 패턴 측벽의 스페이서 질화막(24)으로 구성된다.In the self-aligned bit line contact hole forming process according to the present embodiment, first, an interlayer insulating oxide film (mainly a silicon oxide film) 25 having a gate structure is deposited as shown in FIG. 2A. The photoresist pattern 26 is formed through a photolithography process using a contact hole mask thereon. The gate structure includes a gate oxide film 21, a gate electrode 22, a hard mask nitride film 23, and a spacer nitride film 24 on the sidewalls of the pattern, which are sequentially stacked.

다음으로, 포토레지스트 패턴(26)을 식각 마스크로 사용하여 층간절연 산화막(25)을 건식 식각한다. 식각 소오스 가스로는 CF계 가스, CHF계 가스를 사용한다. 도 2b는 스페이서 질화막(24)이 노출될 정도로 건식 식각을 진행한 상태를 나타낸 것이며, 도 2c는 스페이서 질화막(24)이 노출된 상태에서 건식 식각을 일정 시간만큼 수행한 상태를 나타낸 것이다. 이때, 콘택 영역에서 층간절연 산화막(25)의 일부가 잔류되도록 하며, 식각된 층간절연 산화막(25) 측벽에 폴리머(27)가 형성되며, 스페이서 질화막(24)이 노출되면서 폴리머(27)의 발생이 증가하여 콘택홀 측벽 프로파일이 경사지게 된다.Next, the interlayer insulating oxide film 25 is dry etched using the photoresist pattern 26 as an etching mask. As the etching source gas, CF gas or CHF gas is used. FIG. 2B illustrates a state in which dry etching is performed such that the spacer nitride layer 24 is exposed, and FIG. 2C illustrates a state in which dry etching is performed for a predetermined time while the spacer nitride layer 24 is exposed. At this time, a part of the interlayer insulating oxide film 25 is left in the contact region, and a polymer 27 is formed on the sidewall of the etched interlayer insulating oxide film 25, and the spacer 27 is exposed to generate the polymer 27. This increase causes the contact hole sidewall profile to be inclined.

계혹하여, 도 2d에 도시된 바와 같이 BOE(buffered oxide echant), HF 용액 등을 사용하여 콘택 영역의 층간절연 산화막(25)를 습식 제거함으로써 콘택홀을 완전히 오픈시킨다.In the meantime, as shown in FIG. 2D, the contact hole is completely opened by wet removal of the interlayer insulating oxide film 25 in the contact region using a buffered oxide etch (BOE), an HF solution, or the like.

상기와 같은 공정을 진행하는 경우, 건식 식각과 함께 콘택홀 식각 말기에 습식 식각을 적용함으로써 콘택홀 하부(B적을 확보하고 기판의 식각 손상을 방지할 수 있게 된다.In the case of performing the above process, by applying wet etching to the end of the contact hole etching together with dry etching, it is possible to secure the contact hole lower portion (B) and to prevent the etching damage of the substrate.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

예컨대, 전술한 실시예에서는 실리콘산화막계 층간절연막을 사용하는 경우를 일례로 들어 설명하였으나, 본 발명은 저유전율 산화막을 사용하는 경우에도 적용된다.For example, in the above-described embodiment, a case of using a silicon oxide film-based interlayer insulating film has been described as an example, but the present invention is also applied to a case of using a low dielectric constant oxide film.

또한, 전술한 실시예에서는 하드 마스크 및 측벽 스페이서로 질화막을 사용하는 경우를 일례로 들어 설명하였으나, 질화막을 대신하여 층간절연막과 식각 선택비를 가지는 다른 절연막을 사용하는 경우에도 본 발명은 적용된다.In the above-described embodiment, the case where the nitride film is used as the hard mask and the sidewall spacer is described as an example. However, the present invention is also applied to the case where another insulating film having an etch selectivity with an interlayer insulating film is used instead of the nitride film.

한편, 전술한 실시예에서는 통상의 비트라인 콘택홀을 형성하는 경우를 일례로 들어 설명하였으나, 본 발명은 라인 형태, T자 형태, I자 형태, Z자 형태의 자기정렬 콘택홀을 사용하는 경우에도 적용된다.Meanwhile, in the above-described embodiment, the case of forming a conventional bit line contact hole has been described as an example, but the present invention uses a self-aligned contact hole having a line shape, a T shape, an I shape, and a Z shape. Also applies.

전술한 본 발명은 콘택홀 하부 면적을 확보하여 접촉 저항을 개선하는 효과가 있으며, 기판의 식각 손상을 방지하여 누설전류와 같은 소자의 전기적 특성을 개선하는 효과가 있다.The present invention has the effect of improving the contact resistance by securing a contact hole lower area, and has the effect of preventing the etching damage of the substrate to improve the electrical characteristics of the device, such as leakage current.

Claims (3)

반도체 기판 상에 층간절연막과 식각 선택비를 가지는 물질로 하드 마스크층 및 측벽 스페이서층을 구비한 게이트 구조를 형성하는 제1 단계;Forming a gate structure including a hard mask layer and a sidewall spacer layer of a material having an interlayer insulating layer and an etching selectivity on the semiconductor substrate; 상기 제1 단계를 마친 전체 구조 상부에 평탄화된 상기 층간절연막을 형성하는 제2 단계;A second step of forming the planarized interlayer insulating film on the entire structure after the first step; 자기정렬 콘택 영역의 상기 층간절연막을 선택적으로 건식 식각하되, 상기 측벽 스페이서층이 노출되고 상기 반도체 기판이 노출되지 않을 정도로 상기 건식 식각을 수행하는 제3 단계; 및Selectively dry etching the interlayer dielectric layer in a self-aligned contact region, wherein the dry etching is performed such that the sidewall spacer layer is exposed and the semiconductor substrate is not exposed; And 상기 자기정렬 콘택 영역에 잔류하는 상기 층간절연막을 습식 제거하는 제4 단계A fourth step of wet removing the interlayer dielectric film remaining in the self-aligned contact region 를 포함하여 이루어진 반도체 소자의 자기정렬 콘택홀 형성방법.Self-aligning contact hole forming method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 층간절연막이 실리콘산화막이며, 상기 하드 마스크층 및 상기 측벽 스페이서층이 실리콘질화막인 것을 특징으로 하는 반도체 소자의 자기정렬 콘택홀 형성방법.Wherein said interlayer insulating film is a silicon oxide film and said hard mask layer and said sidewall spacer layer are silicon nitride films. 제2항에 있어서,The method of claim 2, 상기 제4 단계에서,In the fourth step, BOE(buffered oxide echant) 용액 또는 불산(HF) 용액을 에천트로 사용하는 것을 특징으로 하는 반도체 소자의 자기정렬 콘택홀 형성방법.A method of forming a self-aligned contact hole in a semiconductor device, comprising using a BOE (buffered oxide echant) solution or a hydrofluoric acid (HF) solution as an etchant.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100689677B1 (en) * 2005-06-21 2007-03-09 주식회사 하이닉스반도체 A semiconductor device and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100689677B1 (en) * 2005-06-21 2007-03-09 주식회사 하이닉스반도체 A semiconductor device and method for manufacturing the same

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