KR20030002886A - Method of forming fine line pattern using sacrificial oxide layer - Google Patents
Method of forming fine line pattern using sacrificial oxide layer Download PDFInfo
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Abstract
Description
본 발명은 희생산화막을 이용한 미세패턴 형성방법에 관한 것으로, 특히 반도체소자의 디자인 룰의 감소에 따른 포토리소그래피 해상력의 한계로 인해 라인패턴의 크기를 감소시키는 것이 불가능한 상황에서 이를 극복할 수 있는 워드라인 및 비트라인의 형성공정에 관한 것이다.The present invention relates to a method for forming a fine pattern using a sacrificial oxide film, and in particular, a word line that can overcome the situation in which it is impossible to reduce the size of the line pattern due to the limitation of photolithography resolution due to the reduction of the design rule of the semiconductor device. And a bit line forming process.
DRAM소자의 디자인 룰 감소에 따라 해당 선폭(pitch)에서 워드라인(및/또는 비트라인)의 패터닝 크기를 감소시키는 것, 즉 패턴간의 간격을 증가시키는 것은 포토리소그래피 공정 해상력의 한계로 불가능한 상황이다. 해당 선폭에서 워드라인(비트라인)의 패터닝 크기를 감소시키는 것은 다음과 같은 이유로 인해 요구되고 있다.As the design rule of the DRAM device decreases, it is impossible to reduce the patterning size of the word line (and / or bit line) in the corresponding pitch, that is, increase the spacing between patterns, due to the limitation of the photolithography process resolution. Reducing the patterning size of a word line (bit line) in the line width is required for the following reasons.
첫째, 선폭의 애스펙트비를 완화시켜 후속 층간절연막 증착공정의 갭 매립(Gap filling) 마진을 향상시킨다.First, the aspect ratio of the line width is alleviated to improve the gap filling margin of the subsequent interlayer dielectric deposition process.
둘째, 라인 간격의 증가로 인한 하부층(서브 액티브 또는 서브 플러그 패드)과의 접촉면적을 증가시켜 셀 메모리 콘택의 접촉저항을 향상시킨다.Second, the contact area of the cell memory contact is improved by increasing the contact area with the lower layer (sub active or sub plug pad) due to the increase in the line spacing.
종래의 워드라인(비트라인)의 패터닝 크기를 감소시키는 방법으로는 포토리소그래피공정으로 가능한 포토레지스트 패턴을 형성하고, 이것을 건식식각을 통해 등방성 식각함으로써 포토레지스트의 패턴 크기를 물리적으로 감소시킨 후, 그 감소된 포토레지스트 패턴을 사용하여 워드라인(비트라인)을 패터닝하는 방법이 사용되어 왔다. 그러나 이 방법은 포토레지스트의 손실을 감수해야 하므로 후속의 게이트 하드마스크 건식식각이나 게이트물질의 건식식각에서 충분한 포토레지스트를 확보하는 것이 어려워지고, 포토레지스트 손상으로 인한 라인 충실도(line fidelity)의 악화를 동반하게 되는 단점이 있다.A conventional method of reducing the patterning size of word lines (bit lines) is to form a photoresist pattern possible by a photolithography process, and physically reduce the pattern size of the photoresist by isotropically etching it through dry etching. A method of patterning wordlines (bitlines) using reduced photoresist patterns has been used. However, this method requires a loss of photoresist, which makes it difficult to secure sufficient photoresist in subsequent gate hardmask dry etching or dry etching of gate material, and deteriorates line fidelity due to photoresist damage. There are drawbacks to accompany it.
본 발명은 상기 문제점을 해결하기 위한 것으로써, 희생산화막과 희생 로우-k(low-k)막을 이용하여 게이트라인 및 비트라인의 폭을 감소시키는 방법을 제공하는데 목적이 있다.An object of the present invention is to provide a method of reducing the width of a gate line and a bit line by using a sacrificial oxide film and a sacrificial low-k film.
도1 내지 도9는 본 발명의 일실시예에 의한 희생산화막을 이용한 게이트 형성방법을 나타낸 공정순서도.1 to 9 are process flowcharts showing a gate forming method using a sacrificial oxide film according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 게이트 물질층 2 : 희생산화막1: gate material layer 2: sacrificial oxide film
2A,2B : 희생산화막 패턴 3 : 포토레지스트패턴2A, 2B: sacrificial oxide film pattern 3: photoresist pattern
4 : 로우-k막 5 : 트렌치4: low-k film 5: trench
6 : 하드마스크 질화막 6A : 게이트 하드마스크6: hard mask nitride film 6A: gate hard mask
상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 패터닝하고자 하는 도전층과 희생산화막을 차례로 형성하는 단계와; 상기 희생산화막 상부에 상기 도전층으로 형성하고자 하는 형상을 갖는 포토레지스트패턴을 형성하는 단계; 상기 포토레지스트패턴을 마스크로 이용하여 상기 희생산화막을 건식식각하는 단계; 상기 포토레지스트패턴을 제거하는 단계; 상기 건식식각에 의해 형성된 상기 희생산화막 패턴을 습식식각하여 상기 도전층으로 형성할 원하는 도전층 라인의 크기까지 희생산화막의 CD를 감소시키는 단계; 상기 CD가 감소된 희생산화막 패턴 상부에 폴리머 계열의 로우-k막을 도포하는 단계; 상기 로우-k막을 에치백하여 상기 희생산화막 패턴을 노출시키는 단계; 상기 노출된 희생산화막 패턴을 제거하여 상기 로우-k막에 트렌치를 형성하는 단계; 상기 로우-k막의 트렌치내에 매립되도록 게이트 하드마스크용 물질을 증착하는 단계; 상기 로우-k막이 노출되도록 상기 증착된 하드마스크용 물질층을 CMP하여 게이트 하드마스크를 형성하는 단계; 상기 노출된 로우-k막을 스트립하는 단계; 및 상기 질화막 하드마스크를 이용하여 상기 도전층을 건식식각하여 원하는 도전층 라인 패턴을 형성하는 단계를 포함하여 이루어진것을 특징으로 한다.The present invention for achieving the above object comprises the steps of sequentially forming a conductive layer to be patterned on the semiconductor substrate and the sacrificial oxide film; Forming a photoresist pattern having a shape to be formed as the conductive layer on the sacrificial oxide film; Dry etching the sacrificial oxide layer using the photoresist pattern as a mask; Removing the photoresist pattern; Wet etching the sacrificial oxide pattern formed by the dry etching to reduce the CD of the sacrificial oxide layer to a size of a desired conductive layer line to be formed as the conductive layer; Applying a polymer-based low-k film on the sacrificial oxide film pattern having the reduced CD; Etching back the low-k film to expose the sacrificial oxide film pattern; Forming a trench in the low-k film by removing the exposed sacrificial oxide pattern; Depositing a material for the gate hardmask to fill in the trench of the low-k film; CMPing the deposited hardmask material layer to form a gate hardmask to expose the low-k film; Stripping the exposed low-k film; And dry etching the conductive layer using the nitride film hard mask to form a desired conductive layer line pattern.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
본 발명은 패터닝하고자 하는 물질층, 예컨대 게이트 물질층 위에 있는 희생산화막을 리소그래피 해상력의 가능한 범위에서 포토레지스트 마스크로 패터닝한다. 이와 같이 형성된 희생산화막 패턴을 희석된 산화막 에쳔트(BOE)를 이용하여 습식식각하여 요구되는 게이트 크기로 축소시킨다. 이 축소된 희생산화막위에 폴리머 계열의 로우-k층을 코팅하고 에치백하여 희생산화막을 노출시킨다. 노출된 희생산화막을 습식식각으로 제거한 다음, 로우-k막 사이의 트렌치로 게이트 하드마스크로 사용될 질화막을 증착한다. 이어서 CMP공정으로 하드마스크 질화막을 분리한 후, 로우-k막을 제거하면 감소된 크기의 게이트 하드마스크 패턴을 얻을 수 있다. 이 하드마스크를 이용하여 게이트물질층을 식각함으로써 게이트라인의 크기를 감소시킨다.The present invention patterns a sacrificial oxide layer over a layer of material to be patterned, such as a gate material layer, into a photoresist mask in the range of lithographic resolution possible. The sacrificial oxide pattern thus formed is wet-etched using diluted oxide film etchant (BOE) to reduce the required gate size. A polymer-based low-k layer is coated and etched back on the reduced sacrificial oxide to expose the sacrificial oxide. The exposed sacrificial oxide film is removed by wet etching, and then a nitride film to be used as a gate hard mask is deposited into the trench between the low-k films. Subsequently, the hard mask nitride film is separated by the CMP process, and then the low-k film is removed to obtain a gate hard mask pattern having a reduced size. The hard mask is used to etch the gate material layer to reduce the size of the gate line.
본 발명은 패터닝된 희생산화막의 크기를 습식식각을 이용하여 축소시키는 방법으로 최종적으로 형성되는 게이트 크기를 조절하는 것이 가능하다.The present invention can control the size of the gate finally formed by reducing the size of the patterned sacrificial oxide layer using wet etching.
도1내지 도8을 참조하여 본 발명의 바람직한 실시예에 의한 게이트 형성공정을 설명한다.A gate forming process according to a preferred embodiment of the present invention will be described with reference to FIGS.
먼저, 도1에 나타낸 바와 같이 반도체기판상에 게이트 물질층(1)과 희생산화막(2)을 차례로 형성한 후, 그 위에 포토레지스트를 도포하고 포토리소그래피 공정을 통해 형성하고자 하는 게이트 형상을 갖는 포토레지스트패턴(3)을 형성한다. 상기 게이트 물질층은 폴리실리콘, 텅스텐, Ti, TiN, WSix, CoSix 등을 포함한 모든 전도체를 사용하는 것이 가능한다. 상기 희생산화막으로는 후속 화학적 습식식각으로 제거가능한 모든 종류의 산화막을 사용할 수 있으며, 그 두께는 후속 CMP공정과 최종 잔류되는 하드마스크 두께에서 요구되는 높이를 고려하여 1000-10000Å범위로 설정한다.First, as shown in FIG. 1, a gate material layer 1 and a sacrificial oxide film 2 are sequentially formed on a semiconductor substrate, and then a photoresist having a gate shape to be formed by applying a photoresist thereon and performing a photolithography process. The resist pattern 3 is formed. The gate material layer can use any conductor, including polysilicon, tungsten, Ti, TiN, WSix, CoSix, and the like. As the sacrificial oxide film, all kinds of oxide films that can be removed by subsequent chemical wet etching can be used, and the thickness thereof is set in the range of 1000-10000 Pa in consideration of the height required in the subsequent CMP process and the final remaining hard mask thickness.
이어서 도2에 나타낸 바와 같이 상기 포토레지스트패턴을 마스크로 이용하여 상기 희생산화막을 건식식각하여 희생산화막 패턴(2A)을 형성한다. 이때, 게이트물질층에서 식각정지시킨다. 이후, 상기 포토레지스트패턴은 제거한다.Next, as shown in FIG. 2, the sacrificial oxide film is dry-etched using the photoresist pattern as a mask to form the sacrificial oxide film pattern 2A. At this time, the etch stop is performed in the gate material layer. Thereafter, the photoresist pattern is removed.
다음에 도3에 나타낸 바와 같이 상기 희생산화막 패턴을 희석된 산화막 에쳔트(희석된 HF 또는 BOE)를 사용하여 습식식각하여 요구되는 게이트라인 크기까지 희생산화막의 CD를 감소시킨다. 이때, 습식식각 시간을 조절하여 희생산화막패턴(2B)의 크기 조절이 가능하므로 후속 형성될 게이트 하드마스크의 크기를 조절할 수 있다. 희생산화막 패턴의 크기 감소를 위해 사용하는 케이컬은 산화막 식각이 가능한 모든 케미컬을 적용할 수 있으며, 식각속도 조절을 위한 모든 희석비율을 적용할 수 있다. 예를 들면, 300:1 BOE, 200:1 BOE, 9:1 BOE, 200:1 HF, 50:1 HF 등을 적용할 수 있다.Next, as shown in FIG. 3, the sacrificial oxide pattern is wet-etched using diluted oxide etchant (diluted HF or BOE) to reduce the CD of the sacrificial oxide layer to the required gate line size. In this case, since the size of the sacrificial oxide pattern 2B may be adjusted by adjusting the wet etching time, the size of the gate hard mask to be subsequently formed may be adjusted. Caical used to reduce the size of the sacrificial oxide pattern can be applied to all chemicals capable of etching the oxide, all dilution ratio for the etching rate can be applied. For example, 300: 1 BOE, 200: 1 BOE, 9: 1 BOE, 200: 1 HF, 50: 1 HF, and the like can be applied.
이어서 도4에 나타낸 바와 같이 크기가 감소된 희생산화막 패턴(2B) 상부에 폴리머 계열의 로우-k막(4)을 도포한 후, 에치백하여 희생산화막 패턴(2B)을 노출시킨다. 상기 로우-k막으로는 SOG, SilK, BCB, FLARE 등을 사용할 수 있다.Subsequently, as shown in FIG. 4, the polymer-based low-k film 4 is coated on the reduced sized sacrificial oxide pattern 2B, and then etched back to expose the sacrificial oxide pattern 2B. SOG, SilK, BCB, FLARE, etc. may be used as the low-k film.
다음에 도5에 나타낸 바와 같이 상기 노출된 희생산화막 패턴을 화학적 습식식각을 통해 제거하여 로우-k막에 트렌치(5)를 형성한다.Next, as shown in FIG. 5, the exposed sacrificial oxide pattern is removed through chemical wet etching to form a trench 5 in the low-k film.
이어서 도6에 나타낸 바와 같이 상기 형성된 로우-k막의 트렌치내에 매립되도록 게이트 하드마스크용 질화막(6)을 증착한다. 게이트 하드마스크용 물질로는 질화막 이외에도 후속 공정의 요구사항에 따라 희생막 제거시 선택비를 가질 수 있고 CMP가 가능한 모든 절연막, 예컨대 산화막, SiON막 등을 사용할 수 있다.Next, as shown in Fig. 6, a nitride film 6 for a gate hard mask is deposited so as to be embedded in the trench of the formed low-k film. As the gate hard mask material, any insulating film capable of having a selectivity for removing a sacrificial film and a CMP capable, for example, an oxide film and a SiON film, may be used in addition to the nitride film.
다음에 도7에 나타낸 바와 같이 상기 로우-k막이 노출될 때까지 상기 질화막의 CMP(chemical mechanical polishing)를 진행하여 질화막 하드마스크(6A)를 형성한다.Next, as shown in FIG. 7, a CMP (chemical mechanical polishing) of the nitride film is performed until the low-k film is exposed to form a nitride film hard mask 6A.
이어서 도8에 나타낸 바와 같이 CMP공정을 통해 노출된 폴리머 계열의 로우-k막을 스트립하여 질화막 하드마스크(6A)만을 남긴다. 이때, 고밀도 또는 중간 밀도 플라즈마 방식의 식각반응기에서 산소계 가스(oxygen-based gas chemistry)를 이용하여 건식식각한다. 이러한 식각조건은 일반적인 CVD 또는 PVD막에 대하여 거의 무한대의 선택비를 가지므로 하드마스크 질화막(6A)이나 게이트물질에 손상을 주지않으면서 로우-k막을 스트립하는 것이 가능하다. 상기 식각공정에서 사용 가능한 가스 조합으로는 O2/N2/CH4, O2/N2 또는 O2/CO 등이 있다.Subsequently, as shown in FIG. 8, the polymer-based low-k film is stripped through the CMP process to leave only the nitride hard mask 6A. In this case, dry etching is performed using an oxygen-based gas chemistry in an etching reactor of a high density or medium density plasma method. Since the etching conditions have an almost infinite selectivity with respect to the general CVD or PVD film, it is possible to strip the low-k film without damaging the hard mask nitride film 6A or the gate material. Gas combinations usable in the etching process include O 2 / N 2 / CH 4, O 2 / N 2, or O 2 / CO.
다음에 도9에 나타낸 바와 같이 상기 형성된 질화막 하드마스크(6A)를 이용하여 상기 게이트 물질층을 건식식각하여 크기가 감소된 게이트(1A)를 형성한다.Next, as shown in FIG. 9, the gate material layer is dry-etched using the formed nitride film hard mask 6A to form a gate 1A having a reduced size.
본 발명은 상기한 게이트라인 이외에도 비트라인을 비롯한 모든 라인 패턴에적용이 가능하다.The present invention can be applied to all line patterns including bit lines in addition to the gate lines described above.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 디바이스의 해당 선폭에서 포토리소그래피공정의 해상력 한계를 극복하고 게이트 라인(워드라인 및 비트라인) 크기의 감소를 가능하게 함으로써 후속 공정 마진과 접촉면적 확보 측면에서 효과적으로 기여한다. 이에 따라 디바이스 제조시의 수율이 향상되어 경제적인 효과를 얻을 수 있다.The present invention effectively contributes in terms of securing subsequent contact margins and contact area by overcoming the resolution limitations of the photolithography process at the corresponding line width of the device and enabling reduction of gate line (wordline and bitline) size. Thereby, the yield at the time of device manufacture is improved and an economic effect can be acquired.
또한, 기존의 게이트라인 패턴의 크기를 감소시키는 방법인 포토레지스트를 손상시키는 기술에서 발생하는 패턴 충실도(pattern fidelity) 감소와 후속 건식식각공정에서의 포토레지스트 부족현상을 피할 수 있어 양호한 게이트라인을 확보하는 것이 가능하다.In addition, it is possible to reduce the pattern fidelity caused by the technique of damaging the photoresist, which is a method of reducing the size of the existing gate line pattern, and to avoid the photoresist shortage in the subsequent dry etching process, thereby ensuring a good gate line. It is possible to do
또한, 형성된 희생산화막 패턴을 습식식각을 이용하여 그 크기를 감소시키는 방법을 통해 게이트 하드마스크 크기의 조절이 가능하므로 습식식각 시간을 증감하여 요구되는 게이트 크기를 쉽게 얻을 수 있다.In addition, the size of the gate hard mask may be adjusted by a method of reducing the size of the formed sacrificial oxide layer pattern using wet etching, so that the required gate size may be easily obtained by increasing or decreasing the wet etching time.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100695434B1 (en) * | 2006-02-28 | 2007-03-16 | 주식회사 하이닉스반도체 | Method for forming micro pattern of semiconductor device |
| KR100714477B1 (en) * | 2005-12-07 | 2007-05-07 | 삼성전자주식회사 | Fabrication method for semiconductor integrated circuit device |
| KR100835103B1 (en) * | 2004-08-27 | 2008-06-03 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device |
| KR100905181B1 (en) * | 2007-10-31 | 2009-06-29 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| US7804716B2 (en) | 2007-08-03 | 2010-09-28 | Samsung Electronics Co., Ltd. | Flash memory device having improved bit-line layout and layout method for the flash memory device |
| CN102509698A (en) * | 2011-11-23 | 2012-06-20 | 北京大学 | Method for preparing superfine wire |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100835103B1 (en) * | 2004-08-27 | 2008-06-03 | 동부일렉트로닉스 주식회사 | Manufacturing method of semiconductor device |
| KR100714477B1 (en) * | 2005-12-07 | 2007-05-07 | 삼성전자주식회사 | Fabrication method for semiconductor integrated circuit device |
| KR100695434B1 (en) * | 2006-02-28 | 2007-03-16 | 주식회사 하이닉스반도체 | Method for forming micro pattern of semiconductor device |
| US7804716B2 (en) | 2007-08-03 | 2010-09-28 | Samsung Electronics Co., Ltd. | Flash memory device having improved bit-line layout and layout method for the flash memory device |
| KR100905181B1 (en) * | 2007-10-31 | 2009-06-29 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
| CN102509698A (en) * | 2011-11-23 | 2012-06-20 | 北京大学 | Method for preparing superfine wire |
| WO2013138276A1 (en) * | 2012-03-12 | 2013-09-19 | Advanced Technology Materials, Inc. | Methods for the selective removal of ashed spin-on glass |
| CN104488068A (en) * | 2012-03-12 | 2015-04-01 | 安格斯公司 | Methods for the selective removal of ashed spin-on glass |
| CN104488068B (en) * | 2012-03-12 | 2019-02-12 | 恩特格里斯公司 | The method of selective removal ashing spin-coating glass |
| KR20210018976A (en) * | 2012-03-12 | 2021-02-18 | 엔테그리스 아시아 엘엘씨 | Methods for the selective removal of ashed spin-on glass |
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