KR20030001084A - Method for forming pattern of semiconductor device - Google Patents
Method for forming pattern of semiconductor device Download PDFInfo
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- KR20030001084A KR20030001084A KR1020010037414A KR20010037414A KR20030001084A KR 20030001084 A KR20030001084 A KR 20030001084A KR 1020010037414 A KR1020010037414 A KR 1020010037414A KR 20010037414 A KR20010037414 A KR 20010037414A KR 20030001084 A KR20030001084 A KR 20030001084A
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- pattern
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000005498 polishing Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000007261 regionalization Effects 0.000 claims abstract 2
- 239000000126 substance Substances 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 2
- 230000018109 developmental process Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 20
- 238000000206 photolithography Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 워드라인, 비트라인과 같은 반도체소자의 패턴(pattern)의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a pattern of semiconductor devices such as word lines and bit lines.
일반적으로 반도체소자 제조시 워드라인, 비트라인, 게이트전극과 같은 패턴(pattern) 형성은 포토리소그래피(photolithography) 공정을 적용한다.In general, when the semiconductor device is manufactured, patterns such as word lines, bit lines, and gate electrodes are applied to a photolithography process.
최근에 반도체 소자의 디자인룰(design rule)이 감소에 따라 해당 선폭(pitch)에서 패턴의 패터닝 사이즈(patterning size)를 감소시키는 것이 요구되고 있다.Recently, as the design rule of a semiconductor device decreases, it is required to reduce the patterning size of a pattern at a corresponding pitch.
해당 선폭(pitch)에서 패턴의 패터닝 크기를 감소시키는 이유는, 선폭의 종횡비(aspect ratio)를 완화시켜 후속 층간절연막(Inter Layer Dielectric; ILD) 증착 공정의 갭필 마진(gapfill margin)을 향상시킬 수 있기 때문이다.The reason for reducing the patterning size of the pattern at the corresponding pitch is that the aspect ratio of the line width can be alleviated to improve the gapfill margin of the subsequent inter-layer dielectric (ILD) deposition process. Because.
또한, 라인/스페이스(Line/Space; L/S) 증가로 인한 활성영역, 플러그패드 등의 하부층과의 접촉 면적을 증가시켜 셀 메모리 콘택의 접촉저항을 향상시킬 수 있기 때문이다.In addition, the contact resistance of the cell memory contact can be improved by increasing the contact area with the lower layer such as the active region and the plug pad due to the increase in the line / space (L / S).
종래 워드라인과 같은 패턴의 패터닝 크기를 감소시키는 방법으로는, 도 1에 도시된 바와 같이, 패턴이 형성될 도전막(11)상에 감광막을 도포한 후, 포토리소그래피 공정으로 감광막 패턴(12a)을 형성하고, 감광막 패턴(12a)을 건식식각 공정을 통해 등방성 식각하므로써 감광막 패턴(12a)의 크기를 물리적으로 감소시킨 후, 크기가 감소된 감광막 패턴(12b)을 이용하여 도전막(11)을 패터닝하는 방법이 사용되었다.As a method of reducing the patterning size of a pattern such as a conventional word line, as shown in FIG. 1, after the photosensitive film is coated on the conductive film 11 on which the pattern is to be formed, the photosensitive film pattern 12a is subjected to a photolithography process. After physically reducing the size of the photoresist pattern 12a by isotropic etching the photoresist pattern 12a through a dry etching process, the conductive film 11 is formed using the reduced photoresist pattern 12b. Patterning method was used.
그러나, 패턴 사이의 스페이스(space)를 증가시키는 것은 포토리소그래피의해상력(resolution) 한계로 불가능하고, 감광막의 손실(A)을 감수해야 하므로 후속 게이트 하드마스크(Hard Mask; HM)의 건식식각이나 게이트의 건식식각에서 충분한 감광막 두께를 확보하는 것이 어려워지고, 감광막 어택(attack)으로 인한 라인 충실도(line fidelity)의 악화를 수반하는 문제점이 있다.However, increasing the space between the patterns is not possible due to the resolution limitation of photolithography, and the loss of the photoresist film (A), so dry etching or gate etching of the subsequent gate hard mask (HM) It is difficult to secure sufficient photoresist thickness in dry etching, and there is a problem accompanied by deterioration of line fidelity due to photoresist attack.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 포토리소그래피 공정의 해상력 한계를 극복하고 감광막 어택으로 인한 라인 패턴의 충실도 악화를 방지하면서 패턴의 크기를 확보하는데 적합한 반도체소자의 패턴 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and overcomes the limitations of the resolution of the photolithography process and prevents the deterioration of the fidelity of the line pattern due to the photoresist attack. The purpose is to provide a method.
도 1은 종래기술에 따른 패턴 형성 방법을 간략히 도시한 도면,1 is a view briefly showing a pattern forming method according to the prior art,
도 2a 내지 도 2f는 본 발명의 실시예에 따른 게이트패턴의 형성 방법을 도시한 공정 단면도.2A to 2F are cross-sectional views illustrating a method of forming a gate pattern according to an exemplary embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film
23a : 게이트패턴 24a : 희생막패턴23a: gate pattern 24a: sacrificial layer pattern
25 : 감광막 26 : 스페이서 절연막25 photosensitive film 26 spacer insulating film
27 : 스페이서 28 : 하드마스크27: spacer 28: hard mask
29 : 하드마스크패턴29: hard mask pattern
상기의 목적을 달성하기 위한 반도체소자의 패턴 형성 방법은 반도체기판상에 도전층, 희생막을 차례로 형성하는 단계, 상기 희생막상에 감광막을 도포하고 노광 및 현상으로 패터닝하는 단계, 상기 패터닝된 감광막을 마스크로 하여 상기 희생막을 식각하여 다수의 희생막패턴을 형성하는 단계, 상기 희생막패턴의 양측벽에 스페이서를 형성하는 단계, 상기 스페이서가 형성된 희생막패턴을 포함한 전면에 하드마스크를 형성하는 단계, 상기 희생막패턴의 표면이 노출될때까지 상기 하드마스크를 화학적기계적연마하는 단계, 상기 희생막패턴 및 스페이서를 제거하는 단계, 및 상기 하드마스크를 마스크로 하여 상기 도전층을 식각하는 단계를 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, a method of forming a pattern of a semiconductor device may include forming a conductive layer and a sacrificial film on a semiconductor substrate, applying a photoresist film on the sacrificial film, and patterning the photosensitive film by exposure and development, and masking the patterned photoresist film. Forming a plurality of sacrificial layer patterns by etching the sacrificial layer, forming spacers on both side walls of the sacrificial layer pattern, and forming a hard mask on the entire surface including the sacrificial layer pattern on which the spacers are formed. Chemically polishing the hard mask until the surface of the sacrificial film pattern is exposed, removing the sacrificial film pattern and the spacer, and etching the conductive layer using the hard mask as a mask. It features.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2f는 본 발명의 실시예에 따른 반도체소자의 패턴 형성 방법을 도시한 공정 단면도로서, 게이트패턴의 형성 방법을 도시하고 있다.2A through 2F are cross-sectional views illustrating a method of forming a pattern of a semiconductor device in accordance with an embodiment of the present invention, and illustrate a method of forming a gate pattern.
도 2a에 도시된 바와 같이, 반도체기판(21)상에 게이트산화막(22)을 형성한 후, 게이트산화막(22)상에 게이트 도전막(23)을 증착한다. 이 때, 게이트 도전막(23)은 폴리실리콘(polysilicon), 텅스텐(W), 티타늄(Ti), 티타늄나이트라이드(TiN), 텅스텐실리사이드(WSi2), 코발트실리사이드(CoSi2) 중에서 선택된다.As shown in FIG. 2A, after the gate oxide film 22 is formed on the semiconductor substrate 21, the gate conductive film 23 is deposited on the gate oxide film 22. In this case, the gate conductive layer 23 is selected from polysilicon, tungsten (W), titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi 2 ), and cobalt silicide (CoSi 2 ).
계속해서, 게이트 도전막(23)상에 희생막(24)을 증착한 후, 희생막(24)상에 감광막을 도포한다.Subsequently, after the sacrificial film 24 is deposited on the gate conductive film 23, a photosensitive film is coated on the sacrificial film 24.
여기서, 희생막(24)은 케미컬 습식에 의해 스트립 가능한 종류의 산화막이나, 저유전율(low-k)을 갖는 절연막을 이용하되, 희생막(24)은 후속 화학적기계적연마 공정과 최종 잔류 하드마스크의 두께에서 요구되는 높이를 고려하여 1000Å∼10000Å 두께로 증착된다.Here, the sacrificial film 24 may be an oxide film of a strippable type by chemical wet, or an insulating film having a low dielectric constant (low-k). The sacrificial film 24 may be formed by a subsequent chemical mechanical polishing process and a final residual hard mask. In consideration of the height required in the thickness, it is deposited to a thickness of 1000 kPa to 10,000 kPa.
한편, 희생막(24)으로 적용 가능한 저유전율 절연막은 FSG, 카르보나도(carbonado 또는 black diamond)와 같은 화학기상증착(Chemical Vapor Deposition; CVD)계 절연막, HSQ, HOSP 등의 H 또는 C-도우프드계 절연막, 또는SiLK, BCB, FLARE 등의 폴리머계 SOG막 중에서 선택된다.Meanwhile, the low dielectric constant insulating film applicable to the sacrificial film 24 may be a chemical vapor deposition (CVD) -based insulating film such as FSG, carbonado or black diamond, or H or C-dough such as HSQ and HOSP. Or a polymer SOG film such as SILK, BCB, or FLARE.
다음으로, 감광막을 노광 및 현상으로 패터닝하여 감광막패턴(25)을 형성하되, 게이트패턴 형성을 위한 설정된 감광막과는 다르게 네가티브톤(negative tone)으로 패터닝한다. 즉, 게이트패턴이 형성될 부분을 노출시키는 감광막패턴을 형성한다.Next, the photoresist film is patterned by exposure and development to form the photoresist pattern 25, but patterned with a negative tone different from the set photoresist film for forming the gate pattern. That is, a photoresist pattern is formed to expose a portion where the gate pattern is to be formed.
도 2b에 도시된 바와 같이, 감광막패턴(25)을 마스크로 하여 희생막(24)을 식각하여 희생막패턴(24a)을 형성한 후, 감광막패턴(25)을 제거하고 희생막패턴(24a)을 포함한 전면에 스페이서 절연막(26)을 증착한다.As shown in FIG. 2B, after the sacrificial layer 24 is etched using the photoresist layer 25 as a mask to form the sacrificial layer pattern 24a, the photoresist layer pattern 25 is removed and the sacrificial layer pattern 24a is removed. Depositing a spacer insulating film 26 on the front surface including.
여기서, 스페이서 절연막(26)은 후속 케미컬을 이용한 습식스트립으로 제거 가능한 모든 절연막을 이용하며, 스페이서 절연막(26)은 게이트패턴의 크기를 고려하여 50Å∼1000Å의 두께로 증착된다. 그리고, 스페이서 절연막(26)의 증착 두께를 이용하여 희생막패턴(24a) 사이의 스페이스가 조절가능하므로 후속 증착될 하드마스크의 크기(폭)를 제어할 수 있다Here, the spacer insulating film 26 uses all insulating films that can be removed by a wet strip using subsequent chemicals, and the spacer insulating film 26 is deposited to have a thickness of 50 mV to 1000 mV in consideration of the size of the gate pattern. In addition, since the space between the sacrificial layer patterns 24a is adjustable using the deposition thickness of the spacer insulating layer 26, the size (width) of the hard mask to be subsequently deposited may be controlled.
도 2c에 도시된 바와 같이, 스페이서 절연막(26)을 전면 식각하여 희생막패턴(24a)의 양측벽에 접하는 스페이서(27)를 형성한 후, 전면에 하드마스크(28)를 증착한다. 여기서, 하드마스크(28)는 희생막제거시 선택비를 가지며 화학적기계적연마가 가능한 모든 절연막을 이용하는데, 예컨대, 질화막, 산화막, SiON 중에서 선택된다. 바람직하게는, 후속 자기정렬콘택시 배리어막으로 이용하기 위해서 질화막을 이용한다.As illustrated in FIG. 2C, the spacer insulating layer 26 is etched to the entire surface to form a spacer 27 in contact with both sidewalls of the sacrificial layer pattern 24a, and then a hard mask 28 is deposited on the entire surface. Here, the hard mask 28 uses all insulating films having a selectivity when removing the sacrificial film and capable of chemical mechanical polishing, for example, selected from nitride, oxide, and SiON. Preferably, a nitride film is used for use as a barrier film in subsequent self-aligned contacts.
도 2d에 도시된 바와 같이, 희생막패턴(24a)의 표면이 드러날때까지 화학적기계적연마를 실시하여 스페이서(27)가 접하는 희생막패턴(24a) 사이에만 하드마스크패턴(29)을 잔류시킨다.As illustrated in FIG. 2D, the chemical mask is subjected to chemical mechanical polishing until the surface of the sacrificial layer pattern 24a is exposed, thereby leaving the hard mask pattern 29 only between the sacrificial layer pattern 24a that the spacer 27 contacts.
도 2e에 도시된 바와 같이, 희생막패턴(24a) 및 스페이서(27)를 선택적으로 습식제거하여 하드마스크패턴(29)만을 잔류시킨다.As shown in FIG. 2E, the sacrificial film pattern 24a and the spacer 27 are selectively wet removed to leave only the hard mask pattern 29.
한편, 희생막패턴(24a)이 산화막인 경우에는 희생막패턴(24a)을 불산(HF)계 또는 BOE(Buffered Oxide Etchant)계 케미컬(chemical)을 사용하여 제거하며, 희생막패턴(24a)이 저유전율 절연막인 경우에는 희생막패턴(24a)을 모든 방식의 플라즈마 발생 반응기에서 산소계 가스 화학반응(oxygen-base gas chemistry)을 이용하여 제거한다. 이 때, 가능한 가스 화학반응 조합은 O2/N2/CH4, O2/N2, O2/SO2또는 O2/CO 중에서 선택된다.On the other hand, when the sacrificial film pattern 24a is an oxide film, the sacrificial film pattern 24a is removed by using hydrofluoric acid (HF) or buffered oxide (BOE) -based chemical, and the sacrificial film pattern 24a is removed. In the case of the low dielectric constant insulating film, the sacrificial film pattern 24a is removed by using an oxygen-based gas chemistry in all types of plasma generation reactors. At this time, the possible gas chemical reaction combination is selected from O 2 / N 2 / CH 4 , O 2 / N 2 , O 2 / SO 2 or O 2 / CO.
플라즈마 발생 반응기에서 제거하는 경우, 게이트 도전막(23)이 아닌 하드마스크(29)에 대한 어택없이 저유전율 절연막을 제거하는 것이 가능하다.In the case of removal in the plasma generation reactor, it is possible to remove the low dielectric constant insulating film without attacking the hard mask 29 rather than the gate conductive film 23.
도 2f에 도시된 바와 같이, 하드마스크패턴(29)을 마스크로 하여 게이트 도전막(23)을 건식식각하여 게이트패턴(23a)를 형성한다.As shown in FIG. 2F, the gate pattern 23a is dry-etched using the hard mask pattern 29 as a mask to form the gate pattern 23a.
상술한 본 발명의 실시예에서는 게이트패턴의 형성 방법에 설명하였으나, 본 발명은 워드라인, 비트라인 형성시에도 적용가능하다.In the above-described embodiment of the present invention, a method of forming a gate pattern has been described, but the present invention can be applied to word lines and bit lines.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 소자의 해당 선폭에서 포토리소그래피 공정의 해상력 한계를 극복하고 게이트의 라인 크기를 감소시킬 수 있으므로 후속 공정의 마진과 접촉면적을 충분히 확보하여 소자 제조의 수율을 향상시킬 수 있는 효과가 있다.As described above, the present invention can overcome the resolution limit of the photolithography process at the corresponding line width of the device and reduce the line size of the gate, thereby sufficiently securing the margin and contact area of the subsequent process, thereby improving the yield of device fabrication. It works.
그리고, 종래 감광막을 손실시키는 방법에서 발생하는 패턴 충실도 감소와 후속 건식식각 공정에서 감광막 부족 현상을 피할 수 있어 양호한 게이트패턴의 라인을 확보할 수 있는 효과가 있다.In addition, there is an effect of reducing the pattern fidelity generated in the conventional method of losing the photosensitive film and avoiding the photosensitive film shortage in the subsequent dry etching process, thereby securing a good gate pattern line.
또한, 스페이서 절연막의 두께를 조절하므로써 희생막패턴의 스페이스, 즉 후속 공정을 통한 하드마스크의 크기 조절이 가능하므로 요구되는 게이트의 크기를 용이하게 구현할 수 있는 효과가 있다.In addition, by adjusting the thickness of the spacer insulating film, it is possible to easily control the size of the space of the sacrificial film pattern, that is, the size of the hard mask through a subsequent process, thereby easily implementing the required gate size.
Claims (11)
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100714477B1 (en) * | 2005-12-07 | 2007-05-07 | 삼성전자주식회사 | Fabrication method for semiconductor integrated circuit device |
| US7855408B2 (en) | 2005-04-19 | 2010-12-21 | Samsung Electronics Co., Ltd. | Semiconductor device having fine contacts |
| CN106910677A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | Patterning process, the manufacturing method of semiconductor device being used for producing the semiconductor devices |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7855408B2 (en) | 2005-04-19 | 2010-12-21 | Samsung Electronics Co., Ltd. | Semiconductor device having fine contacts |
| US8242018B2 (en) | 2005-04-19 | 2012-08-14 | Samsung Electronics Co., Ltd. | Semiconductor device having fine contacts and method of fabricating the same |
| KR100714477B1 (en) * | 2005-12-07 | 2007-05-07 | 삼성전자주식회사 | Fabrication method for semiconductor integrated circuit device |
| CN106910677A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | Patterning process, the manufacturing method of semiconductor device being used for producing the semiconductor devices |
| CN106910677B (en) * | 2015-12-23 | 2020-12-18 | 中芯国际集成电路制造(上海)有限公司 | Patterning method for manufacturing semiconductor device, and semiconductor device manufacturing method |
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