KR20020056013A - Method for fabricating dual damascene - Google Patents
Method for fabricating dual damascene Download PDFInfo
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- KR20020056013A KR20020056013A KR1020000085294A KR20000085294A KR20020056013A KR 20020056013 A KR20020056013 A KR 20020056013A KR 1020000085294 A KR1020000085294 A KR 1020000085294A KR 20000085294 A KR20000085294 A KR 20000085294A KR 20020056013 A KR20020056013 A KR 20020056013A
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Abstract
Description
본 발명은 반도체소자에 대한 것으로, 특히 듀얼 다마센(Dual Damascene) 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a dual damascene.
종래 듀얼 다마센 형성방법에 대하여 설명하면 다음과 같다.Referring to the conventional dual damascene formation method as follows.
종래 듀얼 다마센 공정은 층간절연막의 저유전율화를 위해 유전상수가 작은 물질을 사용하는데, 이때 모노레이어(monolayer)의 경우 금속라인과 비아홀을 패터닝하기 위하여 식각선택비가 다른 물질(SiO2, SiON, Si3N4)을 식각스톱층으로 사용한다.In the conventional dual damascene process, a material having a low dielectric constant is used to lower the dielectric constant of an interlayer insulating layer. In the case of a monolayer, materials having different etching selectivities for patterning metal lines and via holes (SiO2, SiON, Si3N4) are used. ) As an etch stop layer.
이때 사용되는 식각스톱층은 유전상수가 작은 물질(k=2.5~2.7)에 비해 유전상수가 크므로(예: SiO2는 k가 2~4이고, Si3N4는 k가 약 7) 식각스톱층으로 사용시 전체적인 커패시턴스를 증가시키게 된다.In this case, the etch stop layer used has a larger dielectric constant than a material having a low dielectric constant (k = 2.5 to 2.7) (for example, SiO 2 is k is 2 to 4 and Si 3 N 4 is k is about 7). This will increase the overall capacitance.
이때 커패시턴스의 증가를 최소화하기 위해서는 식각스톱층의 두께를 얇게 하여야하는데, 상기 SiO2나 SiON이나 Si3N4는 식각 선택비(Etch Selectivity)를 높게하여야 함으로 트랜치 식각공정시 마진 확보가 어려운 점이 있다.In this case, in order to minimize the increase in capacitance, the thickness of the etch stop layer should be thin. Since SiO2, SiON, or Si3N4 must increase the etching selectivity, it is difficult to secure a margin during the trench etching process.
이와 같은 트랜치 식각공정시 난점을 개선하기 위해서 크리닝공정시 O2 플라즈마를 사용하고, 차후에 구리의 금속라인을 형성할 때 화학적 기계적 연마공정의 식각스톱층을 질화막으로 형성하는데, 이때도 유전율을 높이는 요인이 된다.In order to improve the difficulty in the trench etching process, O2 plasma is used in the cleaning process, and when the metal line of copper is subsequently formed, an etch stop layer of the chemical mechanical polishing process is formed of a nitride film. do.
상기와 같은 종래 듀얼 다마센 형성방법은 다음과 같은 문제가 있다.The conventional dual damascene formation method as described above has the following problems.
식각스톱층과 하드마스크를 SiON이나 Si3N4나 SiO2으로 형성하므로 커패시턴스가 높아서 RC 지연이 발생하고, 트랜치 식각시 공정 마진을 확보하기가 어렵다.Since the etch stop layer and the hard mask are formed of SiON, Si3N4 or SiO2, the capacitance is high, resulting in RC delay, and it is difficult to secure process margin during trench etching.
본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 커패시턴스를 낮춰서 RC 지연을 개선하고 식각시 공정 마진을 확보하기에 유리한 듀얼 다마센 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and in particular, it is an object of the present invention to provide a dual damascene formation method that is advantageous to lower the capacitance to improve the RC delay and secure the process margin during etching.
도 1a 내지 도 1g는 본 발명 실시예에 따른 듀얼 다마센 형성방법을 나타낸 공정단면도1A to 1G are cross-sectional views showing a process for forming dual damascene according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
11 : 제 1 질화막 12 : 제 1 층간절연막11: first nitride film 12: first interlayer insulating film
13 : 제 1 금속막 14 : 제 2 질화막13: first metal film 14 second nitride film
15 : 제 2 층간절연막 16 : 식각스톱층15: second interlayer insulating film 16: etching stop layer
17 : 제 1 반사방지막 18 : 제 1 감광막17: first antireflection film 18: first photosensitive film
19 : 제 3 층간절연막 20 : 하드마스크층19: third interlayer insulating film 20: hard mask layer
21 : 캡절연막 22 : 제 2 반사방지막21 cap insulation film 22 second antireflection film
23 : 제 2 감광막 24 : 베리어메탈층23: second photosensitive film 24: barrier metal layer
25 : 제 2 금속막25: second metal film
상기와 같은 목적을 달성하기 위한 본 발명 듀얼 다마센 형성방법은 제 1 금속막상에 베리어절연막을 형성하는 공정, 상기 베리어절연막상에 폴리머 계열인 제 1 층간절연막과 OSG(Organic Silicate Glass) 계열의 식각스톱층을 차례로 형성하는 공정, 상기 식각스톱층상에 제 1 반사방지막과 제 1 감광막을 차례로 형성하는 공정, 상기 제 1 감광막을 패터닝하여 이를 마스크로 상기 제 1 반사방지막을 식각하고 이어서 상기 식각스톱층을 부분식각하는 공정, 상기 제 1 감광막과 상기 제 1 반사방지막을 제거하는 공정, 상기 전면에 폴리머 계열인 제 2 층간절연막과 상기 OSG계열의 하드마스크을 차례로 형성하는 공정, 상기 하드마스크상에 캡절연막과 제 2 반사방지막과 제 2 감광막을 차례로 형성하는 공정, 상기 제 2 감광막을 패터닝하여 이를 마스크로 상기 제 2 반사방지막과 상기 캡절연막과 상기 하드마스크와 상기 제 2 층간절연막을 차례로 식각하고, 이어서 상기 식각스톱층의 부분식각된 폭만큼 상기 식각스톱층과 상기 제 1 층간절연막과 상기 베리어절연막을 식각하여 상기 제 1 금속막이 오픈되도록 이중 폭을 갖는 비아홀을 형성하는 공정, 상기 제 2 감광막과 상기 제 2 반사방지막과 상기 캡절연막을 제거하는 공정, 상기 비아홀내에 제 2 금속막을 형성하는 공정을 포함함을 특징으로 한다.The dual damascene formation method of the present invention for achieving the above object is a step of forming a barrier insulating film on the first metal film, the first interlayer insulating film and the OSG (Organic Silicate Glass) etching of the polymer based on the barrier insulating film A step of sequentially forming a stop layer, a step of sequentially forming a first antireflection film and a first photoresist film on the etch stop layer, and patterning the first photoresist film to etch the first antireflection film with a mask and then to the etch stop layer Partially etching the film, removing the first photoresist film and the first anti-reflection film, and sequentially forming a polymer-based second interlayer insulating film and a OSG-based hard mask on the front surface, and a cap insulating film on the hard mask. And sequentially forming a second anti-reflection film and a second photoresist film, patterning the second photoresist film, and using the second mask as a mask. The anti-reflection film, the cap insulating film, the hard mask, and the second interlayer insulating film are sequentially etched, and then the etch stop layer, the first interlayer insulating film, and the barrier insulating film are etched by the partially etched width of the etch stop layer. Forming a via hole having a double width such that the first metal film is opened; removing the second photoresist film, the second anti-reflection film, and the cap insulating film; and forming a second metal film in the via hole. It is done.
첨부 도면을 참조하여 본 발명 듀얼 다마센 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a dual damascene formation method of the present invention will be described.
도 1a 내지 도 1g는 본 발명 실시예에 따른 듀얼 다마센 형성방법을 나타낸공정단면도이다.1A to 1G are cross-sectional views illustrating a process for forming dual damascene according to an embodiment of the present invention.
본 발명 실시예에 따른 듀얼 다마센 형성방법은 도 1a에 도시한 바와 같이 기판(도면에 도시되지 않음)에 구리 확산베리어막으로 제 1 질화막(11)을 300~500Å의 두께로 증착한다.In the dual damascene formation method according to the embodiment of the present invention, as shown in FIG. 1A, the first nitride film 11 is deposited to a thickness of 300 to 500 kW over a copper diffusion barrier film on a substrate (not shown).
그리고 제 1 질화막(11)상에 유전상수(k)가 작은 유기(Organic)나 무기(Inorganic)의 제 1 층간절연막(12)을 증착한다.Then, an organic or inorganic first interlayer insulating film 12 having a small dielectric constant k is deposited on the first nitride film 11.
그리고 제 1 질화막(11)이 드러나도록 제 1 층간절연막(12)을 사진식각해서 제 1 콘택홀을 형성한다.The first interlayer insulating film 12 is photoetched to expose the first nitride film 11 to form a first contact hole.
이어서 제 1 콘택홀을 포함한 제 1 층간절연막(12)상에 베리어막으로 탄탈륨나이트라이드(도면에 도시되지 않았음)를 증착하고, 이후에 구리를 증착하여 화학적 기계적 연마공정으로 평탄화하여 제 1 콘택홀내에 제 1 금속막(13)을 형성하여서 싱글 다마센 구조를 형성한다.Subsequently, tantalum nitride (not shown) is deposited on the first interlayer insulating film 12 including the first contact hole as a barrier film, and then copper is deposited to be flattened by a chemical mechanical polishing process. The first metal film 13 is formed in the hole to form a single damascene structure.
이후에 제 1 금속막(13)을 포함한 제 1 층간절연막(12)상에 제 2 질화막(14)을 200~400Å의 두께로 증착한다.Thereafter, a second nitride film 14 is deposited on the first interlayer insulating film 12 including the first metal film 13 to a thickness of 200 to 400 Å.
다음에 도 1b에 도시한 바와 같이 제 1 금속막(13)과 차후에 형성될 제 2 금속막과의 절연을 위해서 제 2 질화막(14)상에 저유전상수를 갖는 폴리머계열의 제 2 층간절연막(15)을 5000~7000Å의 두께를 갖도록 증착한다.Next, as shown in FIG. 1B, a polymer-based second interlayer insulating film 15 having a low dielectric constant on the second nitride film 14 for insulation between the first metal film 13 and the second metal film to be formed later. ) Is deposited to have a thickness of 5000 ~ 7000Å.
이때 제 2 층간절연막(15)은 SiLK, BCB로 형성하고 차후에 비아홀 형성시 O2나 N2에 의한 식각이 용이한 물질로 형성한다.At this time, the second interlayer insulating film 15 is formed of SiLK and BCB, and is later formed of a material which is easily etched by O2 or N2 when forming via holes.
그리고 도 1c에 도시한 바와 같이 제 2 층간절연막(15)상에 OSG(OrganicSilica Glass)계열의 저유전상수를 갖는 물질로 식각스톱층(16)을 증착하고, 식각스톱층(16)상에 유기의 제 1 반사방지(Bottom Anti Reflective Coating)막(17)을 형성한다.As illustrated in FIG. 1C, an etch stop layer 16 is deposited on the second interlayer insulating layer 15 using a material having a low dielectric constant of OSG (Organic Silica Glass) series, and an organic layer is formed on the etch stop layer 16. A first anti-reflective coating film 17 is formed.
이때 식각스톱층(16)은 SiO2식각에 적용하는 플루오로카본으로 식각이 가능한 물질로써 HOSP나 블랙 다이아몬드(Black Diamond)나 코럴(Coral)을 1000~1500Å의 두께로 증착한다.In this case, the etch stop layer 16 is a fluorocarbon applied to SiO 2 etching, and as a material capable of etching, HOSP, black diamond, or coral is deposited to a thickness of 1000 to 1500 Å.
이때 차후에 트랜치 형성 및 비아홀 패터닝시 식각스톱층의 식각선택비가 낮을 경우 식각스톱층(16)의 두께가 높게 진행하여도 전체적인 유전율의 상승은 거의 없으므로 식각공정 마진을 넓혀줄수 있다.At this time, if the etching selectivity of the etch stop layer is low at the time of trench formation and via hole patterning, even if the thickness of the etch stop layer 16 proceeds high, the overall dielectric constant is hardly increased, thereby increasing the etching process margin.
그리고 상기에서 제 1 반사방지막(17)은 500~800Å의 두께를 갖도록 코팅한다.And the first anti-reflection film 17 is coated to have a thickness of 500 ~ 800Å.
이후에 도 1d에 도시한 바와 같이 제 1 반사방지막(17)상에 비아홀 형성 마스크로써 제 2 감광막(18)을 도포한다.Thereafter, as illustrated in FIG. 1D, a second photosensitive film 18 is coated on the first antireflection film 17 as a via hole forming mask.
그리고 노광 및 현상공정으로 감광막(18)을 선택적으로 패터닝하고, 패터닝된 제 1 감광막(18)을 마스크로 제 1 반사방지막(17)을 식각하고, 이후에 식각스톱층(16)이 일정 두께를 갖고 남도록 식각스톱층(16)을 부분 식각한다.The photoresist 18 is selectively patterned by an exposure and development process, and the first anti-reflection film 17 is etched using the patterned first photoresist 18 as a mask, and then the etch stop layer 16 has a predetermined thickness. The etch stop layer 16 is partially etched to remain.
이때 식각은 중이온밀도(middle ion density)(1×1011ion/㎤)를 갖는 장비를 사용하는데, 먼저 CF4/N2/Ar가스를 이용하여 제 1 반사방지막(17)을 식각하고, 연속으로(in-situ)로 C4F8/Ar/N2/CO가스로 식각스톱층(16)을 부분 식각한다.In this case, the etching is performed using a device having a middle ion density (1 × 10 11 ions / cm 3). First, the first anti-reflection film 17 is etched using CF 4 / N 2 / Ar gas, and then continuously ( in-situ) to partially etch the etch stop layer 16 with C4F8 / Ar / N2 / CO gas.
이때 식각스톱층(16)을 부분식각하는 이유는 차후에 제 1 감광막(18)을 제거하기 위해 O2 플라즈마를 진행할 때 노출된 폴리머계열의 제 2 층간절연막(15)이 식각됨으로서 후속의 제 2 금속막을 형성하기 위한 폴리머 계열의 저유전상수를 갖는 제 3 층간절연막을 증착할 때 채움성이 좋지않고, O2 플라즈마에 노출되면 산화 반응이 일어나서 카본 디플리션이 되어 유전상수값을 높임으로써 유전율 특성이 나빠지는 것을 방지하기 위함이다.The etch stop layer 16 may be partially etched because the second polymer interlayer insulating film 15 exposed during the O2 plasma is subsequently etched to remove the first photoresist film 18. When the third interlayer insulating film having a low dielectric constant of the polymer series to be formed is not deposited, the fillability is poor, and when exposed to O2 plasma, an oxidation reaction occurs, resulting in carbon depletion, resulting in a high dielectric constant, resulting in poor dielectric constant characteristics. To prevent this.
이후에 O2 플라즈마로 제 1 감광막(18)을 제거한다.Thereafter, the first photosensitive film 18 is removed with an O 2 plasma.
이때 제 1 감광막(18)의 제거는 OSG 계열의 식각스톱층(16)의 충격을 방지하여 유전율 특성을 개선하기 위해서 O2 라디칼(radical) 확산속도를 감소시키는 바이어스가 가해진 고밀도 플라즈마 장비에서 O2가스를 이용하여 진행한다.At this time, the removal of the first photoresist film 18 is to prevent the impact of the OSG-based etch stop layer 16 to improve the dielectric constant characteristics to reduce the O2 radical (radical diffusion rate) to increase the O2 gas in the high density plasma equipment Proceed with.
그리고 제 1 반사방지막(17)을 제거한다.Then, the first antireflection film 17 is removed.
다음에 도 1e에 도시한 바와 같이 식각스톱층(16)을 포함한 전면에 저유전상수를 갖는 폴리머계열의 제 3 층간절연막(19)을 4000~7000Å의 두께로 증착한다.Next, as illustrated in FIG. 1E, a third interlayer dielectric film 19 having a low dielectric constant on the entire surface including the etch stop layer 16 is deposited to a thickness of 4000 to 7000 Å.
그리고 저유전상수의 OSG 계열의 하드마스크층(20)과 캡산화막(21)과 유기의 제 2 반사방지막(22)과 제 2 감광막(23)을 차례로 증착한다.The OSG-based hard mask layer 20, the cap oxide film 21, the organic second antireflection film 22, and the second photoresist film 23 having low dielectric constants are sequentially deposited.
이때 제 3 층간절연막(19)은 SiLK나 BCB로 형성하고, 하드마스크층(20)은 HOSP나 블랙 다이아몬드나 코럴(Coral)을 1000~1500Å의 두께로 증착하고, 캡산화막(21)은 TEOS(Tetra Ethyl Ortho Silicate)나 USG(Undoped Silicate Glass)와 같은 막을 500~1000Å 형성하고, 제 2 반사방지막(22)은 500~1000Å의 두께를 갖는 BARC(Bottom Anti Reflective Coating)를 형성한다.At this time, the third interlayer insulating film 19 is formed of SiLK or BCB, the hard mask layer 20 is deposited HOSP, black diamond or coral (Coral) to a thickness of 1000 ~ 1500Å, the cap oxide film 21 is TEOS ( A film, such as Tetra Ethyl Ortho Silicate (UST) or Undoped Silicate Glass (USG), is formed at 500 to 1000 microns, and the second anti-reflective film 22 forms a Bottom Anti Reflective Coating (BARC) having a thickness of 500 to 1000 microns.
이후에 노광 및 현상공정으로 제 2 감광막(23)을 선택적으로 패터닝한다.Thereafter, the second photosensitive film 23 is selectively patterned by an exposure and development process.
다음에 도 1f에 도시한 바와 같이 패터닝된 감광막(23)을 마스크로 제 2 반사방지막(22)과 캡산화막(21)과 하드마스크층(20)과 제 3 층간절연막(19)과 식각스톱층(16)과 제 2 층간절연막(15)과 제 2 질화막(14)을 차례로 단일장비에서 연속으로(in-site) 식각하여서 제 2 콘택홀을 형성한다.Next, as shown in FIG. 1F, the second anti-reflection film 22, the cap oxide film 21, the hard mask layer 20, the third interlayer insulating film 19, and the etch stop layer are patterned using the patterned photosensitive film 23 as a mask. (16), the second interlayer insulating film 15 and the second nitride film 14 are sequentially in-site etched in a single device to form a second contact hole.
이때 제 2 콘택홀 식각은 중이온밀도(middle ion density)(1×1011ion/㎤)를 갖는 장비를 사용하는데, 먼저 CF4/N2/Ar가스를 이용하여 제 2 반사방지막(22)과 캡산화막(21)을 식각하고, 하드마스크층(20)은 CO를 이용해서 식각한다.In this case, the second contact hole etching uses a device having a middle ion density (1 × 10 11 ions / cm 3). First, the second anti-reflection film 22 and the cap oxide film are formed using CF 4 / N 2 / Ar gas. (21) is etched, and the hard mask layer 20 is etched using CO.
그리고 제 3 층간절연막(19)을 식각하는데, 이때 O2 플라즈마만을 이용하면 제 2 콘택홀 측벽의 제 3 층간절연막(19)이 산소계 활성종에 의해 산화되어 붕괴층이 형성된다.Then, the third interlayer insulating film 19 is etched. In this case, when only the O2 plasma is used, the third interlayer insulating film 19 on the sidewall of the second contact hole is oxidized by oxygen-based active species to form a decay layer.
그리고 이방성식각을 위한 입사이온 에너지가 불가피하기 때문에 하드마스크층(20)이 과도식각될 수 있다. 이와 같은 이유로 O2 대신에 유기막 식각 가스로서 N2를 이용한다.In addition, since the incident ion energy for anisotropic etching is inevitable, the hard mask layer 20 may be over-etched. For this reason, N2 is used as the organic film etching gas instead of O2.
이와 같이 N2를 이용하면 식각후 측벽이 산화될 염려가 없고 플라즈마 식각중의 활성종과 유기막의 반응성이 낮기 때문에 이방성 가공에 높은 이온에너지도 필요하지 않고, 하드마스크층(20)의 붕괴도 일어나지 않는다. 그러나 식각율이 낮다는 결점이 있다.As such, when N2 is used, there is no fear of oxidizing the sidewalls after etching, and since the reactivity between the active species and the organic layer during plasma etching is low, high ion energy is not required for anisotropic processing, and no collapse of the hard mask layer 20 occurs. . However, there is a drawback that the etching rate is low.
이에 따라서 식각율을 증가시키기 위해서 H2또는 NH3를 첨가하여 O2/H2/NH3또는 N2/H2를 이용하여서 제 3 층간절연막(19)을 식각한다.Accordingly, in order to increase the etching rate, the third interlayer insulating film 19 is etched using O 2 / H 2 / NH 3 or N 2 / H 2 by adding H 2 or NH 3.
상기의 식각으로 제 2 감광막(23)도 제거되고, 식각스톱층(16)과의 선택비를 약 20:1로 유지한다.The second photoresist film 23 is also removed by the etching, and the selectivity with the etch stop layer 16 is maintained at about 20: 1.
다음에 연속으로(in-situ) 비아홀 오픈을 위해 상기 부분식각된 식각스톱층(16)을 C4F8/Ar/N2/CO가스로 식각하고, 제 2 층간절연막(15)을 식각한다.The partially etched stop layer 16 is then etched with C 4 F 8 / Ar / N 2 / CO gas to in-situ open via holes, and the second interlayer insulating film 15 is etched.
그리고 구리로 구성된 제 1 금속막(13)의 확산 베리어막인 제 2 질화막(14)을 CHF3/Ar으로 제거하여서 제 1 금속막(13)이 오픈되도록 한다.Then, the second nitride film 14, which is a diffusion barrier film of the first metal film 13 made of copper, is removed with CHF3 / Ar so that the first metal film 13 is opened.
이때 제 2 층간절연막(15)과 제 2 질화막(14)을 식가할 때 식각스톱층(16)이 마스크 역할을 하여서 제 2 층간절연막(15)과 제 2 질화막(14)은 부분식각된 폭만큼만 식각된다.At this time, when the second interlayer insulating film 15 and the second nitride film 14 are etched, the etch stop layer 16 serves as a mask so that the second interlayer insulating film 15 and the second nitride film 14 are only partially etched in width. Etched.
이때 발생한 폴리머를 제거하기 위해 습식 크리닝을 실시한다.Wet cleaning is performed to remove the polymer generated at this time.
그리고 상기 제 2 반사방지막(22)과 캡절연막(21)을 제거한다.The second anti-reflection film 22 and the cap insulating film 21 are removed.
이후에 도 1g에 도시한 바와 같이 제 2 콘택홀과 하드마스크층(22)을 따라서 베리어메탈층(24)을 증착하고, 제 2 콘택홀을 채우도록 전면에 구리를 증착한 후 구리를 화학적 기계적 연마해서 제 2 콘택홀내에 제 2 금속막(25)을 형성한다.Thereafter, as shown in FIG. 1G, the barrier metal layer 24 is deposited along the second contact hole and the hard mask layer 22, and copper is deposited on the entire surface to fill the second contact hole. Polishing is performed to form the second metal film 25 in the second contact hole.
상기와 같은 본 발명 듀얼 다마센 형성방법은 다음과 같은 효과가 있다.The dual damascene formation method of the present invention as described above has the following effects.
듀얼 다마센을 형성하기 위해서 제 2, 제 3 층간절연막을 폴리머 계열의 물질로 형성하고, 그 사이에 식각스톱층을 OSG계열의 물질로 형성하여서 전체적으로금속막의 커패시턴스를 낮추어주므로써 RC(Resistance Capacitance) 지연현상을 개선하고, 식각스톱층과 하드마스크의 두께를 두껍게 형성하므로써 식각 선택비에 대한 마진 확보를 용이하게 하면서 식각 효율을 높일 수 있다.In order to form dual damascene, second and third interlayer insulating films are formed of a polymer-based material, and an etch stop layer is formed of an OSG-based material therebetween, thereby lowering the capacitance of the metal film as a whole, thereby reducing RC (Resistance Capacitance). By improving the delay and forming a thick thickness of the etch stop layer and the hard mask, it is possible to increase the etching efficiency while facilitating securing the margin for the etching selectivity.
Claims (6)
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100527568B1 (en) * | 2003-10-27 | 2005-11-09 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
| KR100558493B1 (en) * | 2003-12-03 | 2006-03-07 | 삼성전자주식회사 | method of of forming interconnection lines in a semiconductor memory device |
| US7098139B2 (en) | 2003-02-17 | 2006-08-29 | Renesas Technology Corp. | Method of manufacturing a semiconductor device with copper wiring treated in a plasma discharge |
| KR100819672B1 (en) * | 2006-06-16 | 2008-04-04 | 주식회사 하이닉스반도체 | Method for forming metal pattern of semiconductor device |
| KR101069167B1 (en) * | 2008-06-09 | 2011-09-30 | 주식회사 동부하이텍 | Method for forming metal line of semiconductor device |
| KR101138838B1 (en) * | 2009-12-28 | 2012-05-10 | 에스케이하이닉스 주식회사 | Method for forming semiconductor device |
-
2000
- 2000-12-29 KR KR1020000085294A patent/KR100617076B1/en active IP Right Grant
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7098139B2 (en) | 2003-02-17 | 2006-08-29 | Renesas Technology Corp. | Method of manufacturing a semiconductor device with copper wiring treated in a plasma discharge |
| US7462565B2 (en) | 2003-02-17 | 2008-12-09 | Renesas Technology Corp. | Method of manufacturing semiconductor device |
| KR100527568B1 (en) * | 2003-10-27 | 2005-11-09 | 주식회사 하이닉스반도체 | Manufacturing method for semiconductor device |
| KR100558493B1 (en) * | 2003-12-03 | 2006-03-07 | 삼성전자주식회사 | method of of forming interconnection lines in a semiconductor memory device |
| KR100819672B1 (en) * | 2006-06-16 | 2008-04-04 | 주식회사 하이닉스반도체 | Method for forming metal pattern of semiconductor device |
| KR101069167B1 (en) * | 2008-06-09 | 2011-09-30 | 주식회사 동부하이텍 | Method for forming metal line of semiconductor device |
| KR101138838B1 (en) * | 2009-12-28 | 2012-05-10 | 에스케이하이닉스 주식회사 | Method for forming semiconductor device |
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