KR20030041550A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR20030041550A KR20030041550A KR1020010072383A KR20010072383A KR20030041550A KR 20030041550 A KR20030041550 A KR 20030041550A KR 1020010072383 A KR1020010072383 A KR 1020010072383A KR 20010072383 A KR20010072383 A KR 20010072383A KR 20030041550 A KR20030041550 A KR 20030041550A
- Authority
- KR
- South Korea
- Prior art keywords
- forming
- contact hole
- storage node
- insulating film
- semiconductor device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 239000011229 interlayer Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims abstract description 37
- 238000003860 storage Methods 0.000 claims abstract description 27
- 125000006850 spacer group Chemical group 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 229920005591 polysilicon Polymers 0.000 description 18
- 238000007789 sealing Methods 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000005498 polishing Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 워드라인과 스토리지노드콘택간 숏트를 억제하도록 한 반도체소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to suppress a short between a word line and a storage node contact.
최근의 반도체소자는 소자의 집적도가 증가함에 따라 메모리 셀 크기가 점점 감소되면서 워드라인과 캐패시터 콘택, 비트라인과 캐패시터 콘택의 마진이 점점 작아져 캐패시터 콘택을 더욱 작게 형성해야만 한다.In recent years, as the integration of devices increases, the size of memory cells decreases gradually, so that margins of word lines and capacitor contacts, bit lines and capacitor contacts become smaller, and thus capacitor capacitors must be made smaller.
또한, 반도체 집적회로가 고집적화됨에 따라 다수의 배선층 또는 콘택홀 사이의 미스얼라인 마진(mis-align margin)이 점점 줄어들고 있다. 더욱이, 반도체 메모리셀과 같이 디자인 룰(design rule)에 여유가 없고 같은 형태의 패턴이 반복되는 경우, 콘택홀을 자기정렬(self-align) 방식으로 형성함으로써 메모리셀의 면적을 축소시키는 방법이 연구개발되었다. 이는 주변구조물의 단차를 이용하여 콘택홀을 형성하는 것으로, 주변구조물의 높이, 콘택홀이 형성될 절연물질의 두께 및식각방법 등에 의해 다양한 크기의 콘택홀을 마스크 사용없이 얻을 수 있기 때문에 고집적화에 의해 미세화되는 반도체소자의 구현에 적합한 방법으로 사용된다.In addition, as semiconductor integrated circuits become highly integrated, mis-align margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, in the case where there is no room in a design rule like a semiconductor memory cell and a pattern of the same pattern is repeated, a method of reducing the area of the memory cell by forming a contact hole in a self-aligned manner is studied. Developed. This is to form a contact hole by using the step of the peripheral structure, the contact hole of various sizes can be obtained without using a mask by the height of the peripheral structure, the thickness of the insulating material to be formed and the etching method, etc. It is used in a method suitable for the implementation of the semiconductor device to be miniaturized.
도 1a 내지 도 1d는 종래기술에 따른 반도체소자의 제조 공정 단면도이다.1A to 1D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the prior art.
도 1a에 도시된 바와 같이, 반도체기판(11)에 트랜지스터의 소스/드레인(도시 생략)을 형성하고, 반도체기판(11)상에 게이트산화막(도시 생략)이 개재된 다수의 게이트패턴 즉, 워드라인(12)을 형성한다. 이 때, 워드라인(12)은 후속 콘택식각시 게이트가 식각되는 것을 방지하기 위한 제1식각방지막(12a)을 포함한다.As shown in FIG. 1A, a plurality of gate patterns, that is, words, are formed on a semiconductor substrate 11 with a source / drain (not shown) of a transistor and a gate oxide film (not shown) interposed on the semiconductor substrate 11. Line 12 is formed. In this case, the word line 12 includes a first etch stop layer 12a to prevent the gate from being etched during subsequent contact etching.
다음으로, 워드라인(12)을 포함한 전면에 폴리실리콘을 증착 및 화학적기계적연마하여 워드라인(12) 사이에 매립되는 제 1 폴리실리콘플러그(13)을 형성하고, 전면에 제 1 층간절연막(14)을 형성한다.Next, polysilicon is deposited and chemically mechanically polished on the entire surface including the word line 12 to form a first polysilicon plug 13 embedded between the word lines 12, and the first interlayer insulating layer 14 is formed on the front surface. ).
다음으로, 제 1 층간절연막(14)상에 제 2 식각방지막(15a)을 구비하는 비트라인(15)을 형성한 후, 제 2 식각방지막(15a)을 포함한 전면에 실링 질화막(sealing nitride)(16)을 형성한다. 이 때, 실링 질화막(16)은 비트라인(15)으로 이용되는 전도막, 예컨대 텅스텐과 후속 제 2 층간절연막이 직접 접촉하여 반응하는 것을 방지하기 위해 적용된다.Next, after the bit line 15 having the second etch stop 15a is formed on the first interlayer insulating film 14, a sealing nitride film (seal nitride) is formed on the entire surface including the second etch stop 15a. 16). At this time, the sealing nitride film 16 is applied to prevent the conductive film used as the bit line 15, for example, tungsten and the subsequent second interlayer insulating film from directly contacting and reacting.
다음으로, 실링질화막(16)을 포함한 전면에 제 2 층간절연막(17)을 형성한다.Next, a second interlayer insulating film 17 is formed on the entire surface including the sealing nitride film 16.
도 1b에 도시된 바와 같이, 제 2 층간절연막(17)상에 감광막을 이용한 콘택마스크(18)를 형성한 후, 콘택마스크(18)로 제2층간절연막(17), 실링 질화막(16), 제 1 층간절연막(14)을 순차적으로 식각하여 제 1 폴리실리콘플러그(13)의 표면을 노출시키는 콘택홀(19)을 형성한다. 이 때, 콘택홀(19) 형성은 자기정렬콘택식각이나 비트라인(15)이 노출되지 않은 통상적인 콘택식각 공정을 적용한다.As shown in FIG. 1B, after forming the contact mask 18 using the photosensitive film on the second interlayer insulating film 17, the second interlayer insulating film 17, the sealing nitride film 16, and the contact mask 18 are formed. The first interlayer insulating layer 14 is sequentially etched to form a contact hole 19 exposing the surface of the first polysilicon plug 13. At this time, the formation of the contact hole 19 uses a conventional contact etching process in which the self-aligned contact etching or the bit line 15 is not exposed.
도 1c에 도시된 바와 같이, 콘택마스크(18)를 제거한 후, 전면에 스페이서용 절연막을 증착 및 전면식각하여 콘택홀 형성후 드러난 비트라인(15) 및 제1층간절연막(14)의 식각부분의 양측벽에 스페이서(20)를 형성한다.As shown in FIG. 1C, after the contact mask 18 is removed, an insulating layer for spacers is deposited on the entire surface and then etched to form a contact hole, thereby forming an etching portion of the bit line 15 and the first interlayer insulating layer 14 exposed after the contact hole is formed. Spacers 20 are formed on both side walls.
도 1d에 도시된 바와 같이, 스페이서(20)를 포함한 전면에 폴리실리콘을 증착 및 화학적기계적연마 또는 에치백하여 콘택홀에 매립되는 제2폴리실리콘 플러그(이하 '스토리지노드콘택플러그'라 약칭함)(21)를 형성한다.As shown in FIG. 1D, a second polysilicon plug embedded in the contact hole by depositing and chemically mechanically polishing or etching back polysilicon on the front surface including the spacer 20 (hereinafter referred to as a storage node contact plug) 21 is formed.
도면에 도시되지 않았지만, 후속 공정으로 스토리지노드콘택플러그(21)를 통해 반도체기판(11)에 접속되며 하부전극, 유전막, 상부전극으로 이루어지는 캐패시터를 형성한다.Although not shown in the drawings, a capacitor connected to the semiconductor substrate 11 through the storage node contact plug 21 and formed of a lower electrode, a dielectric film, and an upper electrode is formed in a subsequent process.
상술한 종래기술에서는 스토리지노드콘택플러그를 형성하기 위한 콘택홀 형성후에 비트라인과 스토리지노드콘택플러그의 전기적 접속을 억제하기 위한 스페이서를 형성한다. 이는 스페이서 형성후 층간절연막을 증착하고 스토리지노드콘택플러그를 위한 콘택홀을 형성하는 경우에 발생되는 층간절연막의 보이드를 방지하기 위함이다. 여기서, 층간절연막 증착시 보이드가 발생되는 이유는 스페이서 형성후 비트라인 사이의 간격이 좁아져서 콘택홀의 종횡비가 커지기 때문이다.In the above-described prior art, after forming the contact hole for forming the storage node contact plug, a spacer for suppressing electrical connection between the bit line and the storage node contact plug is formed. This is to prevent voids of the interlayer insulating film generated when the interlayer insulating film is deposited after forming the spacer and the contact hole for the storage node contact plug is formed. The reason why voids are generated during the deposition of the interlayer insulating film is because the gap between the bit lines after the formation of the spacer is narrowed to increase the aspect ratio of the contact hole.
그러나, 상술한 종래기술에서는 스페이서를 콘택홀 형성후에 형성하므로 하부의 워드라인이 콘택 식각 공정 및 스페이서 형성 공정에 걸쳐 두 번의 어택을 받는 문제점이 있다.However, in the above-described prior art, since the spacer is formed after the contact hole is formed, there is a problem in that the lower word line receives two attacks through the contact etching process and the spacer forming process.
이러한 두 번의 어택은 워드라인을 보호해주는 식각방지막의 손실을 초래하여 워드라인이 드러나게 되고, 후속 증착되는 플러그 물질과 워드라인의 원하지 않는 전기적 연결이 발생하여 소자의 오동작을 유발시키는 문제가 있다.These two attacks cause the loss of the etch barrier that protects the word line, resulting in the word line being exposed, and the subsequent deposition of undesired electrical connections between the plug material and the word line, resulting in malfunction of the device.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 스토리지노드콘택플러그를 위한 콘택 식각 및 비트라인 스페이서 형성시의 워드라인 어택을 감소시키는데 적합한 반도체소자의 제조 방법을 제공하는데 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above-mentioned problems of the prior art, and provides a method of manufacturing a semiconductor device suitable for reducing a word line attack in forming a contact line and a bit line spacer for a storage node contact plug. have.
도 1a 내지 도 1d는 종래기술에 따른 반도체소자의 제조 방법을 도시한 공정 단면도,1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체소자의 제조 공정 단면도.2A through 2E are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
31 : 반도체기판 32 : 워드라인31: semiconductor substrate 32: word line
32a : 제 1 식각방지막 33 : 제 1 콘택플러그32a: first etching preventing film 33: first contact plug
34 : 제 1 층간절연막 35 : 비트라인34: first interlayer insulating film 35: bit line
35a : 제 2 식각방지막 36 : 실링질화막35a: second etching preventing film 36: sealing nitride film
37 : 제 2 층간절연막 38 : 콘택마스크37: second interlayer insulating film 38: contact mask
39 : 1차 콘택홀 40 : 스페이서39: primary contact hole 40: spacer
41 : 2차 콘택홀 42 : 스토리지노드 콘택플러그41: 2nd contact hole 42: Storage node contact plug
상기의 목적을 달성하기 위한 본 발명의 반도체소자의 제조 방법은 반도체기판상에 다수의 워드라인을 형성하는 단계, 상기 워드라인들 사이의 상기 반도체기판의 소정부분에 접속되는 제1플러그를 형성하는 단계, 상기 제1플러그를 포함한 전면에 제1층간절연막을 형성하는 단계, 상기 제1층간절연막상에 상기 워드라인과 교차하는 방향으로 다수의 비트라인을 형성하는 단계, 상기 비트라인을 포함한 전면에 식각정지막과 제2층간절연막을 차례로 형성하는 단계, 상기 식각정지막에서 식각이 멈추도록 상기 제2층간절연막을 식각하여 상기 비트라인 사이를 노출시키는 스토리지노드 콘택홀을 형성하는 단계, 상기 스토리지노드 콘택홀을 포함한 전면에 스페이서 절연막을 형성하는 단계, 상기 스페이서 절연막을 전면식각하여 상기 스토리지노드 콘택홀의 측벽에 스페이서를 형성함과 동시에 상기 스페이서 절연막의 전면식각시 상기 식각정지막과 상기 제1층간절연막을 동시에 식각하여 상기 제1플러그를 노출시키는 단계, 및 상기 노출된 제1플러그상에 제2플러그를 매립시키는 단계를 포함함을 특징으로 한다.A method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming a plurality of word lines on a semiconductor substrate, forming a first plug connected to a predetermined portion of the semiconductor substrate between the word lines Forming a first interlayer insulating film on the front surface including the first plug; forming a plurality of bit lines on the first interlayer insulating film in a direction crossing the word line; Forming an etch stop layer and a second interlayer dielectric layer in order, forming a storage node contact hole to expose the bit lines by etching the second interlayer dielectric layer to stop etching from the etch stop layer, the storage node Forming a spacer insulating film on the entire surface including the contact hole and etching the spacer insulating film on the entire surface of the storage node cone Forming a spacer on a sidewall of the hole and simultaneously etching the etch stop layer and the first interlayer insulating layer during the entire surface etching of the spacer insulating layer to expose the first plug, and a second on the exposed first plug And embedding the plug.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체소자의 제조방법을 도시한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 2a에 도시된 바와 같이, 반도체기판(31)에 트랜지스터의 소스/드레인(도시 생략)을 형성하고, 반도체기판(31)상에 게이트산화막(도시 생략)이 개재된 다수의 워드라인(32)을 형성한다. 이 때, 워드라인(32)은 후속 콘택식각시 워드라인이 식각되는 것을 방지하기 위한 제 1 식각방지막(32a)을 포함한다.As shown in FIG. 2A, a plurality of word lines 32 are formed on a semiconductor substrate 31 with a source / drain (not shown) of a transistor and a gate oxide film (not shown) interposed on the semiconductor substrate 31. To form. In this case, the word line 32 includes a first etch stop layer 32a for preventing the word line from being etched during subsequent contact etching.
다음으로, 워드라인(32)을 포함한 전면에 폴리실리콘을 증착 및 화학적기계적연마하여 워드라인(32) 사이에 매립되는 제 1 폴리실리콘플러그(33)를 형성하고, 전면에 제 1 층간절연막(34)을 형성한다.Next, polysilicon is deposited and chemically mechanically polished on the entire surface including the word line 32 to form a first polysilicon plug 33 embedded between the word lines 32 and the first interlayer insulating layer 34 on the front surface. ).
이 때, 제1폴리실리콘플러그(33)를 형성하는 방법은, 층간절연막 증착 및 콘택 식각으로 제1폴리실리콘플러그가 형성될 부분만을 노출시킨후 폴리실리콘증착 및 화학적기계적연마를 통해 워드라인 사이에 제1폴리실리콘플러그를 매립시키거나, 또는 폴리실리콘을 먼저 플러그패턴으로 식각한 후, 층간절연막 증착 및 화학적기계적연마를 통해 워드라인 사이에 제1폴리실리콘플러그를 매립시킬 수 있다.At this time, the method of forming the first polysilicon plug 33 exposes only the portion where the first polysilicon plug is to be formed by interlayer insulating film deposition and contact etching, and then, between the word lines through polysilicon deposition and chemical mechanical polishing. The first polysilicon plug may be embedded, or the polysilicon may be first etched into the plug pattern, and then the first polysilicon plug may be embedded between the word lines through interlayer dielectric deposition and chemical mechanical polishing.
다음으로, 제 1 층간절연막(34)상에 제2식각방지막(35a)을 구비하는 비트라인(35)을 형성한 후, 비트라인(35)을 포함한 전면에 실링 질화막(36)을 형성한다. 이 때, 실링질화막(36)은 비트라인(35)과 후속 제2층간절연막이 직접 접촉하여 반응하는 것을 방지하기 위해 50Å∼500Å의 두께로 형성되며, 실리콘질화막(SiN) 및실리콘산화질화막(SiON) 중에서 선택된 어느 하나를 이용한다.Next, after the bit line 35 including the second etch stop layer 35a is formed on the first interlayer insulating layer 34, the sealing nitride layer 36 is formed on the entire surface including the bit line 35. At this time, the sealing nitride film 36 is formed to have a thickness of 50 kV to 500 kV to prevent the bit line 35 and the subsequent second interlayer insulating film from directly contacting and reacting, and the silicon nitride film SiN and the silicon oxynitride film SiON. Use any one selected from).
여기서, 비트라인(35)으로는 텅스텐(W), 텅스텐실리사이드(WSi), 티타늄실리사이드(TiSi), 코발트실리사이드(CoSi), 알루미늄(Al), 구리(Cu) 및 폴리실리콘중에서 선택된 어느 하나를 이용한다.Here, the bit line 35 may be any one selected from tungsten (W), tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), aluminum (Al), copper (Cu), and polysilicon. .
그리고, 제2식각방지막(35a)으로는 제2층간절연막의 식각 과정에서 선택비를 가질 수 있는 모든 물질, 예컨대 제2층간절연막을 산화막계열을 사용하는 경우 실리콘질화막(SiN), 실리콘산화질화막(SiON)을 이용하고, 제2층간절연막을 저유전율계 또는 폴리머계를 사용하는 경우 산화막계열을 이용한다. 아울러, 제2식각방지막(35a)은 식각방지 역할과 후속 스토리지노드 콘택플러그와의 절연을 고려하여 500Å∼5000Å의 두께로 형성된다.As the second etch stop layer 35a, all materials which may have a selectivity in the etching process of the second interlayer insulating film, for example, when the second interlayer insulating film uses an oxide layer, a silicon nitride film (SiN), a silicon oxynitride film ( SiON), and an oxide film series is used when the second interlayer insulating film uses a low dielectric constant or polymer type. In addition, the second etch stop layer 35a may be formed to have a thickness of 500 mW to 5000 mW in consideration of the role of the etch stop and the insulation of the subsequent storage node contact plug.
다음으로, 실링질화막(36)을 포함한 전면에 제 2 층간절연막(37)을 형성하되, 제2층간절연막(37)은 전술한 것처럼 비트라인(35)에 적용되는 제2식각방지막(35a)에 따라 각각 다른 절연막을 이용한다. 그리고, 제2층간절연막(37)은 제2식각방지막(35a) 상부로 500Å∼10000Å의 두께로 형성한다.Next, a second interlayer insulating film 37 is formed on the entire surface including the sealing nitride film 36, and the second interlayer insulating film 37 is formed on the second etch stop layer 35a applied to the bit line 35 as described above. Therefore, different insulating films are used. The second interlayer insulating film 37 is formed to have a thickness of 500 kPa to 10,000 kPa above the second etch stop layer 35a.
도 2b에 도시된 바와 같이, 제 2 층간절연막(37)상에 감광막을 이용한 콘택마스크(도시 생략)를 형성한 후, 콘택마스크로 제2층간절연막(37)과 실링질화막(36)간의 식각선택비를 이용하여 실링질화막(36)에서 식각이 멈추도록 제 2 층간절연막(37)을 식각하여 비트라인(35) 사이를 노출시키는 콘택홀을 1차로 형성시킨다(이하 '1차 콘택홀(38)'이라 약칭함).As shown in FIG. 2B, after forming a contact mask (not shown) using a photoresist film on the second interlayer insulating film 37, an etching selection between the second interlayer insulating film 37 and the sealing nitride film 36 is performed by using a contact mask. By using the ratio, the second interlayer insulating layer 37 is etched to stop the etching in the sealing nitride layer 36 to form a first contact hole exposing between the bit lines 35 (hereinafter referred to as 'primary contact hole 38'). Abbreviated as ").
여기서, 콘택마스크는 홀형, 티형, 아이형, 라인형 및 바형 중에서 선택된 어느 하나를 포함하며, 콘택마스크를 이용한 식각 공정은 자기정렬 식각공정 또는 비트라인이 드러나지 않는 통상적인 콘택식각 공정을 포함한다.Here, the contact mask may include any one selected from a hole type, a tee type, an eye type, a line type, and a bar type, and the etching process using the contact mask includes a self-aligned etching process or a conventional contact etching process in which bit lines are not exposed.
또한, 1차 콘택홀(38)을 형성하기 위한 식각은 고밀도 및 중밀도 플라즈마원을 이용하는 식각챔버에서 이루어지되, 질화막계열의 제2식각방지막(35a)과 산화막계열의 제2층간절연막(37)을 사용하는 경우, Ar/C4F8/CH2F2, Ar/C4F8/O2, Ar/C4F8/CH3F, Ar/C4F8/CHF3, Ar/C5F8/O2의 가스조합과 위 가스조합의 다른 조합으로 건식식각한다.In addition, the etching for forming the primary contact hole 38 is performed in an etching chamber using a high density and medium density plasma source, the second etching prevention film 35a of the nitride film series and the second interlayer insulating film 37 of the oxide film series. When using Ar / C 4 F 8 / CH 2 F 2 , Ar / C 4 F 8 / O 2 , Ar / C 4 F 8 / CH 3 F, Ar / C 4 F 8 / CHF 3 , Ar / Dry etch with a gas combination of C 5 F 8 / O 2 and another combination of the above.
만약, 산화막계열의 제2식각방지막과 저유전율계 또는 폴리머계 제2층간절연막을 사용하는 경우, Ar/O2/N2/H2/CH4/C2H4/CxFy의 가스 조합으로 진행한다.If an oxide-based second etch stop layer and a low dielectric constant or polymer-based second interlayer insulating film are used, a gas of Ar / O 2 / N 2 / H 2 / CH 4 / C 2 H 4 / C x F y Proceed to the combination.
상술한 1차 콘택홀(38) 식각 공정은 1mtorr∼100mtorr의 압력하에서 진행한다.The primary contact hole 38 etching process described above proceeds under a pressure of 1 mtorr to 100 mtorr.
도 2c에 도시된 바와 같이, 콘택마스크를 제거하고, 전면에 스페이서 절연막(39), 예컨대 SiNx, SiO 및 SiON 중에서 선택된 어느 하나를 50Å∼1000Å의 두께로 증착한다. 이 때, 플라즈마인핸스드 화학기상증착법(Plasma Enhanced Chemical Vapor Deposition; PE-CVD)으로 증착하여 1차 콘택홀(38)의 바닥에 두껍게 증착되도록 한다.As shown in Fig. 2C, the contact mask is removed, and any one selected from the spacer insulating film 39, such as SiN x , SiO, and SiON, is deposited on the entire surface with a thickness of 50 kV to 1000 kV. At this time, the plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition; PE-CVD) to be deposited to be thickly deposited on the bottom of the primary contact hole (38).
도 2d에 도시된 바와 같이, 스페이서 절연막(39)을 전면식각하여 1차 콘택홀(38)의 측벽에 스페이서(40)를 형성한다. 이 때, 실링 질화막(36) 및 제 1 층간절연막(34)까지 함께 식각하여 제 1 폴리실리콘플러그(33)의 표면을 완전히 노출시키는 콘택홀을 형성시킨다(이하 '2차 콘택홀(41)'이라 약칭함).As illustrated in FIG. 2D, the spacer insulating layer 39 is etched to form a spacer 40 on the sidewall of the primary contact hole 38. At this time, the sealing nitride film 36 and the first interlayer insulating film 34 are etched together to form a contact hole for completely exposing the surface of the first polysilicon plug 33 (hereinafter referred to as 'secondary contact hole 41'). Abbreviated).
이 때, 스페이서를 형성하기 위한 전면식각은 1차 콘택홀(39) 형성과 동일한식각 조건에서 이루어지며, 2차 콘택홀(41)은 1차 콘택홀(39)을 포함하는 스토리지노드 콘택 플러그를 형성하기 위한 콘택홀이다.At this time, the front etching for forming the spacer is performed under the same etching conditions as the formation of the primary contact hole 39, the secondary contact hole 41 is a storage node contact plug including the primary contact hole (39) It is a contact hole for forming.
상술한 것처럼, 스페이서(40) 형성시 제1폴리실리콘플러그(33)를 노출시키므로, 워드라인(32)이 어택받는 공정을 한 번으로 감소시킨다.As described above, since the first polysilicon plug 33 is exposed when the spacer 40 is formed, the word line 32 is attacked once.
도 2e에 도시된 바와 같이, 2차 콘택홀(41)을 포함한 전면에 폴리실리콘을 증착 및 화학적기계적연마 또는 에치백하여 2차 콘택홀(41)에 매립되는 제2폴리실리콘 플러그 즉, 스토리지노드콘택플러그(42)를 형성한다.As shown in FIG. 2E, the second polysilicon plug, that is, the storage node, is embedded in the secondary contact hole 41 by depositing and chemically mechanically polishing or etching back the polysilicon on the front surface including the secondary contact hole 41. The contact plug 42 is formed.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명은 워드라인의 어택을 감소시켜 워드라인이 노출되는 현상을 억제하므로 스토리지노드 콘택플러그와 워드라인간의 접속을 방지하여 소자의 전기적 특성을 향상시킬 수 있는 효과가 있다.As described above, the present invention reduces the attack of the word line, thereby suppressing the exposure of the word line, thereby preventing the connection between the storage node contact plug and the word line, thereby improving the electrical characteristics of the device.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010072383A KR20030041550A (en) | 2001-11-20 | 2001-11-20 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010072383A KR20030041550A (en) | 2001-11-20 | 2001-11-20 | Method for fabricating semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20030041550A true KR20030041550A (en) | 2003-05-27 |
Family
ID=29570435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010072383A KR20030041550A (en) | 2001-11-20 | 2001-11-20 | Method for fabricating semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20030041550A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100576083B1 (en) * | 2003-12-26 | 2006-05-03 | 삼성전자주식회사 | Semiconductor device and method of manufacturing semiconductor device |
| US7326613B2 (en) | 2004-04-02 | 2008-02-05 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices having elongated contact plugs |
| KR100807114B1 (en) | 2006-06-30 | 2008-02-27 | 주식회사 하이닉스반도체 | Method for forming contact hole in semiconductor device |
| KR100825034B1 (en) * | 2006-02-21 | 2008-04-24 | 주식회사 하이닉스반도체 | Semiconductor device with nitride?nitride?oxide spacer and method for manufacturing the same |
-
2001
- 2001-11-20 KR KR1020010072383A patent/KR20030041550A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100576083B1 (en) * | 2003-12-26 | 2006-05-03 | 삼성전자주식회사 | Semiconductor device and method of manufacturing semiconductor device |
| US7326613B2 (en) | 2004-04-02 | 2008-02-05 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices having elongated contact plugs |
| US7547938B2 (en) | 2004-04-02 | 2009-06-16 | Samsung Electronics Co., Ltd. | Semiconductor devices having elongated contact plugs |
| KR100825034B1 (en) * | 2006-02-21 | 2008-04-24 | 주식회사 하이닉스반도체 | Semiconductor device with nitride?nitride?oxide spacer and method for manufacturing the same |
| KR100807114B1 (en) | 2006-06-30 | 2008-02-27 | 주식회사 하이닉스반도체 | Method for forming contact hole in semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6881659B2 (en) | Methods of forming self-aligned contact structures in semiconductor integrated circuit devices | |
| US6268252B1 (en) | Method of forming self-aligned contact pads on electrically conductive lines | |
| TW200522203A (en) | Method for fabricating semiconductor device | |
| KR20050038869A (en) | Method for fabrication of semiconductor device capable of forming fine pattern | |
| KR100616499B1 (en) | Method for fabrication of semiconductor device | |
| KR100390039B1 (en) | Method for forming the self aligned contact | |
| KR20030041550A (en) | Method for fabricating semiconductor device | |
| US6225216B1 (en) | Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide | |
| KR20060000912A (en) | Method for fabrication of semiconductor device | |
| KR101057759B1 (en) | Semiconductor device manufacturing method | |
| KR20050041263A (en) | Method for fabrication of semiconductor device | |
| KR100835506B1 (en) | Manufacturing method of semiconductor device | |
| KR100537187B1 (en) | Method for fabrication of semiconductor device | |
| KR100382542B1 (en) | method for manufacturing of semiconductor device | |
| KR100303318B1 (en) | method for forming self-aligned contact in semiconductor device | |
| KR20040038049A (en) | Method of forming contact in semiconductor device | |
| KR100910868B1 (en) | Method for fabrication of semiconductor device | |
| KR100429008B1 (en) | Method of forming contact hole of semiconductor device | |
| KR100695417B1 (en) | Method for fabrication of semiconductor device capable of forming fine pattern | |
| KR20030002110A (en) | Method for forming self aligned contact plug | |
| KR20030058636A (en) | A method for forming of a semiconductor device | |
| KR20000039691A (en) | Method of forming contact hole of semiconductor device | |
| KR20040057348A (en) | Method for fabrication of semiconductor device | |
| KR20040003960A (en) | Method for fabricating semiconductor device | |
| KR20040008620A (en) | Method for fabricating semiconductor device using hardmask |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |