KR100807114B1 - Method for forming contact hole in semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a contact hole of a semiconductor device that can simplify the process by reducing the aspect ratio due to the hard mask used in the landing plug contact forming process, the present invention is a substrate having a plurality of patterns Forming an etch barrier layer along an upper surface of the entire structure including the pattern; depositing an interlayer insulating film to cover the entire structure including the etch barrier layer; Planarizing the interlayer insulating film with a polishing stop layer, recessing the planarized interlayer insulating film so as to protrude the upper portion of the pattern, and depositing a hard mask to fill in the curvature formed by the recessed interlayer insulating film. And the hard mask so that the recessed interlayer insulating film formed between the patterns is exposed. Forming a contact hole in the semiconductor device by etching a hard disk pattern, removing the exposed interlayer insulating layer by performing an etching process using the hard mask pattern, and removing the hard mask pattern. Provide a method.

 Semiconductor Memory Devices, Landing Plugs, Storage Node Contact Plugs, Hard Masks

Description

Method for forming contact hole in semiconductor device {METHOD FOR FORMING CONTACT HOLE IN SEMICONDUCTOR DEVICE}

1 to 7 are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10 substrate 11 gate oxide film

12: polysilicon film 13: hard mask

14 gate electrode 15 spacer

16: junction region 17: nitride film

18: interlayer insulating film 18A: planarized interlayer insulating film

18B: recessed interlayer insulating film

18C: Patterned Interlayer Insulator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technology, and in particular, a method of forming a contact hole in a semiconductor device, and more particularly, a landing plug for interconnecting a lower electrode of a capacitor and an active region in a semiconductor memory device having a capacitor. plug) and a storage node contact plug.

Generally, in the DRAM device manufacturing process, a landing plug and a storage node contact plug are formed to interconnect the active region (source region) and the storage node, which is the lower electrode of the capacitor. It includes.

The landing plug contact hole (hereinafter referred to as a landing plug contact) in which the landing plug is to be formed has a hole type structure and a bar type structure. The double bar structure is characterized in that the thickness of the hard mask required for the Self Aligned Contact (SAC) process becomes very thick due to a separation process using a subsequent CMP (Chemical Mechanical Polishing) process.

Currently, the thickness of the gate electrode hard mask required to define a device of 60 nm or less is required to be approximately 2200 GPa or more. The reason is that the loss of the hard mask that is lost when the same etching conditions are applied due to the reduction of the line pattern is further increased.

For this reason, in the device manufacturing process of 60nm or less, the hard mask must be sufficiently thick to proceed with the process. However, when the thickness of the hard mask is increased, the aspect ratio is relatively increased, and thus, an etching process for forming a contact hole becomes difficult. Moreover, since the etching process for forming the contact hole uses a SAC process in which a large amount of polymer is generated, the increase of the etch target further increases the difficulty of the process.

Accordingly, the present invention has been proposed to solve the above-mentioned problems of the prior art, and a method for forming a contact hole in a semiconductor device which can simplify the process by reducing the aspect ratio due to the hard mask used in the landing plug contact forming process. The purpose is to provide.

According to an aspect of the present invention, there is provided a method including providing a substrate on which a plurality of patterns are formed, forming an etching barrier layer along an upper surface of an entire structure including the pattern, and forming the etching barrier. Depositing an interlayer insulating film so as to cover the entire structure including the layer, planarizing the interlayer insulating film with the etch barrier layer as a polishing stop layer, and recessing the planarized interlayer insulating film so as to protrude the pattern top. Depositing a hard mask to fill up the curvature formed by the recessed interlayer insulating film, and etching the hard mask to expose the recessed interlayer insulating film formed between the patterns to form a hard mask pattern. And removing the exposed interlayer insulating layer by performing an etching process using the hard mask pattern. And, providing a contact hole, forming a semiconductor device including a step of removing the hard mask pattern.

According to another aspect of the present invention, there is provided a substrate on which a gate electrode and a junction region are formed, and forming an etch barrier layer along an upper surface of the entire structure including the gate electrode. Depositing an interlayer insulating film to cover an entire structure including the etch barrier layer, planarizing the interlayer insulating film with the etch barrier layer as a polishing stop layer, and protruding an upper portion of the gate electrode. Recessing the planarized interlayer insulating film, depositing a hard mask to fill the curvature formed by the recessed interlayer insulating film, and exposing the recessed interlayer insulating film formed on the junction region to expose the hard mask. Etching the hard mask pattern, and performing an etching process using the hard mask pattern. Provides the group and removing the exposed interlayer insulating film, the contact hole forming method for a semiconductor device including a step of removing the hard mask pattern.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity and may be formed directly on other layers or substrates when referred to as being on another layer or substrate. Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

1 to 7 are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to a preferred embodiment of the present invention. For convenience of description, a cross-sectional view of a process for forming a landing plug contact of a DRAM device is illustrated as an example.

First, referring to FIG. 1, a semiconductor substrate 10 having an isolation layer (not shown), a gate electrode 14, and a junction region (source and drain regions) 16 defining active and inactive regions are provided. do. In this case, the gate electrode 14 may be formed of the gate oxide film 11, the polysilicon film 12, and the hard mask 13, and may be formed of tungsten or tungsten between the polysilicon film 12 and the hard mask 13. A silicide layer may be further formed. In addition, spacers 15 formed of an oxide film and an oxide film / nitride film are formed on both side walls of the gate electrode 14.

Subsequently, the nitride film 17 for SAC is deposited along the step of the upper surface of the entire structure including the gate electrode 14. In this case, the nitride film 17 functions as an etch barrier layer in the SAC process.

Subsequently, an interlayer insulating film 18 is deposited to cover the upper portion of the nitride film 17. In this case, the interlayer insulating film 18 is formed of an oxide film-based material. For example, it is formed of Boron Phosphorus Silicate Glass (BPSG), Phosphorus Silicate Glass (PSG), Tetra Ethyle Ortho Silicate (TEOS), or the like.

Next, as shown in FIG. 2, the CMP process 19 is performed to planarize the interlayer insulating film 18 (see FIG. 1). In this case, the CMP process 19 is performed to stop polishing on the nitride film 17 using a slurry having an etching selectivity between the nitride film and the oxide film. Here, '18A' represents a planarized interlayer insulating film.

Subsequently, as shown in FIG. 3, an etching process 20 is performed to recess the interlayer insulating layer 18A (see FIG. 2) to a predetermined depth so that the upper portion of the gate electrode 14 protrudes. In this case, the etching process 20 may be performed by a wet etching process or a dry etching process, and in the case of the wet etching process, dilute HF (DHF) -H by ex-situ or in-situ. _It is carried out using HF solution diluted with 20- or BOE (Buffered Oxide Etchant)-a solution of HF and NH ₄ F mixed. Here, '18B' represents a recessed interlayer insulating film.

Meanwhile, the thickness of the interlayer insulating film 18B remaining in FIG. 3 must be thicker than the thickness remaining in the CMP process for forming a subsequent landing plug. The reason for this is to prevent a short circuit between the landing plugs after the CMP process for forming the landing plugs.

Next, as shown in FIG. 4, the hard mask 21 is formed so that the bending caused by the interlayer insulating film 18B recessed in FIG. 3 is completely filled. At this time, the hard mask 21 is formed of a material having a sufficient selectivity with respect to the nitride film and the oxide film. Preferably, it is formed of an amorphous carbon layer or a photosensitive film containing silicon. For example, when the hard mask 21 is formed of an amorphous carbon film, it is preferable to further form a SiON film having an etching selectivity on the amorphous carbon film. In addition, instead of the SiON film, an oxide film-based, for example, a TEOS (Tetra Ethyle Ortho Silicate) film may be further formed on the amorphous carbon film.

Subsequently, when irregularities are present on the hard mask 21, a planar OBARC film (Organic Bottom Anti Reflective Coating layer) may be further applied for uniformity.

Subsequently, as shown in FIG. 5, the photoresist film is coated on the hard mask 21 (see FIG. 4), and then the photoresist pattern 22 is formed by performing an exposure and development process using a photo mask.

Next, an etching process 23 using the photosensitive film pattern 22 is performed to form the hard mask pattern 21A. In this case, the etching process 23 is performed under an etching condition having a sufficient selectivity between the nitride film and the oxide film so that the hard mask 21 existing between the gate electrodes 14 is also completely removed.

Next, as illustrated in FIG. 6, an etching process 24 using the hard mask pattern 21A as an etching barrier layer is performed to remove the interlayer insulating film 18B (see FIG. 5) existing between the gate electrodes 14. do. At this time, since the thickness of the interlayer insulating film 18B is primarily reduced by the etching process 20 of FIG. 3, the thickness of the interlayer insulating film 18B can be easily removed. Here, '22A' represents a state in which the thickness of the photoresist pattern 22 is reduced during the process, and '18C' represents an interlayer insulating layer from which a region where a landing plug is to be formed is removed.

Subsequently, as shown in FIG. 7, the photoresist pattern 22A (see FIG. 6) and the hard mask pattern 21A (see FIG. 6) are removed.

Next, the nitride film 17 is etched. As a result, a landing plug contact through which the junction region 16 is exposed is formed.

Subsequently, the landing plug material is embedded such that the landing plug contact is embedded, and then a CMP process is performed to form the landing plug. In this case, a polysilicon film is used as the landing plug material.

In the above, the present invention has been described with respect to the process of forming a landing plug contact through an embodiment. However, the present invention may also be applied to a process of forming a contact hole for a storage node contact plug using the SAC process.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the following effects can be obtained.

First, the aspect ratio of the landing plug contact forming process may be reduced by reducing the thickness of the insulating layer etched during the etching process for forming the landing plug contact.

Second, according to the present invention, by reducing the aspect ratio during the etching process for forming the landing plug contact, the problem of the landing plug contact is not opened by reducing the etch target during the etching process for forming the landing plug contact It is possible to prevent device defects due to.

Third, according to the present invention, by reducing the etching target during the etching process for forming the landing plug contact, the loss amount of the hard mask for the gate electrode is reduced, so that the gate electrode during the thickness-landing plug contact forming process of the hard mask for the initial gate electrode In consideration of the loss amount of the hard mask, the increase in thickness may be reduced by depositing the hard mask for the gate electrode sufficiently thick in advance before the landing plug contact forming process.

Claims (10)

Providing a substrate having a plurality of patterns formed thereon; Forming an etch barrier layer along an upper surface of the entire structure including the pattern; Depositing an interlayer insulating film overlying the entire structure including the etch barrier layer; Planarizing the interlayer insulating film with the etch barrier layer as a polishing stop layer; Recessing the planarized interlayer insulating layer to protrude the upper portion of the pattern; Depositing a hard mask to fill in the curvature formed by the recessed interlayer insulating film; Etching the hard mask to expose the recessed interlayer insulating layer formed between the patterns to form a hard mask pattern; Performing an etching process using the hard mask pattern to remove the exposed interlayer insulating film; And Removing the hard mask pattern Contact hole forming method of a semiconductor device comprising a. Providing a substrate having a gate electrode and a junction region formed thereon; Forming an etch barrier layer along an upper surface of the entire structure including the gate electrode; Depositing an interlayer insulating film overlying the entire structure including the etch barrier layer; Planarizing the interlayer insulating film with the etch barrier layer as a polishing stop layer; Recessing the planarized interlayer insulating layer so that an upper portion of the gate electrode protrudes; Depositing a hard mask to fill in the curvature formed by the recessed interlayer insulating film; Etching the hard mask to expose the recessed interlayer insulating layer formed on the junction region to form a hard mask pattern; Performing an etching process using the hard mask pattern to remove the exposed interlayer insulating film; And Removing the hard mask pattern Contact hole forming method of a semiconductor device comprising a. The method according to claim 1 or 2, And planarizing the interlayer insulating layer using a slurry having an etch selectivity between the interlayer insulating layer and the etch barrier layer. The method according to claim 1 or 2, And recessing the planarized interlayer insulating layer is performed by a dry or wet etching process. The method of claim 4, wherein The wet etching process is a contact hole forming method of a semiconductor device performed by DHF or BOE solution. The method according to claim 1 or 2, The hard mask may be formed of a material having a high etching selectivity between the etch barrier layer and the interlayer insulating layer. The method of claim 6, And the hard mask is formed of an amorphous carbon film or a photosensitive film containing silicon. The method of claim 6, And the hard mask has a laminated structure of an amorphous carbon film and a SiON film or a laminated structure of an amorphous carbon film and a TEOS film. The method according to claim 1 or 2, And depositing an OBARC layer on the hard mask after depositing the hard mask. The method according to claim 1 or 2, And forming the etch barrier layer as a nitride layer.

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